llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v Author: Zeyi Xu (zeyi2) <details> <summary>Changes</summary> Add experimental MC support for the remaining ACLIC v0.20 extensions. This completes MC support for the ACLIC v0.20 extensions. --- Patch is 22.54 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/218108.diff 12 Files Affected: - (modified) clang/test/Driver/print-supported-extensions-riscv.c (+4) - (modified) clang/test/Preprocessor/riscv-target-features.c (+46) - (modified) llvm/docs/RISCVUsage.md (+1-1) - (modified) llvm/docs/ReleaseNotes.md (+1-7) - (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+18) - (modified) llvm/lib/Target/RISCV/RISCVSystemOperands.td (+6) - (modified) llvm/test/CodeGen/RISCV/attributes.ll (+16) - (modified) llvm/test/CodeGen/RISCV/features-info.ll (+4) - (modified) llvm/test/MC/RISCV/attribute-arch.s (+12) - (modified) llvm/test/MC/RISCV/machine-csr-names.s (+42) - (modified) llvm/test/MC/RISCV/supervisor-csr-names.s (+42) - (modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+4) ``````````diff diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 857bb8831d672..bbd0c2bebee9d 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -272,13 +272,17 @@ // CHECK-NEXT: zvzip 0.1 'Zvzip' (Vector Reordering Structured Data) // CHECK-NEXT: smcsps 0.20 'Smcsps' (Conditional Stack Pointer Swap at Machine Level) // CHECK-NEXT: smehv 0.20 'Smehv' (Synchronous Exception Hardware Vectoring at Machine Level) +// CHECK-NEXT: smidctrl 0.20 'Smidctrl' (Interrupt Domain Control Interface at Machine Level) // CHECK-NEXT: smijt 0.20 'Smijt' (Interrupt Jump Table at Machine Level) // CHECK-NEXT: smip 0.20 'Smip' (Support for Interrupt Handler Push/Pop at Machine Level) +// CHECK-NEXT: smnip 0.20 'Smnip' (Nested Interrupt Preemption Support at Machine Level) // CHECK-NEXT: smpmpmt 0.6 'Smpmpmt' (PMP-based Memory Types Extension) // CHECK-NEXT: sscsps 0.20 'Sscsps' (Conditional Stack Pointer Swap at Supervisor Level) // CHECK-NEXT: ssehv 0.20 'Ssehv' (Synchronous Exception Hardware Vectoring at Supervisor Level) +// CHECK-NEXT: ssidctrl 0.20 'Ssidctrl' (Interrupt Domain Control Interface at Supervisor Level) // CHECK-NEXT: ssijt 0.20 'Ssijt' (Interrupt Jump Table at Supervisor Level) // CHECK-NEXT: ssip 0.20 'Ssip' (Support for Interrupt Handler Push/Pop at Supervisor Level) +// CHECK-NEXT: ssnip 0.20 'Ssnip' (Nested Interrupt Preemption Support at Supervisor Level) // CHECK-NEXT: svukte 1.0 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses) // CHECK-NEXT: xqccmt 0.1 'Xqccmt' (Qualcomm 16-bit Table Jump) // CHECK-NEXT: xsfmclic 0.1 'XSfmclic' (SiFive CLIC Machine-mode CSRs) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 21147121a8c05..ee7f72b3b5ff7 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -40,9 +40,11 @@ // CHECK-NOT: __riscv_smdbltrp {{.*$}} // CHECK-NOT: __riscv_smehv {{.*$}} // CHECK-NOT: __riscv_smepmp {{.*$}} +// CHECK-NOT: __riscv_smidctrl {{.*$}} // CHECK-NOT: __riscv_smijt {{.*$}} // CHECK-NOT: __riscv_smip {{.*$}} // CHECK-NOT: __riscv_smmpm{{.*$}} +// CHECK-NOT: __riscv_smnip {{.*$}} // CHECK-NOT: __riscv_smnpm{{.*$}} // CHECK-NOT: __riscv_smpmpmt {{.*$}} // CHECK-NOT: __riscv_smrnmi {{.*$}} @@ -57,8 +59,10 @@ // CHECK-NOT: __riscv_ssctr{{.*$}} // CHECK-NOT: __riscv_ssdbltrp {{.*$}} // CHECK-NOT: __riscv_ssehv {{.*$}} +// CHECK-NOT: __riscv_ssidctrl {{.*$}} // CHECK-NOT: __riscv_ssijt {{.*$}} // CHECK-NOT: __riscv_ssip {{.*$}} +// CHECK-NOT: __riscv_ssnip {{.*$}} // CHECK-NOT: __riscv_ssnpm{{.*$}} // CHECK-NOT: __riscv_sspm{{.*$}} // CHECK-NOT: __riscv_ssqosid{{.*$}} @@ -1413,6 +1417,26 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-SMEPMP-EXT %s // CHECK-SMEPMP-EXT: __riscv_smepmp 1000000{{$}} +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_smidctrl0p20 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SMIDCTRL-EXT %s +// RUN: %clang --target=riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_smidctrl0p20 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SMIDCTRL-EXT %s +// CHECK-SMIDCTRL-EXT: __riscv_smaia 1000000{{$}} +// CHECK-SMIDCTRL-EXT: __riscv_smcsrind 1000000{{$}} +// CHECK-SMIDCTRL-EXT: __riscv_smidctrl 20000{{$}} + +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_ssidctrl0p20 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSIDCTRL-EXT %s +// RUN: %clang --target=riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_ssidctrl0p20 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSIDCTRL-EXT %s +// CHECK-SSIDCTRL-EXT: __riscv_ssaia 1000000{{$}} +// CHECK-SSIDCTRL-EXT: __riscv_sscsrind 1000000{{$}} +// CHECK-SSIDCTRL-EXT: __riscv_ssidctrl 20000{{$}} + // RUN: %clang --target=riscv32 -menable-experimental-extensions \ // RUN: -march=rv32i_smijt0p20 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-SMIJT-EXT %s @@ -1463,6 +1487,28 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-SSIP-EXT %s // CHECK-SSIP-EXT: __riscv_ssip 20000{{$}} +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_smnip0p20 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SMNIP-EXT %s +// RUN: %clang --target=riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_smnip0p20 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SMNIP-EXT %s +// CHECK-SMNIP-EXT: __riscv_smaia 1000000{{$}} +// CHECK-SMNIP-EXT: __riscv_smcsrind 1000000{{$}} +// CHECK-SMNIP-EXT: __riscv_smidctrl 20000{{$}} +// CHECK-SMNIP-EXT: __riscv_smnip 20000{{$}} + +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_ssnip0p20 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSNIP-EXT %s +// RUN: %clang --target=riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_ssnip0p20 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSNIP-EXT %s +// CHECK-SSNIP-EXT: __riscv_ssaia 1000000{{$}} +// CHECK-SSNIP-EXT: __riscv_sscsrind 1000000{{$}} +// CHECK-SSNIP-EXT: __riscv_ssidctrl 20000{{$}} +// CHECK-SSNIP-EXT: __riscv_ssnip 20000{{$}} + // RUN: %clang --target=riscv32 -menable-experimental-extensions \ // RUN: -march=rv32ismpmpmt0p6 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-SMPMPMT %s diff --git a/llvm/docs/RISCVUsage.md b/llvm/docs/RISCVUsage.md index 6c6173d46d631..7879ea5d90888 100644 --- a/llvm/docs/RISCVUsage.md +++ b/llvm/docs/RISCVUsage.md @@ -346,7 +346,7 @@ The primary goal of experimental support is to assist in the process of ratifica : LLVM implements the [1.0 release specification](https://github.com/riscv/riscv-cfi/releases/tag/v1.0). -`experimental-smcsps`, `experimental-sscsps`, `experimental-smijt`, `experimental-ssijt`, `experimental-smehv`, `experimental-ssehv`, `experimental-smip`, `experimental-ssip` +`experimental-smcsps`, `experimental-sscsps`, `experimental-smijt`, `experimental-ssijt`, `experimental-smehv`, `experimental-ssehv`, `experimental-smip`, `experimental-ssip`, `experimental-smidctrl`, `experimental-ssidctrl`, `experimental-smnip`, `experimental-ssnip` : LLVM implements the [0.20 release specification](https://github.com/riscv/riscv-fast-interrupt/releases/tag/v0.20). diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 051d726b7aa8d..e2e41f8eec63c 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -113,15 +113,9 @@ Makes programs 10x faster by doing Special New Thing. ### Changes to the RISC-V Backend -* Added experimental MC support for the `Smcsps` and `Sscsps` - conditional stack pointer swap extensions. +* Added experimental MC support for the ACLIC v0.20 extensions. * Adds experimental assembler/CodeGen support for the `Zilx` (Indexed Integer Load) extension. -* Added experimental MC support for the `Smijt` and `Ssijt` interrupt jump - table extensions and the `Smehv` and `Ssehv` synchronous exception hardware - vectoring extensions. -* Added experimental MC support for the `Smip` and `Ssip` interrupt handler - push/pop extensions. * Bump Svukte extension to 1.0. * Remove experimental from Zicfiss. diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index fe70dd0450074..90222c9fc620e 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1099,6 +1099,15 @@ def FeatureStdExtSsdbltrp def FeatureStdExtSmepmp : RISCVExtension<1, 0, "Enhanced Physical Memory Protection">; +def FeatureStdExtSmidctrl + : RISCVExperimentalExtension<0, 20, + "Interrupt Domain Control Interface at Machine Level", + [FeatureStdExtSmcsrind, FeatureStdExtSmaia]>; +def FeatureStdExtSsidctrl + : RISCVExperimentalExtension<0, 20, + "Interrupt Domain Control Interface at Supervisor Level", + [FeatureStdExtSscsrind, FeatureStdExtSsaia]>; + def FeatureStdExtSmijt : RISCVExperimentalExtension<0, 20, "Interrupt Jump Table at Machine Level">; @@ -1130,6 +1139,15 @@ def HasStdExtSsip : Predicate<"Subtarget->hasStdExtSsip()">, "'Ssip' (Support for Interrupt Handler Push/Pop at " "Supervisor Level)">; +def FeatureStdExtSmnip + : RISCVExperimentalExtension<0, 20, + "Nested Interrupt Preemption Support at Machine Level", + [FeatureStdExtSmidctrl]>; +def FeatureStdExtSsnip + : RISCVExperimentalExtension<0, 20, + "Nested Interrupt Preemption Support at Supervisor Level", + [FeatureStdExtSsidctrl]>; + def FeatureStdExtSmpmpmt : RISCVExperimentalExtension<0, 6, "PMP-based Memory Types Extension">; diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td index 421a3ae37338d..94e9261077401 100644 --- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td +++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td @@ -166,6 +166,9 @@ def : SysReg<"scause", 0x142>; def : SysReg<"stval", 0x143>; def : DeprecatedSysRegName<"sbadaddr", 0x143>; def : SysReg<"sip", 0x144>; +def : SysReg<"sistatus", 0x146>; +def : SysReg<"sithreshold", 0x147>; +def : SysReg<"stopsi", 0x148>; def : SysReg<"sspcs", 0x149>; def : SysReg<"siph", 0x154, RV32Only=true>; def : SysReg<"stopei", 0x15C>; @@ -379,6 +382,9 @@ def : SysReg<"mcause", 0x342>; def : SysReg<"mtval", 0x343>; def : DeprecatedSysRegName<"mbadaddr", 0x343>; def : SysReg<"mip", 0x344>; +def : SysReg<"mistatus", 0x346>; +def : SysReg<"mithreshold", 0x347>; +def : SysReg<"mtopsi", 0x348>; def : SysReg<"mspcs", 0x349>; def : SysReg<"mtinst", 0x34A>; def : SysReg<"mtval2", 0x34B>; diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 0d304edb9aacb..e852358dbf20f 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -131,12 +131,16 @@ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-smcsps %s -o - | FileCheck --check-prefix=RV32SMCSPS %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-sscsps %s -o - | FileCheck --check-prefix=RV32SSCSPS %s ; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMEPMP %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-smidctrl %s -o - | FileCheck --check-prefix=RV32SMIDCTRL %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssidctrl %s -o - | FileCheck --check-prefix=RV32SSIDCTRL %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-smijt %s -o - | FileCheck --check-prefix=RV32SMIJT %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssijt %s -o - | FileCheck --check-prefix=RV32SSIJT %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-smehv %s -o - | FileCheck --check-prefix=RV32SMEHV %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssehv %s -o - | FileCheck --check-prefix=RV32SSEHV %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-smip %s -o - | FileCheck --check-prefix=RV32SMIP %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssip %s -o - | FileCheck --check-prefix=RV32SSIP %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-smnip %s -o - | FileCheck --check-prefix=RV32SMNIP %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssnip %s -o - | FileCheck --check-prefix=RV32SSNIP %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-smpmpmt %s -o - | FileCheck --check-prefixes=CHECK,RV32SMPMPMT %s ; RUN: llc -mtriple=riscv32 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV32SMRNMI %s ; RUN: llc -mtriple=riscv32 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s @@ -306,12 +310,16 @@ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-smcsps %s -o - | FileCheck --check-prefix=RV64SMCSPS %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-sscsps %s -o - | FileCheck --check-prefix=RV64SSCSPS %s ; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMEPMP %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-smidctrl %s -o - | FileCheck --check-prefix=RV64SMIDCTRL %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssidctrl %s -o - | FileCheck --check-prefix=RV64SSIDCTRL %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-smijt %s -o - | FileCheck --check-prefix=RV64SMIJT %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssijt %s -o - | FileCheck --check-prefix=RV64SSIJT %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-smehv %s -o - | FileCheck --check-prefix=RV64SMEHV %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssehv %s -o - | FileCheck --check-prefix=RV64SSEHV %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-smip %s -o - | FileCheck --check-prefix=RV64SMIP %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssip %s -o - | FileCheck --check-prefix=RV64SSIP %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-smnip %s -o - | FileCheck --check-prefix=RV64SMNIP %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssnip %s -o - | FileCheck --check-prefix=RV64SSNIP %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-smpmpmt %s -o - | FileCheck --check-prefixes=CHECK,RV64SMPMPMT %s ; RUN: llc -mtriple=riscv64 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV64SMRNMI %s ; RUN: llc -mtriple=riscv64 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s @@ -491,12 +499,16 @@ ; RV32SMCSPS: .attribute 5, "rv32i2p1_smcsps0p20" ; RV32SSCSPS: .attribute 5, "rv32i2p1_smcsps0p20_sscsps0p20" ; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0" +; RV32SMIDCTRL: .attribute 5, "rv32i2p1_smaia1p0_smcsrind1p0_smidctrl0p20" +; RV32SSIDCTRL: .attribute 5, "rv32i2p1_ssaia1p0_sscsrind1p0_ssidctrl0p20" ; RV32SMIJT: .attribute 5, "rv32i2p1_smijt0p20" ; RV32SSIJT: .attribute 5, "rv32i2p1_ssijt0p20" ; RV32SMEHV: .attribute 5, "rv32i2p1_smehv0p20_smijt0p20" ; RV32SSEHV: .attribute 5, "rv32i2p1_ssehv0p20_ssijt0p20" ; RV32SMIP: .attribute 5, "rv32i2p1_smip0p20" ; RV32SSIP: .attribute 5, "rv32i2p1_ssip0p20" +; RV32SMNIP: .attribute 5, "rv32i2p1_smaia1p0_smcsrind1p0_smidctrl0p20_smnip0p20" +; RV32SSNIP: .attribute 5, "rv32i2p1_ssaia1p0_sscsrind1p0_ssidctrl0p20_ssnip0p20" ; RV32SMPMPMT: .attribute 5, "rv32i2p1_smpmpmt0p6" ; RV32SMRNMI: .attribute 5, "rv32i2p1_smrnmi1p0" ; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0" @@ -663,12 +675,16 @@ ; RV64SMCSPS: .attribute 5, "rv64i2p1_smcsps0p20" ; RV64SSCSPS: .attribute 5, "rv64i2p1_smcsps0p20_sscsps0p20" ; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0" +; RV64SMIDCTRL: .attribute 5, "rv64i2p1_smaia1p0_smcsrind1p0_smidctrl0p20" +; RV64SSIDCTRL: .attribute 5, "rv64i2p1_ssaia1p0_sscsrind1p0_ssidctrl0p20" ; RV64SMIJT: .attribute 5, "rv64i2p1_smijt0p20" ; RV64SSIJT: .attribute 5, "rv64i2p1_ssijt0p20" ; RV64SMEHV: .attribute 5, "rv64i2p1_smehv0p20_smijt0p20" ; RV64SSEHV: .attribute 5, "rv64i2p1_ssehv0p20_ssijt0p20" ; RV64SMIP: .attribute 5, "rv64i2p1_smip0p20" ; RV64SSIP: .attribute 5, "rv64i2p1_ssip0p20" +; RV64SMNIP: .attribute 5, "rv64i2p1_smaia1p0_smcsrind1p0_smidctrl0p20_smnip0p20" +; RV64SSNIP: .attribute 5, "rv64i2p1_ssaia1p0_sscsrind1p0_ssidctrl0p20_ssnip0p20" ; RV64SMPMPMT: .attribute 5, "rv64i2p1_smpmpmt0p6" ; RV64SMRNMI: .attribute 5, "rv64i2p1_smrnmi1p0" ; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0" diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index b756a2f862b7d..4128d40524b67 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -26,13 +26,17 @@ ; CHECK-NEXT: experimental-rvm23u32 - RISC-V experimental-rvm23u32 profile. ; CHECK-NEXT: experimental-smcsps - 'Smcsps' (Conditional Stack Pointer Swap at Machine Level). ; CHECK-NEXT: experimental-smehv - 'Smehv' (Synchronous Exception Hardware Vectoring at Machine Level). +; CHECK-NEXT: experimental-smidctrl - 'Smidctrl' (Interrupt Domain Control Interface at Machine Level). ; CHECK-NEXT: experimental-smijt - 'Smijt' (Interrupt Jump Table at Machine Level). ; CHECK-NEXT: experimental-smip - 'Smip' (Support for Interrupt Handler Push/Pop at Machine Level). +; CHECK-NEXT: experimental-smnip - 'Smnip' (Nested Interrupt Preemption Support at Machine Level). ; CHECK-NEXT: experimental-smpmpmt - 'Smpmpmt' (PMP-based Memory Types Extension). ; CHECK-NEXT: experimental-sscsps - 'Sscsps' (Conditional Stack Pointer Swap at Supervisor Level). ; CHECK-NEXT: experimental-ssehv - 'Ssehv' (Synchronous Exception Hardware Vectoring at Supervisor Level). +; CHECK-NEXT: experimental-ssidctrl - 'Ssidctrl' (Interrupt Domain Control Interface at Supervisor Level). ; CHECK-NEXT: experimental-ssijt - 'Ssijt' (Interrupt Jump Table at Supervisor Level). ; CHECK-NEXT: experimental-ssip - 'Ssip' (Support for Interrupt Handler Push/Pop at Supervisor Level). +; CHECK-NEXT: experimental-ssnip - 'Ssnip' (Nested Interrupt Preemption Support at Supervisor Level). ; CHECK-NEXT: experimental-svukte - 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses). ; CHECK-NEXT: experimental-xqccmt - 'Xqccmt' (Qualcomm 16-bit Table Jump). ; CHECK-NEXT: experimental-xsfmclic - 'XSfmclic' (SiFive CLIC Machine-mode CSRs). diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index f802e91b312b4..adb242d53faaf 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -363,6 +363,12 @@ .attribute arch, "rv32i_smepmp1p0" # CHECK: attribute 5, "rv32i2p1_smepmp1p0" +.attribute arch, "rv32i_smidctrl0p20" +# CHECK: attribute 5, "rv32i2p1_smaia1p0_smcsrind1p0_smidctrl0p20" + +.attribute arch, "rv32i_ssidctrl0p20" +# CHECK: attribute 5, "rv32i2p1_ssaia1p0_sscsrind1p0_ssidctrl0p20" + .attribute arch, "rv32i_smijt0p20" # CHECK: attribute 5, "rv32i2p1_smijt0p20" @@ -381,6 +387,12 @@ .attribute arch, "rv32i_ssip0p20" # CHECK: attribute 5, "rv32i2p1_ssip0p20" +.attribute arch, "rv32i_smnip0p20" +# CHECK: attribute 5, "rv32i2p1_smaia1p0_smcsrind1p0_smidctrl0p20_smnip0p20" + +.attribute arch, "rv32i_ssnip0p20" +# CHECK: attribute 5, "rv32i2p1_ssaia1p0_sscsrind1p0_ssidctrl0p20_ssnip0p20" + .attribute arch, "rv32i_smpmpmt0p6" # CHECK: attribute 5, "rv32i2p1_smpmpmt0p6" diff --git a/llvm/test/MC/RISCV/machine-csr-names.s b/llvm/test/MC/RISCV/machine-csr-names.s index f115c234a3428..9b0630476a94a 100644 --- a/llvm/test/MC/RISCV/machine-csr-names.s +++ b/llvm/test/MC/RISCV/machine-csr-names.s @@ -271,6 +271,48 @@ csrrs t1, mip, zero # uimm12 csrrs t2, 0x344, zero +# mistatus +# name +# CHECK-INST: csrrs t1, mistatus, zero +# CHECK-ENC: encoding: [0x73,0x23,0x60,0x34] +# CHECK-INST-ALIAS: csrr t1, mistatus +# uimm12 +# CHECK-INST: csrrs t2, mistatus, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x60,0x34] +# CHECK-INST-ALIAS: csrr t2, mistatus +# name +csrrs t1, mistatus, zero +# uimm12 +csrrs t2, 0x346, zero + +# mithreshold +# name +# CHECK-INST: csrrs t1, mithreshold, zero +# CHECK-ENC: encoding: [0x73,0x23,0x70,0x34] +# CHECK-INST-ALIAS: csrr t1, mithreshold +# uimm12 +# CHECK-INST: csrrs t2, mithreshold, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x70,0x34] +# CHECK-INST-ALIAS: csrr t2, mithreshold +# name +csrrs t1, mithreshold, zero +# uimm12 +csrrs t2, 0x347, zero + +# mtopsi +# name +# CHECK-INST: csrrs t1, mtopsi... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/218108 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
