================ @@ -5208,6 +5208,12 @@ bool TokenAnnotator::spaceRequiredBefore(const AnnotatedLine &Line, const bool IsVerilog = Style.isVerilog(); assert(!IsVerilog || !IsCpp); + // TableGen lexes the lower bound of a bit range as a negative integer. ---------------- HazardyKnusperkeks wrote:
I don't understand what this comment wants to tell me. And from what I understood from the issue there is not a problem, like we generate invalid or changed code, but it just looks odd, so the TableGen lexer shouldn't be mentioned here at all, or am I mistaken? https://github.com/llvm/llvm-project/pull/215837 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
