================ @@ -5208,6 +5208,12 @@ bool TokenAnnotator::spaceRequiredBefore(const AnnotatedLine &Line, const bool IsVerilog = Style.isVerilog(); assert(!IsVerilog || !IsCpp); + // TableGen lexes the lower bound of a bit range as a negative integer. ---------------- fyrsta7 wrote:
Thank you for the clarification. You're right that this is a formatting issue and does not change TableGen semantics. I've reworded the code comment to describe the intended compact formatting directly, and updated the commit message and PR description accordingly. https://github.com/llvm/llvm-project/pull/215837 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
