================
@@ -71,36 +99,78 @@ def rvv_vwabda_vl : RVSDNode<"VWABDA_VL",
SDT_RISCVVWIntTernOp_VL, [SDNPCommuta
def rvv_vwabdau_vl : RVSDNode<"VWABDAU_VL", SDT_RISCVVWIntTernOp_VL,
[SDNPCommutative]>;
} // let HasPassthruOp = true, HasMaskOp = true
-// These instructions are defined for SEW=8 and SEW=16, otherwise the
instruction
-// encoding is reserved.
-defvar ABDIntVectors = !filter(vti, AllIntegerVectors, !or(!eq(vti.SEW, 8),
- !eq(vti.SEW, 16)));
+// The widening instructions are defined for SEW=8 and SEW=16, otherwise the
+// instruction encoding is reserved.
defvar ABDAIntVectors = !filter(vtiTowti, AllWidenableIntVectors,
!or(!eq(vtiTowti.Vti.SEW, 8),
!eq(vtiTowti.Vti.SEW, 16)));
+multiclass VPatTernaryW_VX_VS2First<string intrinsic, string instruction,
+ list<VTypeInfoToWide> vtilist> {
+ foreach vtiTowti = vtilist in {
+ defvar vti = vtiTowti.Vti;
+ defvar wti = vtiTowti.Wti;
+ let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
+ GetVTypePredicates<wti>.Predicates) in
+ defm : VPatTernaryWithPolicy<intrinsic, instruction,
+ "V"#vti.ScalarSuffix,
+ wti.Vector, vti.Vector, vti.Scalar,
+ vti.Mask, vti.Log2SEW, vti.LMul,
+ wti.RegClass, vti.RegClass,
+ vti.ScalarRegClass>;
+ }
+}
+
+multiclass VPatWidenABDVL_VV_VX<SDNode op, string instruction> {
+ defm : VPatWidenMultiplyAddVL_VV<op, instruction, ABDAIntVectors>;
+ foreach vtiTowti = ABDAIntVectors in {
+ defvar vti = vtiTowti.Vti;
+ defvar wti = vtiTowti.Wti;
+ let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
+ GetVTypePredicates<wti>.Predicates) in
+ def : Pat<(op (SplatPat XLenVT:$rs1),
+ (vti.Vector vti.RegClass:$rs2),
+ (wti.Vector wti.RegClass:$rd),
+ (vti.Mask VMV0:$vm), VLOpFrag),
+ (!cast<Instruction>(instruction#"_VX_"#vti.LMul.MX#"_MASK")
+ wti.RegClass:$rd, vti.RegClass:$rs2,
+ vti.ScalarRegClass:$rs1, (vti.Mask VMV0:$vm), GPR:$vl,
+ vti.Log2SEW, TAIL_AGNOSTIC)>;
+ }
+}
+
let Predicates = [HasStdExtZvabd] in {
-defm : VPatBinarySDNode_VV<abds, "PseudoVABD", ABDIntVectors>;
-defm : VPatBinarySDNode_VV<abdu, "PseudoVABDU", ABDIntVectors>;
+defm : VPatBinarySDNode_VV_VX<abds, "PseudoVABD", AllIntegerVectors>;
+defm : VPatBinarySDNode_VV_VX<abdu, "PseudoVABDU", AllIntegerVectors>;
-defm : VPatBinaryVL_VV<riscv_abds_vl, "PseudoVABD", ABDIntVectors>;
-defm : VPatBinaryVL_VV<riscv_abdu_vl, "PseudoVABDU", ABDIntVectors>;
+defm : VPatBinaryVL_VV_VX<riscv_abds_vl, "PseudoVABD", AllIntegerVectors>;
+defm : VPatBinaryVL_VV_VX<riscv_abdu_vl, "PseudoVABDU", AllIntegerVectors>;
-defm : VPatUnaryV_V<"int_riscv_vabs", "PseudoVABS", AllIntegerVectors>;
-defm : VPatBinaryV_VV<"int_riscv_vabd", "PseudoVABD", ABDIntVectors>;
-defm : VPatBinaryV_VV<"int_riscv_vabdu", "PseudoVABDU", ABDIntVectors>;
+defm : VPatBinaryV_VV_VX<"int_riscv_vabd", "PseudoVABD", AllIntegerVectors>;
+defm : VPatBinaryV_VV_VX<"int_riscv_vabdu", "PseudoVABDU", AllIntegerVectors>;
defm : VPatTernaryW_VV<"int_riscv_vwabda", "PseudoVWABDA", ABDAIntVectors>;
defm : VPatTernaryW_VV<"int_riscv_vwabdau", "PseudoVWABDAU", ABDAIntVectors>;
+defm : VPatTernaryW_VX_VS2First<"int_riscv_vwabda", "PseudoVWABDA",
+ ABDAIntVectors>;
+defm : VPatTernaryW_VX_VS2First<"int_riscv_vwabdau", "PseudoVWABDAU",
+ ABDAIntVectors>;
foreach vti = AllIntegerVectors in {
- def : Pat<(vti.Vector (abs (vti.Vector vti.RegClass:$rs2))),
- (!cast<Instruction>("PseudoVABS_V_"#vti.LMul.MX)
- (vti.Vector (IMPLICIT_DEF)),
- vti.RegClass:$rs2, vti.AVL, vti.Log2SEW, TA_MA)>;
+ let Predicates = GetVTypePredicates<vti>.Predicates in {
+ def : Pat<(vti.Vector (abs (vti.Vector vti.RegClass:$rs2))),
+ (!cast<Instruction>("PseudoVABD_VX_"#vti.LMul.MX)
+ (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2,
+ (XLenVT X0), vti.AVL, vti.Log2SEW, TA_MA)>;
+ def : Pat<(riscv_abs_vl (vti.Vector vti.RegClass:$rs2),
----------------
wangpc-pp wrote:
I think we don't need `riscv_abs_vl` either and we can emit `VABDS_VL` in
`lowerABS`. Then we can reduce some duplicated patterns.
https://github.com/llvm/llvm-project/pull/218576
_______________________________________________
cfe-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
