================
@@ -71,36 +99,78 @@ def rvv_vwabda_vl : RVSDNode<"VWABDA_VL",
SDT_RISCVVWIntTernOp_VL, [SDNPCommuta
def rvv_vwabdau_vl : RVSDNode<"VWABDAU_VL", SDT_RISCVVWIntTernOp_VL,
[SDNPCommutative]>;
} // let HasPassthruOp = true, HasMaskOp = true
-// These instructions are defined for SEW=8 and SEW=16, otherwise the
instruction
-// encoding is reserved.
-defvar ABDIntVectors = !filter(vti, AllIntegerVectors, !or(!eq(vti.SEW, 8),
- !eq(vti.SEW, 16)));
+// The widening instructions are defined for SEW=8 and SEW=16, otherwise the
+// instruction encoding is reserved.
defvar ABDAIntVectors = !filter(vtiTowti, AllWidenableIntVectors,
!or(!eq(vtiTowti.Vti.SEW, 8),
!eq(vtiTowti.Vti.SEW, 16)));
+multiclass VPatTernaryW_VX_VS2First<string intrinsic, string instruction,
+ list<VTypeInfoToWide> vtilist> {
+ foreach vtiTowti = vtilist in {
+ defvar vti = vtiTowti.Vti;
+ defvar wti = vtiTowti.Wti;
+ let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
+ GetVTypePredicates<wti>.Predicates) in
+ defm : VPatTernaryWithPolicy<intrinsic, instruction,
+ "V"#vti.ScalarSuffix,
+ wti.Vector, vti.Vector, vti.Scalar,
+ vti.Mask, vti.Log2SEW, vti.LMul,
+ wti.RegClass, vti.RegClass,
+ vti.ScalarRegClass>;
+ }
+}
+
+multiclass VPatWidenABDVL_VV_VX<SDNode op, string instruction> {
+ defm : VPatWidenMultiplyAddVL_VV<op, instruction, ABDAIntVectors>;
+ foreach vtiTowti = ABDAIntVectors in {
+ defvar vti = vtiTowti.Vti;
+ defvar wti = vtiTowti.Wti;
+ let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
----------------
wangpc-pp wrote:
Ditto.
https://github.com/llvm/llvm-project/pull/218576
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