llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v Author: SiHuaN (sihuan) <details> <summary>Changes</summary> Add SelectionDAG and intrinsic support for the RISC-V P multiply-parts operations, which widen one element out of every pair: `pmul.h.b00`, `pmul.w.h01`, `mul.h11`, `mul.w00` and their unsigned and signed-unsigned forms. The element width is implied by the overloaded types, so the intrinsic names only carry the element selection and the signedness: `llvm.riscv.pmul.00` covers both `pmul.h.b00` and `pmul.w.h00`, and `llvm.riscv.mul.00` covers `mul.h00` and `mul.w00`. The packed operands are `LLVMSubdivide2VectorType` of the result, so only the result type is mangled. Three shapes need legalizing rather than a pattern. On RV32 a 64-bit packed result lives in a GPR pair, so each half is computed with the 32-bit form of the same product, which for a `<2 x i32>` result is the scalar form. On RV64 there is no halfword multiply-parts instruction, so the `<2 x i16>` operands are widened to `<4 x i16>` and the wanted product is the first element of the packed result. On RV32 there is no word multiply-parts instruction, so the selected elements are extracted and multiplied into a GPR pair with `wmul`/`wmulu`/`wmulsu`. Also adds the Clang builtins and the `riscv_packed_simd.h` wrappers. --- Patch is 57.80 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/218875.diff 10 Files Affected: - (modified) clang/include/clang/Basic/BuiltinsRISCV.td (+43) - (modified) clang/lib/CodeGen/TargetBuiltins/RISCV.cpp (+131) - (modified) clang/lib/Headers/riscv_packed_simd.h (+43) - (modified) cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c (+281) - (modified) llvm/include/llvm/IR/IntrinsicsRISCV.td (+30) - (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+156) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfoP.td (+44) - (modified) llvm/test/CodeGen/RISCV/rvp-simd-32.ll (+202) - (modified) llvm/test/CodeGen/RISCV/rvp-simd-64.ll (+378) - (modified) llvm/test/CodeGen/RISCV/rvp-simd-intrinsic-invalid.ll (+26) ``````````diff diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td b/clang/include/clang/Basic/BuiltinsRISCV.td index 89dbf736f4435..fd48c0d01a0f5 100644 --- a/clang/include/clang/Basic/BuiltinsRISCV.td +++ b/clang/include/clang/Basic/BuiltinsRISCV.td @@ -318,6 +318,49 @@ def pmulq_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<4, short>, _Vector<4, def pmulqr_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<4, short>, _Vector<4, short>)">; def pmulq_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<2, int>)">; def pmulqr_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<2, int>)">; +// Packed Multiply Parts (32-bit) +def pmul_b00_i16x2 : RISCVBuiltin<"_Vector<2, short>(_Vector<4, signed char>, _Vector<4, signed char>)">; +def pmul_b01_i16x2 : RISCVBuiltin<"_Vector<2, short>(_Vector<4, signed char>, _Vector<4, signed char>)">; +def pmul_b11_i16x2 : RISCVBuiltin<"_Vector<2, short>(_Vector<4, signed char>, _Vector<4, signed char>)">; +def pmulu_b00_u16x2 : RISCVBuiltin<"_Vector<2, unsigned short>(_Vector<4, unsigned char>, _Vector<4, unsigned char>)">; +def pmulu_b01_u16x2 : RISCVBuiltin<"_Vector<2, unsigned short>(_Vector<4, unsigned char>, _Vector<4, unsigned char>)">; +def pmulu_b11_u16x2 : RISCVBuiltin<"_Vector<2, unsigned short>(_Vector<4, unsigned char>, _Vector<4, unsigned char>)">; +def pmulsu_b00_i16x2 : RISCVBuiltin<"_Vector<2, short>(_Vector<4, signed char>, _Vector<4, unsigned char>)">; +def pmulsu_b11_i16x2 : RISCVBuiltin<"_Vector<2, short>(_Vector<4, signed char>, _Vector<4, unsigned char>)">; +def mul_h00_i32 : RISCVBuiltin<"int(_Vector<2, short>, _Vector<2, short>)">; +def mul_h01_i32 : RISCVBuiltin<"int(_Vector<2, short>, _Vector<2, short>)">; +def mul_h11_i32 : RISCVBuiltin<"int(_Vector<2, short>, _Vector<2, short>)">; +def mulu_h00_u32 : RISCVBuiltin<"unsigned int(_Vector<2, unsigned short>, _Vector<2, unsigned short>)">; +def mulu_h01_u32 : RISCVBuiltin<"unsigned int(_Vector<2, unsigned short>, _Vector<2, unsigned short>)">; +def mulu_h11_u32 : RISCVBuiltin<"unsigned int(_Vector<2, unsigned short>, _Vector<2, unsigned short>)">; +def mulsu_h00_i32 : RISCVBuiltin<"int(_Vector<2, short>, _Vector<2, unsigned short>)">; +def mulsu_h11_i32 : RISCVBuiltin<"int(_Vector<2, short>, _Vector<2, unsigned short>)">; + +// Packed Multiply Parts (64-bit) +def pmul_b00_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<8, signed char>, _Vector<8, signed char>)">; +def pmul_b01_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<8, signed char>, _Vector<8, signed char>)">; +def pmul_b11_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<8, signed char>, _Vector<8, signed char>)">; +def pmulu_b00_u16x4 : RISCVBuiltin<"_Vector<4, unsigned short>(_Vector<8, unsigned char>, _Vector<8, unsigned char>)">; +def pmulu_b01_u16x4 : RISCVBuiltin<"_Vector<4, unsigned short>(_Vector<8, unsigned char>, _Vector<8, unsigned char>)">; +def pmulu_b11_u16x4 : RISCVBuiltin<"_Vector<4, unsigned short>(_Vector<8, unsigned char>, _Vector<8, unsigned char>)">; +def pmulsu_b00_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<8, signed char>, _Vector<8, unsigned char>)">; +def pmulsu_b11_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<8, signed char>, _Vector<8, unsigned char>)">; +def pmul_h00_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<4, short>, _Vector<4, short>)">; +def pmul_h01_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<4, short>, _Vector<4, short>)">; +def pmul_h11_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<4, short>, _Vector<4, short>)">; +def pmulu_h00_u32x2 : RISCVBuiltin<"_Vector<2, unsigned int>(_Vector<4, unsigned short>, _Vector<4, unsigned short>)">; +def pmulu_h01_u32x2 : RISCVBuiltin<"_Vector<2, unsigned int>(_Vector<4, unsigned short>, _Vector<4, unsigned short>)">; +def pmulu_h11_u32x2 : RISCVBuiltin<"_Vector<2, unsigned int>(_Vector<4, unsigned short>, _Vector<4, unsigned short>)">; +def pmulsu_h00_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<4, short>, _Vector<4, unsigned short>)">; +def pmulsu_h11_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<4, short>, _Vector<4, unsigned short>)">; +def mul_w00_i64 : RISCVBuiltin<"int64_t(_Vector<2, int>, _Vector<2, int>)">; +def mul_w01_i64 : RISCVBuiltin<"int64_t(_Vector<2, int>, _Vector<2, int>)">; +def mul_w11_i64 : RISCVBuiltin<"int64_t(_Vector<2, int>, _Vector<2, int>)">; +def mulu_w00_u64 : RISCVBuiltin<"uint64_t(_Vector<2, unsigned int>, _Vector<2, unsigned int>)">; +def mulu_w01_u64 : RISCVBuiltin<"uint64_t(_Vector<2, unsigned int>, _Vector<2, unsigned int>)">; +def mulu_w11_u64 : RISCVBuiltin<"uint64_t(_Vector<2, unsigned int>, _Vector<2, unsigned int>)">; +def mulsu_w00_i64 : RISCVBuiltin<"int64_t(_Vector<2, int>, _Vector<2, unsigned int>)">; +def mulsu_w11_i64 : RISCVBuiltin<"int64_t(_Vector<2, int>, _Vector<2, unsigned int>)">; // Packed Sign and Zero Extend (32-bit) def psext_b_i16x2 : RISCVBuiltin<"_Vector<2, short>(_Vector<2, short>)">; diff --git a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp index 88fedecbee504..1415a6446e733 100644 --- a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp +++ b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp @@ -1625,6 +1625,137 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, IntrinsicTypes = {ResultType, Ops.back()->getType()}; break; } + // Packed Multiply Parts. + case RISCV::BI__builtin_riscv_pmul_b00_i16x2: + case RISCV::BI__builtin_riscv_pmul_b01_i16x2: + case RISCV::BI__builtin_riscv_pmul_b11_i16x2: + case RISCV::BI__builtin_riscv_pmulu_b00_u16x2: + case RISCV::BI__builtin_riscv_pmulu_b01_u16x2: + case RISCV::BI__builtin_riscv_pmulu_b11_u16x2: + case RISCV::BI__builtin_riscv_pmulsu_b00_i16x2: + case RISCV::BI__builtin_riscv_pmulsu_b11_i16x2: + case RISCV::BI__builtin_riscv_pmul_b00_i16x4: + case RISCV::BI__builtin_riscv_pmul_b01_i16x4: + case RISCV::BI__builtin_riscv_pmul_b11_i16x4: + case RISCV::BI__builtin_riscv_pmulu_b00_u16x4: + case RISCV::BI__builtin_riscv_pmulu_b01_u16x4: + case RISCV::BI__builtin_riscv_pmulu_b11_u16x4: + case RISCV::BI__builtin_riscv_pmulsu_b00_i16x4: + case RISCV::BI__builtin_riscv_pmulsu_b11_i16x4: + case RISCV::BI__builtin_riscv_pmul_h00_i32x2: + case RISCV::BI__builtin_riscv_pmul_h01_i32x2: + case RISCV::BI__builtin_riscv_pmul_h11_i32x2: + case RISCV::BI__builtin_riscv_pmulu_h00_u32x2: + case RISCV::BI__builtin_riscv_pmulu_h01_u32x2: + case RISCV::BI__builtin_riscv_pmulu_h11_u32x2: + case RISCV::BI__builtin_riscv_pmulsu_h00_i32x2: + case RISCV::BI__builtin_riscv_pmulsu_h11_i32x2: { + switch (BuiltinID) { + default: + llvm_unreachable("unexpected builtin ID"); + case RISCV::BI__builtin_riscv_pmul_b00_i16x2: + case RISCV::BI__builtin_riscv_pmul_b00_i16x4: + case RISCV::BI__builtin_riscv_pmul_h00_i32x2: + ID = Intrinsic::riscv_pmul_00; + break; + case RISCV::BI__builtin_riscv_pmul_b01_i16x2: + case RISCV::BI__builtin_riscv_pmul_b01_i16x4: + case RISCV::BI__builtin_riscv_pmul_h01_i32x2: + ID = Intrinsic::riscv_pmul_01; + break; + case RISCV::BI__builtin_riscv_pmul_b11_i16x2: + case RISCV::BI__builtin_riscv_pmul_b11_i16x4: + case RISCV::BI__builtin_riscv_pmul_h11_i32x2: + ID = Intrinsic::riscv_pmul_11; + break; + case RISCV::BI__builtin_riscv_pmulu_b00_u16x2: + case RISCV::BI__builtin_riscv_pmulu_b00_u16x4: + case RISCV::BI__builtin_riscv_pmulu_h00_u32x2: + ID = Intrinsic::riscv_pmulu_00; + break; + case RISCV::BI__builtin_riscv_pmulu_b01_u16x2: + case RISCV::BI__builtin_riscv_pmulu_b01_u16x4: + case RISCV::BI__builtin_riscv_pmulu_h01_u32x2: + ID = Intrinsic::riscv_pmulu_01; + break; + case RISCV::BI__builtin_riscv_pmulu_b11_u16x2: + case RISCV::BI__builtin_riscv_pmulu_b11_u16x4: + case RISCV::BI__builtin_riscv_pmulu_h11_u32x2: + ID = Intrinsic::riscv_pmulu_11; + break; + case RISCV::BI__builtin_riscv_pmulsu_b00_i16x2: + case RISCV::BI__builtin_riscv_pmulsu_b00_i16x4: + case RISCV::BI__builtin_riscv_pmulsu_h00_i32x2: + ID = Intrinsic::riscv_pmulsu_00; + break; + case RISCV::BI__builtin_riscv_pmulsu_b11_i16x2: + case RISCV::BI__builtin_riscv_pmulsu_b11_i16x4: + case RISCV::BI__builtin_riscv_pmulsu_h11_i32x2: + ID = Intrinsic::riscv_pmulsu_11; + break; + } + + IntrinsicTypes = {ResultType}; + break; + } + + // Scalar Multiply Parts. + case RISCV::BI__builtin_riscv_mul_h00_i32: + case RISCV::BI__builtin_riscv_mul_w00_i64: + case RISCV::BI__builtin_riscv_mul_h01_i32: + case RISCV::BI__builtin_riscv_mul_w01_i64: + case RISCV::BI__builtin_riscv_mul_h11_i32: + case RISCV::BI__builtin_riscv_mul_w11_i64: + case RISCV::BI__builtin_riscv_mulu_h00_u32: + case RISCV::BI__builtin_riscv_mulu_w00_u64: + case RISCV::BI__builtin_riscv_mulu_h01_u32: + case RISCV::BI__builtin_riscv_mulu_w01_u64: + case RISCV::BI__builtin_riscv_mulu_h11_u32: + case RISCV::BI__builtin_riscv_mulu_w11_u64: + case RISCV::BI__builtin_riscv_mulsu_h00_i32: + case RISCV::BI__builtin_riscv_mulsu_w00_i64: + case RISCV::BI__builtin_riscv_mulsu_h11_i32: + case RISCV::BI__builtin_riscv_mulsu_w11_i64: { + switch (BuiltinID) { + default: + llvm_unreachable("unexpected builtin ID"); + case RISCV::BI__builtin_riscv_mul_h00_i32: + case RISCV::BI__builtin_riscv_mul_w00_i64: + ID = Intrinsic::riscv_mul_00; + break; + case RISCV::BI__builtin_riscv_mul_h01_i32: + case RISCV::BI__builtin_riscv_mul_w01_i64: + ID = Intrinsic::riscv_mul_01; + break; + case RISCV::BI__builtin_riscv_mul_h11_i32: + case RISCV::BI__builtin_riscv_mul_w11_i64: + ID = Intrinsic::riscv_mul_11; + break; + case RISCV::BI__builtin_riscv_mulu_h00_u32: + case RISCV::BI__builtin_riscv_mulu_w00_u64: + ID = Intrinsic::riscv_mulu_00; + break; + case RISCV::BI__builtin_riscv_mulu_h01_u32: + case RISCV::BI__builtin_riscv_mulu_w01_u64: + ID = Intrinsic::riscv_mulu_01; + break; + case RISCV::BI__builtin_riscv_mulu_h11_u32: + case RISCV::BI__builtin_riscv_mulu_w11_u64: + ID = Intrinsic::riscv_mulu_11; + break; + case RISCV::BI__builtin_riscv_mulsu_h00_i32: + case RISCV::BI__builtin_riscv_mulsu_w00_i64: + ID = Intrinsic::riscv_mulsu_00; + break; + case RISCV::BI__builtin_riscv_mulsu_h11_i32: + case RISCV::BI__builtin_riscv_mulsu_w11_i64: + ID = Intrinsic::riscv_mulsu_11; + break; + } + + IntrinsicTypes = {ResultType, Ops[0]->getType()}; + break; + } // Zk builtins diff --git a/clang/lib/Headers/riscv_packed_simd.h b/clang/lib/Headers/riscv_packed_simd.h index 318900805043c..581ffb91f4b84 100644 --- a/clang/lib/Headers/riscv_packed_simd.h +++ b/clang/lib/Headers/riscv_packed_simd.h @@ -851,6 +851,49 @@ __packed_binary_builtin(pmulq_i16x4, int16x4_t, __builtin_riscv_pmulq_i16x4) __packed_binary_builtin(pmulqr_i16x4, int16x4_t, __builtin_riscv_pmulqr_i16x4) __packed_binary_builtin(pmulq_i32x2, int32x2_t, __builtin_riscv_pmulq_i32x2) __packed_binary_builtin(pmulqr_i32x2, int32x2_t, __builtin_riscv_pmulqr_i32x2) +/* Packed Multiply Parts (32-bit) */ +__packed_binary_builtin_mixed(pmul_b00_i16x2, int16x2_t, int8x4_t, int8x4_t, __builtin_riscv_pmul_b00_i16x2) +__packed_binary_builtin_mixed(pmul_b01_i16x2, int16x2_t, int8x4_t, int8x4_t, __builtin_riscv_pmul_b01_i16x2) +__packed_binary_builtin_mixed(pmul_b11_i16x2, int16x2_t, int8x4_t, int8x4_t, __builtin_riscv_pmul_b11_i16x2) +__packed_binary_builtin_mixed(pmulu_b00_u16x2, uint16x2_t, uint8x4_t, uint8x4_t, __builtin_riscv_pmulu_b00_u16x2) +__packed_binary_builtin_mixed(pmulu_b01_u16x2, uint16x2_t, uint8x4_t, uint8x4_t, __builtin_riscv_pmulu_b01_u16x2) +__packed_binary_builtin_mixed(pmulu_b11_u16x2, uint16x2_t, uint8x4_t, uint8x4_t, __builtin_riscv_pmulu_b11_u16x2) +__packed_binary_builtin_mixed(pmulsu_b00_i16x2, int16x2_t, int8x4_t, uint8x4_t, __builtin_riscv_pmulsu_b00_i16x2) +__packed_binary_builtin_mixed(pmulsu_b11_i16x2, int16x2_t, int8x4_t, uint8x4_t, __builtin_riscv_pmulsu_b11_i16x2) +__packed_binary_builtin_mixed(mul_h00_i32, int32_t, int16x2_t, int16x2_t, __builtin_riscv_mul_h00_i32) +__packed_binary_builtin_mixed(mul_h01_i32, int32_t, int16x2_t, int16x2_t, __builtin_riscv_mul_h01_i32) +__packed_binary_builtin_mixed(mul_h11_i32, int32_t, int16x2_t, int16x2_t, __builtin_riscv_mul_h11_i32) +__packed_binary_builtin_mixed(mulu_h00_u32, uint32_t, uint16x2_t, uint16x2_t, __builtin_riscv_mulu_h00_u32) +__packed_binary_builtin_mixed(mulu_h01_u32, uint32_t, uint16x2_t, uint16x2_t, __builtin_riscv_mulu_h01_u32) +__packed_binary_builtin_mixed(mulu_h11_u32, uint32_t, uint16x2_t, uint16x2_t, __builtin_riscv_mulu_h11_u32) +__packed_binary_builtin_mixed(mulsu_h00_i32, int32_t, int16x2_t, uint16x2_t, __builtin_riscv_mulsu_h00_i32) +__packed_binary_builtin_mixed(mulsu_h11_i32, int32_t, int16x2_t, uint16x2_t, __builtin_riscv_mulsu_h11_i32) + +/* Packed Multiply Parts (64-bit) */ +__packed_binary_builtin_mixed(pmul_b00_i16x4, int16x4_t, int8x8_t, int8x8_t, __builtin_riscv_pmul_b00_i16x4) +__packed_binary_builtin_mixed(pmul_b01_i16x4, int16x4_t, int8x8_t, int8x8_t, __builtin_riscv_pmul_b01_i16x4) +__packed_binary_builtin_mixed(pmul_b11_i16x4, int16x4_t, int8x8_t, int8x8_t, __builtin_riscv_pmul_b11_i16x4) +__packed_binary_builtin_mixed(pmulu_b00_u16x4, uint16x4_t, uint8x8_t, uint8x8_t, __builtin_riscv_pmulu_b00_u16x4) +__packed_binary_builtin_mixed(pmulu_b01_u16x4, uint16x4_t, uint8x8_t, uint8x8_t, __builtin_riscv_pmulu_b01_u16x4) +__packed_binary_builtin_mixed(pmulu_b11_u16x4, uint16x4_t, uint8x8_t, uint8x8_t, __builtin_riscv_pmulu_b11_u16x4) +__packed_binary_builtin_mixed(pmulsu_b00_i16x4, int16x4_t, int8x8_t, uint8x8_t, __builtin_riscv_pmulsu_b00_i16x4) +__packed_binary_builtin_mixed(pmulsu_b11_i16x4, int16x4_t, int8x8_t, uint8x8_t, __builtin_riscv_pmulsu_b11_i16x4) +__packed_binary_builtin_mixed(pmul_h00_i32x2, int32x2_t, int16x4_t, int16x4_t, __builtin_riscv_pmul_h00_i32x2) +__packed_binary_builtin_mixed(pmul_h01_i32x2, int32x2_t, int16x4_t, int16x4_t, __builtin_riscv_pmul_h01_i32x2) +__packed_binary_builtin_mixed(pmul_h11_i32x2, int32x2_t, int16x4_t, int16x4_t, __builtin_riscv_pmul_h11_i32x2) +__packed_binary_builtin_mixed(pmulu_h00_u32x2, uint32x2_t, uint16x4_t, uint16x4_t, __builtin_riscv_pmulu_h00_u32x2) +__packed_binary_builtin_mixed(pmulu_h01_u32x2, uint32x2_t, uint16x4_t, uint16x4_t, __builtin_riscv_pmulu_h01_u32x2) +__packed_binary_builtin_mixed(pmulu_h11_u32x2, uint32x2_t, uint16x4_t, uint16x4_t, __builtin_riscv_pmulu_h11_u32x2) +__packed_binary_builtin_mixed(pmulsu_h00_i32x2, int32x2_t, int16x4_t, uint16x4_t, __builtin_riscv_pmulsu_h00_i32x2) +__packed_binary_builtin_mixed(pmulsu_h11_i32x2, int32x2_t, int16x4_t, uint16x4_t, __builtin_riscv_pmulsu_h11_i32x2) +__packed_binary_builtin_mixed(mul_w00_i64, int64_t, int32x2_t, int32x2_t, __builtin_riscv_mul_w00_i64) +__packed_binary_builtin_mixed(mul_w01_i64, int64_t, int32x2_t, int32x2_t, __builtin_riscv_mul_w01_i64) +__packed_binary_builtin_mixed(mul_w11_i64, int64_t, int32x2_t, int32x2_t, __builtin_riscv_mul_w11_i64) +__packed_binary_builtin_mixed(mulu_w00_u64, uint64_t, uint32x2_t, uint32x2_t, __builtin_riscv_mulu_w00_u64) +__packed_binary_builtin_mixed(mulu_w01_u64, uint64_t, uint32x2_t, uint32x2_t, __builtin_riscv_mulu_w01_u64) +__packed_binary_builtin_mixed(mulu_w11_u64, uint64_t, uint32x2_t, uint32x2_t, __builtin_riscv_mulu_w11_u64) +__packed_binary_builtin_mixed(mulsu_w00_i64, int64_t, int32x2_t, uint32x2_t, __builtin_riscv_mulsu_w00_i64) +__packed_binary_builtin_mixed(mulsu_w11_i64, int64_t, int32x2_t, uint32x2_t, __builtin_riscv_mulsu_w11_i64) /* Packed Narrowing Clip Pair (32-bit) */ __packed_binary_builtin_cast(pnclipp_i8x4, int16x2_t, int8x4_t, __builtin_riscv_pnclipp_i8x4) diff --git a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c index 75dcb796b66cd..262194d3eb08f 100644 --- a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c +++ b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c @@ -3406,3 +3406,284 @@ int32x2_t test_pnclipp_i32x2(int64_t a, int64_t b) { uint32x2_t test_pnclipup_u32x2(uint64_t a, uint64_t b) { return __riscv_pnclipup_u32x2(a, b); } + +// Packed Multiply Parts. +// CHECK-LABEL: test_pmul_b00_i16x2: +// RV32: pmul.h.b00 +// RV64: pmul.h.b00 +int16x2_t test_pmul_b00_i16x2(int8x4_t a, int8x4_t b) { + return __riscv_pmul_b00_i16x2(a, b); +} + +// CHECK-LABEL: test_pmul_b01_i16x2: +// RV32: pmul.h.b01 +// RV64: pmul.h.b01 +int16x2_t test_pmul_b01_i16x2(int8x4_t a, int8x4_t b) { + return __riscv_pmul_b01_i16x2(a, b); +} + +// CHECK-LABEL: test_pmul_b11_i16x2: +// RV32: pmul.h.b11 +// RV64: pmul.h.b11 +int16x2_t test_pmul_b11_i16x2(int8x4_t a, int8x4_t b) { + return __riscv_pmul_b11_i16x2(a, b); +} + +// CHECK-LABEL: test_pmulu_b00_u16x2: +// RV32: pmulu.h.b00 +// RV64: pmulu.h.b00 +uint16x2_t test_pmulu_b00_u16x2(uint8x4_t a, uint8x4_t b) { + return __riscv_pmulu_b00_u16x2(a, b); +} + +// CHECK-LABEL: test_pmulu_b01_u16x2: +// RV32: pmulu.h.b01 +// RV64: pmulu.h.b01 +uint16x2_t test_pmulu_b01_u16x2(uint8x4_t a, uint8x4_t b) { + return __riscv_pmulu_b01_u16x2(a, b); +} + +// CHECK-LABEL: test_pmulu_b11_u16x2: +// RV32: pmulu.h.b11 +// RV64: pmulu.h.b11 +uint16x2_t test_pmulu_b11_u16x2(uint8x4_t a, uint8x4_t b) { + return __riscv_pmulu_b11_u16x2(a, b); +} + +// CHECK-LABEL: test_pmulsu_b00_i16x2: +// RV32: pmulsu.h.b00 +// RV64: pmulsu.h.b00 +int16x2_t test_pmulsu_b00_i16x2(int8x4_t a, uint8x4_t b) { + return __riscv_pmulsu_b00_i16x2(a, b); +} + +// CHECK-LABEL: test_pmulsu_b11_i16x2: +// RV32: pmulsu.h.b11 +// RV64: pmulsu.h.b11 +int16x2_t test_pmulsu_b11_i16x2(int8x4_t a, uint8x4_t b) { + return __riscv_pmulsu_b11_i16x2(a, b); +} + +// CHECK-LABEL: test_mul_h00_i32: +// RV32: mul.h00 +// RV64: pmul.w.h00 +int32_t test_mul_h00_i32(int16x2_t a, int16x2_t b) { + return __riscv_mul_h00_i32(a, b); +} + +// CHECK-LABEL: test_mul_h01_i32: +// RV32: mul.h01 +// RV64: pmul.w.h01 +int32_t test_mul_h01_i32(int16x2_t a, int16x2_t b) { + return __riscv_mul_h01_i32(a, b); +} + +// CHECK-LABEL: test_mul_h11_i32: +// RV32: mul.h11 +// RV64: pmul.w.h11 +int32_t test_mul_h11_i32(int16x2_t a, int16x2_t b) { + return __riscv_mul_h11_i32(a, b); +} + +// CHECK-LABEL: test_mulu_h00_u32: +// RV32: mulu.h00 +// RV64: pmulu.w.h00 +uint32_t test_mulu_h00_u32(uint16x2_t a, uint16x2_t b) { + return __riscv_mulu_h00_u32(a, b); +} + +// CHECK-LABEL: test_mulu_h01_u32: +// RV32: mulu.h01 +// RV64: pmulu.w.h01 +uint32_t test_mulu_h01_u32(uint16x2_t a, uint16x2_t b) { + return __riscv_mulu_h01_u32(a, b); +} + +// CHECK-LABEL: test_mulu_h11_u32: +// RV32: mulu.h11 +// RV64: pmulu.w.h11 +uint32_t test_mulu_h11_u32(uint16x2_t a, uint16x2_t b) { + return __riscv_mulu_h11_u32(a, b); +} + +// CHECK-LABEL: test_mulsu_h00_i32: +// RV32: mulsu.h00 +// RV64: pmulsu.w.h00 +int32_t test_mulsu_h00_i32(int16x2_t a, uint16x2_t b) { + return __riscv_mulsu_h00_i32(a, b); +} + +// CHECK-LABEL: test_mulsu_h11_i32: +// RV32: mulsu.h11 +// RV64: pmulsu.w.h11 +int32_t test_mulsu_h11_i32(int16x2_t a, uint16x2_t b) { + return __riscv_mulsu_h11_i32(a, b); +} + +// CHECK-LABEL: test_pmul_b00_i16x4: +// RV32-COUNT-2: pmul.h.b00 +// RV64: pmul.h.b00 +int16x4_t test_pmul_b00_i16x4(int8x8_t a, int8x8_t b) { + return __riscv_pmul_b00_i16x4(a, b); +} + +// CHECK-LABEL: test_pmul_b01_i16x4: +// RV32-COUNT-2: pmul.h.b01 +// RV64: pmul.h.b01 +int16x4_t test_pmul_b01_i16x4(int8x8_t a, int8x8_t b) { + return __riscv_pmul_b01_i16x4(a, b); +} + +// CHECK-LABEL: test_pmul_b11_i16x4: +// RV32-COUNT-2: pmul.h.b11 +// RV64: pmul.h.b11 +int16x4_t test_pmul_b11_i16x4(int8x8_t a, int8x8_t b) { + return __riscv_pmul_b11_i16x4(a, b); +} + +// CHECK-LABEL: test_pmulu_b00_u16x4: +// RV32-COUNT-2: pmulu.h.b00 +// RV64: pmulu.h.b00 +uint16x4_t test_pmulu_b00_u16x4(uint8x8_t a, uint8x8_t b) { + return __riscv_pmulu_b00_u16x4(a, b); +} + +// CHECK-LABEL: test_pmulu_b01_u16x4: +// RV32-COUNT-2: pmulu.h.b01 +// RV64: pmulu.h.b01 +uint16x4_t test_pmulu_b01_u16x4(uint8x8_t a, uint8x8_t b) { + return __riscv_pmulu_b01_u16x4(a, b); +} + +// CHECK-LABEL: test_pmulu_b11_u16x4: +// RV32-COUNT-2: pmulu.h.b11 ... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/218875 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
