================
@@ -2431,10 +2433,11 @@ SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
ArgValue = convertValVTToLocVT(DAG, DL, VA, ArgValue);
if (VA.isRegLoc()) {
- // In XPLINK64, for the 128-bit vararg case, ArgValue is bitcasted to a
- // MVT::i128 type. We decompose the 128-bit type to a pair of its high
- // and low values.
- if (VA.getLocVT() == MVT::i128)
+ // i128 in a GR128 register pair (e.g. R2Q) must be decomposed into
+ // hi/lo GPR halves. i128 assigned to a VR128 vector register (V24-V31)
+ // is passed directly — do not decompose in that case.
----------------
uweigand wrote:
I think we should keep the comment that i128 in R2Q can only happen due to the
128-bit vararg handling.
But that raises the question: this used to be done only for f128 and vectors.
With the new logic, should it also be done for i128? What is the ABI for i128
as unnamed arg?
https://github.com/llvm/llvm-project/pull/223026
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