https://github.com/topperc created https://github.com/llvm/llvm-project/pull/237500
These registers have hardcoded usages within the compiler and I don't believe it's worth the effort to make them reservable. We issued some errors when x1 or x2 were reserved and needed, but I don't know it was complete. Fixes #237076. >From aa1451f0c28338dde9d47308cde0c2d1a4b02485 Mon Sep 17 00:00:00 2001 From: Craig Topper <[email protected]> Date: Fri, 30 Oct 2026 23:28:49 -0700 Subject: [PATCH] [RISCV] Remove ffixed-x1/x2/x5/x6/x7 These registers have hardcoded usages within the compiler and I don't believe it's worth the effort to make them reservable. We issued some errors when x1 or x2 were reserved and needed, but I don't know it was complete. Fixes #237076. --- clang/include/clang/Options/Options.td | 6 +- clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 5 - clang/test/Driver/riscv-fixed-x-register.c | 66 +----- llvm/lib/Target/RISCV/RISCVFeatures.td | 3 +- llvm/test/CodeGen/RISCV/features-info.ll | 5 - .../RISCV/machine-outliner-reserved-regs.mir | 214 ++++++++++-------- .../test/CodeGen/RISCV/reserved-reg-errors.ll | 6 - llvm/test/CodeGen/RISCV/reserved-regs.ll | 12 - 8 files changed, 130 insertions(+), 187 deletions(-) diff --git a/clang/include/clang/Options/Options.td b/clang/include/clang/Options/Options.td index 4275eba62bac30..e272d40ee0e5bb 100644 --- a/clang/include/clang/Options/Options.td +++ b/clang/include/clang/Options/Options.td @@ -5982,7 +5982,11 @@ def mno_bti_at_return_twice : Flag<["-"], "mno-bti-at-return-twice">, HelpText<"Do not add a BTI instruction after a setjmp or other" " return-twice construct (Arm/AArch64 only)">; -foreach i = {1-7,9-15,18,20-28} in +foreach i = {1,2,5-7} in + def ffixed_x#i : Flag<["-"], "ffixed-x"#i>, Group<m_Group>, + HelpText<"Reserve the x"#i#" register (AArch64 only)">; + +foreach i = {3,4,9-15,18,20-28} in def ffixed_x#i : Flag<["-"], "ffixed-x"#i>, Group<m_Group>, HelpText<"Reserve the x"#i#" register (AArch64/RISC-V only)">; diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp index 8e650ddf92dfc1..4f5d2fca67910c 100644 --- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp +++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp @@ -105,13 +105,8 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple, #define RESERVE_REG(REG) \ if (Args.hasArg(options::OPT_ffixed_##REG)) \ Features.push_back("+reserve-" #REG); - RESERVE_REG(x1) - RESERVE_REG(x2) RESERVE_REG(x3) RESERVE_REG(x4) - RESERVE_REG(x5) - RESERVE_REG(x6) - RESERVE_REG(x7) RESERVE_REG(x8) RESERVE_REG(x9) RESERVE_REG(x10) diff --git a/clang/test/Driver/riscv-fixed-x-register.c b/clang/test/Driver/riscv-fixed-x-register.c index 5759cd5ccf707c..06d5c0db07bddb 100644 --- a/clang/test/Driver/riscv-fixed-x-register.c +++ b/clang/test/Driver/riscv-fixed-x-register.c @@ -1,15 +1,3 @@ -// RUN: %clang --target=riscv32 -ffixed-x1 -### %s 2> %t -// RUN: FileCheck --check-prefix=CHECK-FIXED-X1 < %t %s -// RUN: %clang --target=riscv64 -ffixed-x1 -### %s 2> %t -// RUN: FileCheck --check-prefix=CHECK-FIXED-X1 < %t %s -// CHECK-FIXED-X1: "-target-feature" "+reserve-x1" - -// RUN: %clang --target=riscv32 -ffixed-x2 -### %s 2> %t -// RUN: FileCheck --check-prefix=CHECK-FIXED-X2 < %t %s -// RUN: %clang --target=riscv64 -ffixed-x2 -### %s 2> %t -// RUN: FileCheck --check-prefix=CHECK-FIXED-X2 < %t %s -// CHECK-FIXED-X2: "-target-feature" "+reserve-x2" - // RUN: %clang --target=riscv32 -ffixed-x3 -### %s 2> %t // RUN: FileCheck --check-prefix=CHECK-FIXED-X3 < %t %s // RUN: %clang --target=riscv64 -ffixed-x3 -### %s 2> %t @@ -22,24 +10,6 @@ // RUN: FileCheck --check-prefix=CHECK-FIXED-X4 < %t %s // CHECK-FIXED-X4: "-target-feature" "+reserve-x4" -// RUN: %clang --target=riscv32 -ffixed-x5 -### %s 2> %t -// RUN: FileCheck --check-prefix=CHECK-FIXED-X5 < %t %s -// RUN: %clang --target=riscv64 -ffixed-x5 -### %s 2> %t -// RUN: FileCheck --check-prefix=CHECK-FIXED-X5 < %t %s -// CHECK-FIXED-X5: "-target-feature" "+reserve-x5" - -// RUN: %clang --target=riscv32 -ffixed-x6 -### %s 2> %t -// RUN: FileCheck --check-prefix=CHECK-FIXED-X6 < %t %s -// RUN: %clang --target=riscv64 -ffixed-x6 -### %s 2> %t -// RUN: FileCheck --check-prefix=CHECK-FIXED-X6 < %t %s -// CHECK-FIXED-X6: "-target-feature" "+reserve-x6" - -// RUN: %clang --target=riscv32 -ffixed-x7 -### %s 2> %t -// RUN: FileCheck --check-prefix=CHECK-FIXED-X7 < %t %s -// RUN: %clang --target=riscv64 -ffixed-x7 -### %s 2> %t -// RUN: FileCheck --check-prefix=CHECK-FIXED-X7 < %t %s -// CHECK-FIXED-X7: "-target-feature" "+reserve-x7" - // RUN: %clang --target=riscv32 -ffixed-x8 -### %s 2> %t // RUN: FileCheck --check-prefix=CHECK-FIXED-X8 < %t %s // RUN: %clang --target=riscv64 -ffixed-x8 -### %s 2> %t @@ -186,35 +156,30 @@ // Test multiple of reserve-x# options together. // RUN: %clang --target=riscv32 \ -// RUN: -ffixed-x1 \ -// RUN: -ffixed-x2 \ +// RUN: -ffixed-x3 \ +// RUN: -ffixed-x4 \ // RUN: -ffixed-x18 \ // RUN: -### %s 2> %t // RUN: FileCheck \ -// RUN: --check-prefix=CHECK-FIXED-X1 \ -// RUN: --check-prefix=CHECK-FIXED-X2 \ +// RUN: --check-prefix=CHECK-FIXED-X3 \ +// RUN: --check-prefix=CHECK-FIXED-X4 \ // RUN: --check-prefix=CHECK-FIXED-X18 \ // RUN: < %t %s // RUN: %clang --target=riscv64 \ -// RUN: -ffixed-x1 \ -// RUN: -ffixed-x2 \ +// RUN: -ffixed-x3 \ +// RUN: -ffixed-x4 \ // RUN: -ffixed-x18 \ // RUN: -### %s 2> %t // RUN: FileCheck \ -// RUN: --check-prefix=CHECK-FIXED-X1 \ -// RUN: --check-prefix=CHECK-FIXED-X2 \ +// RUN: --check-prefix=CHECK-FIXED-X3 \ +// RUN: --check-prefix=CHECK-FIXED-X4 \ // RUN: --check-prefix=CHECK-FIXED-X18 \ // RUN: < %t %s // Test all reserve-x# options together. // RUN: %clang --target=riscv32 \ -// RUN: -ffixed-x1 \ -// RUN: -ffixed-x2 \ // RUN: -ffixed-x3 \ // RUN: -ffixed-x4 \ -// RUN: -ffixed-x5 \ -// RUN: -ffixed-x6 \ -// RUN: -ffixed-x7 \ // RUN: -ffixed-x8 \ // RUN: -ffixed-x9 \ // RUN: -ffixed-x10 \ @@ -241,13 +206,8 @@ // RUN: -ffixed-x31 \ // RUN: -### %s 2> %t // RUN: FileCheck \ -// RUN: --check-prefix=CHECK-FIXED-X1 \ -// RUN: --check-prefix=CHECK-FIXED-X2 \ // RUN: --check-prefix=CHECK-FIXED-X3 \ // RUN: --check-prefix=CHECK-FIXED-X4 \ -// RUN: --check-prefix=CHECK-FIXED-X5 \ -// RUN: --check-prefix=CHECK-FIXED-X6 \ -// RUN: --check-prefix=CHECK-FIXED-X7 \ // RUN: --check-prefix=CHECK-FIXED-X8 \ // RUN: --check-prefix=CHECK-FIXED-X9 \ // RUN: --check-prefix=CHECK-FIXED-X10 \ @@ -274,13 +234,8 @@ // RUN: --check-prefix=CHECK-FIXED-X31 \ // RUN: < %t %s // RUN: %clang --target=riscv64 \ -// RUN: -ffixed-x1 \ -// RUN: -ffixed-x2 \ // RUN: -ffixed-x3 \ // RUN: -ffixed-x4 \ -// RUN: -ffixed-x5 \ -// RUN: -ffixed-x6 \ -// RUN: -ffixed-x7 \ // RUN: -ffixed-x8 \ // RUN: -ffixed-x9 \ // RUN: -ffixed-x10 \ @@ -307,13 +262,8 @@ // RUN: -ffixed-x31 \ // RUN: -### %s 2> %t // RUN: FileCheck \ -// RUN: --check-prefix=CHECK-FIXED-X1 \ -// RUN: --check-prefix=CHECK-FIXED-X2 \ // RUN: --check-prefix=CHECK-FIXED-X3 \ // RUN: --check-prefix=CHECK-FIXED-X4 \ -// RUN: --check-prefix=CHECK-FIXED-X5 \ -// RUN: --check-prefix=CHECK-FIXED-X6 \ -// RUN: --check-prefix=CHECK-FIXED-X7 \ // RUN: --check-prefix=CHECK-FIXED-X8 \ // RUN: --check-prefix=CHECK-FIXED-X9 \ // RUN: --check-prefix=CHECK-FIXED-X10 \ diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index f91b2691cf3376..38096cb916d0a0 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -2008,7 +2008,8 @@ def FeatureExactAssembly : SubtargetFeature<"exact-asm", "EnableExactAssembly", "true", "Enable Exact Assembly (Disables Compression and Relaxation)">; -foreach i = {1-31} in +// Don't allow x0, x1, x2, x5, x6, and, x7 to be reserved. +foreach i = {3-4,8-31} in def FeatureReserveX#i : SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]", "true", "Reserve X"#i>; diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index b999fb062862ba..8fe1b10f460290 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -117,7 +117,6 @@ ; CHECK-NEXT: prefer-w-inst - Prefer instructions with W suffix. ; CHECK-NEXT: q - 'Q' (Quad-Precision Floating-Point). ; CHECK-NEXT: relax - Enable Linker relaxation. -; CHECK-NEXT: reserve-x1 - Reserve X1. ; CHECK-NEXT: reserve-x10 - Reserve X10. ; CHECK-NEXT: reserve-x11 - Reserve X11. ; CHECK-NEXT: reserve-x12 - Reserve X12. @@ -128,7 +127,6 @@ ; CHECK-NEXT: reserve-x17 - Reserve X17. ; CHECK-NEXT: reserve-x18 - Reserve X18. ; CHECK-NEXT: reserve-x19 - Reserve X19. -; CHECK-NEXT: reserve-x2 - Reserve X2. ; CHECK-NEXT: reserve-x20 - Reserve X20. ; CHECK-NEXT: reserve-x21 - Reserve X21. ; CHECK-NEXT: reserve-x22 - Reserve X22. @@ -143,9 +141,6 @@ ; CHECK-NEXT: reserve-x30 - Reserve X30. ; CHECK-NEXT: reserve-x31 - Reserve X31. ; CHECK-NEXT: reserve-x4 - Reserve X4. -; CHECK-NEXT: reserve-x5 - Reserve X5. -; CHECK-NEXT: reserve-x6 - Reserve X6. -; CHECK-NEXT: reserve-x7 - Reserve X7. ; CHECK-NEXT: reserve-x8 - Reserve X8. ; CHECK-NEXT: reserve-x9 - Reserve X9. ; CHECK-NEXT: rva20s64 - RISC-V rva20s64 profile. diff --git a/llvm/test/CodeGen/RISCV/machine-outliner-reserved-regs.mir b/llvm/test/CodeGen/RISCV/machine-outliner-reserved-regs.mir index 5d6a5363d19fd9..310dc77019e6ea 100644 --- a/llvm/test/CodeGen/RISCV/machine-outliner-reserved-regs.mir +++ b/llvm/test/CodeGen/RISCV/machine-outliner-reserved-regs.mir @@ -1,8 +1,11 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=riscv32 -mattr=+reserve-x6 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs \ -# RUN: -riscv-outliner-regsave=true < %s | FileCheck -check-prefixes=CHECK-X6-RESERVED %s -# RUN: llc -mtriple=riscv32 -mattr=+reserve-x6,+reserve-x7 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs \ -# RUN: -riscv-outliner-regsave=true < %s | FileCheck -check-prefixes=CHECK-X6-X7-RESERVED %s +# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs \ +# RUN: -riscv-outliner-regsave=true < %s | FileCheck -check-prefixes=CHECK-NONE-RESERVED %s +# RUN: llc -mtriple=riscv32 -mattr=+reserve-x28 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs \ +# RUN: -riscv-outliner-regsave=true < %s | FileCheck -check-prefixes=CHECK-X28-RESERVED %s + +# x6 and x7 are live throughout the sequence so they can't be used to save x5. +# Reserving x28 should make the outliner pick the next register, x29. --- | define i32 @outline_x5_live_reserved_0(i32 %a, i32 %b) { ret i32 0 } @@ -13,38 +16,41 @@ name: outline_x5_live_reserved_0 tracksRegLiveness: true body: | - ; CHECK-X6-RESERVED-LABEL: name: outline_x5_live_reserved_0 - ; CHECK-X6-RESERVED: bb.0: - ; CHECK-X6-RESERVED-NEXT: liveins: $x10, $x11, $x5 - ; CHECK-X6-RESERVED-NEXT: {{ $}} - ; CHECK-X6-RESERVED-NEXT: $x7 = ADDI $x5, 0 - ; CHECK-X6-RESERVED-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x7, implicit $x10, implicit $x11 - ; CHECK-X6-RESERVED-NEXT: $x5 = ADDI $x7, 0 - ; CHECK-X6-RESERVED-NEXT: PseudoBR %bb.1 - ; CHECK-X6-RESERVED-NEXT: {{ $}} - ; CHECK-X6-RESERVED-NEXT: bb.1: - ; CHECK-X6-RESERVED-NEXT: liveins: $x5, $x14 - ; CHECK-X6-RESERVED-NEXT: {{ $}} - ; CHECK-X6-RESERVED-NEXT: $x10 = ADD $x14, $x5 - ; CHECK-X6-RESERVED-NEXT: PseudoRET implicit $x10 + ; CHECK-NONE-RESERVED-LABEL: name: outline_x5_live_reserved_0 + ; CHECK-NONE-RESERVED: bb.0: + ; CHECK-NONE-RESERVED-NEXT: liveins: $x10, $x11, $x5, $x6, $x7 + ; CHECK-NONE-RESERVED-NEXT: {{ $}} + ; CHECK-NONE-RESERVED-NEXT: $x28 = ADDI $x5, 0 + ; CHECK-NONE-RESERVED-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x10, implicit $x11, implicit $x28 + ; CHECK-NONE-RESERVED-NEXT: $x5 = ADDI $x28, 0 + ; CHECK-NONE-RESERVED-NEXT: PseudoBR %bb.1 + ; CHECK-NONE-RESERVED-NEXT: {{ $}} + ; CHECK-NONE-RESERVED-NEXT: bb.1: + ; CHECK-NONE-RESERVED-NEXT: liveins: $x5, $x6, $x7, $x14 + ; CHECK-NONE-RESERVED-NEXT: {{ $}} + ; CHECK-NONE-RESERVED-NEXT: $x10 = ADD $x14, $x5 + ; CHECK-NONE-RESERVED-NEXT: $x10 = ADD $x10, $x6 + ; CHECK-NONE-RESERVED-NEXT: $x10 = ADD $x10, $x7 + ; CHECK-NONE-RESERVED-NEXT: PseudoRET implicit $x10 ; - ; CHECK-X6-X7-RESERVED-LABEL: name: outline_x5_live_reserved_0 - ; CHECK-X6-X7-RESERVED: bb.0: - ; CHECK-X6-X7-RESERVED-NEXT: liveins: $x10, $x11, $x5 - ; CHECK-X6-X7-RESERVED-NEXT: {{ $}} - ; CHECK-X6-X7-RESERVED-NEXT: $x28 = ADDI $x5, 0 - ; CHECK-X6-X7-RESERVED-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x10, implicit $x11, implicit $x28 - ; CHECK-X6-X7-RESERVED-NEXT: $x5 = ADDI $x28, 0 - ; CHECK-X6-X7-RESERVED-NEXT: PseudoBR %bb.1 - ; CHECK-X6-X7-RESERVED-NEXT: {{ $}} - ; CHECK-X6-X7-RESERVED-NEXT: bb.1: - ; CHECK-X6-X7-RESERVED-NEXT: liveins: $x5, $x14 - ; CHECK-X6-X7-RESERVED-NEXT: {{ $}} - ; CHECK-X6-X7-RESERVED-NEXT: $x10 = ADD $x14, $x5 - ; CHECK-X6-X7-RESERVED-NEXT: PseudoRET implicit $x10 - + ; CHECK-X28-RESERVED-LABEL: name: outline_x5_live_reserved_0 + ; CHECK-X28-RESERVED: bb.0: + ; CHECK-X28-RESERVED-NEXT: liveins: $x10, $x11, $x5, $x6, $x7 + ; CHECK-X28-RESERVED-NEXT: {{ $}} + ; CHECK-X28-RESERVED-NEXT: $x29 = ADDI $x5, 0 + ; CHECK-X28-RESERVED-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x10, implicit $x11, implicit $x29 + ; CHECK-X28-RESERVED-NEXT: $x5 = ADDI $x29, 0 + ; CHECK-X28-RESERVED-NEXT: PseudoBR %bb.1 + ; CHECK-X28-RESERVED-NEXT: {{ $}} + ; CHECK-X28-RESERVED-NEXT: bb.1: + ; CHECK-X28-RESERVED-NEXT: liveins: $x5, $x6, $x7, $x14 + ; CHECK-X28-RESERVED-NEXT: {{ $}} + ; CHECK-X28-RESERVED-NEXT: $x10 = ADD $x14, $x5 + ; CHECK-X28-RESERVED-NEXT: $x10 = ADD $x10, $x6 + ; CHECK-X28-RESERVED-NEXT: $x10 = ADD $x10, $x7 + ; CHECK-X28-RESERVED-NEXT: PseudoRET implicit $x10 bb.0: - liveins: $x10, $x11, $x5 + liveins: $x10, $x11, $x5, $x6, $x7 $x11 = ANDI $x11, 1023 $x12 = ADDI $x10, 17 $x11 = AND $x12, $x11 @@ -56,47 +62,51 @@ body: | PseudoBR %bb.1 bb.1: - liveins: $x5, $x14 + liveins: $x5, $x6, $x7, $x14 $x10 = ADD $x14, $x5 + $x10 = ADD $x10, $x6 + $x10 = ADD $x10, $x7 PseudoRET implicit $x10 ... --- name: outline_x5_live_reserved_1 tracksRegLiveness: true body: | - ; CHECK-X6-RESERVED-LABEL: name: outline_x5_live_reserved_1 - ; CHECK-X6-RESERVED: bb.0: - ; CHECK-X6-RESERVED-NEXT: liveins: $x10, $x11, $x5 - ; CHECK-X6-RESERVED-NEXT: {{ $}} - ; CHECK-X6-RESERVED-NEXT: $x7 = ADDI $x5, 0 - ; CHECK-X6-RESERVED-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x7, implicit $x10, implicit $x11 - ; CHECK-X6-RESERVED-NEXT: $x5 = ADDI $x7, 0 - ; CHECK-X6-RESERVED-NEXT: PseudoBR %bb.1 - ; CHECK-X6-RESERVED-NEXT: {{ $}} - ; CHECK-X6-RESERVED-NEXT: bb.1: - ; CHECK-X6-RESERVED-NEXT: liveins: $x5, $x14 - ; CHECK-X6-RESERVED-NEXT: {{ $}} - ; CHECK-X6-RESERVED-NEXT: $x10 = ADD $x14, $x5 - ; CHECK-X6-RESERVED-NEXT: PseudoRET implicit $x10 + ; CHECK-NONE-RESERVED-LABEL: name: outline_x5_live_reserved_1 + ; CHECK-NONE-RESERVED: bb.0: + ; CHECK-NONE-RESERVED-NEXT: liveins: $x10, $x11, $x5, $x6, $x7 + ; CHECK-NONE-RESERVED-NEXT: {{ $}} + ; CHECK-NONE-RESERVED-NEXT: $x28 = ADDI $x5, 0 + ; CHECK-NONE-RESERVED-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x10, implicit $x11, implicit $x28 + ; CHECK-NONE-RESERVED-NEXT: $x5 = ADDI $x28, 0 + ; CHECK-NONE-RESERVED-NEXT: PseudoBR %bb.1 + ; CHECK-NONE-RESERVED-NEXT: {{ $}} + ; CHECK-NONE-RESERVED-NEXT: bb.1: + ; CHECK-NONE-RESERVED-NEXT: liveins: $x5, $x6, $x7, $x14 + ; CHECK-NONE-RESERVED-NEXT: {{ $}} + ; CHECK-NONE-RESERVED-NEXT: $x10 = ADD $x14, $x5 + ; CHECK-NONE-RESERVED-NEXT: $x10 = ADD $x10, $x6 + ; CHECK-NONE-RESERVED-NEXT: $x10 = ADD $x10, $x7 + ; CHECK-NONE-RESERVED-NEXT: PseudoRET implicit $x10 ; - ; CHECK-X6-X7-RESERVED-LABEL: name: outline_x5_live_reserved_1 - ; CHECK-X6-X7-RESERVED: bb.0: - ; CHECK-X6-X7-RESERVED-NEXT: liveins: $x10, $x11, $x5 - ; CHECK-X6-X7-RESERVED-NEXT: {{ $}} - ; CHECK-X6-X7-RESERVED-NEXT: $x28 = ADDI $x5, 0 - ; CHECK-X6-X7-RESERVED-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x10, implicit $x11, implicit $x28 - ; CHECK-X6-X7-RESERVED-NEXT: $x5 = ADDI $x28, 0 - ; CHECK-X6-X7-RESERVED-NEXT: PseudoBR %bb.1 - ; CHECK-X6-X7-RESERVED-NEXT: {{ $}} - ; CHECK-X6-X7-RESERVED-NEXT: bb.1: - ; CHECK-X6-X7-RESERVED-NEXT: liveins: $x5, $x14 - ; CHECK-X6-X7-RESERVED-NEXT: {{ $}} - ; CHECK-X6-X7-RESERVED-NEXT: $x10 = ADD $x14, $x5 - ; CHECK-X6-X7-RESERVED-NEXT: PseudoRET implicit $x10 - - + ; CHECK-X28-RESERVED-LABEL: name: outline_x5_live_reserved_1 + ; CHECK-X28-RESERVED: bb.0: + ; CHECK-X28-RESERVED-NEXT: liveins: $x10, $x11, $x5, $x6, $x7 + ; CHECK-X28-RESERVED-NEXT: {{ $}} + ; CHECK-X28-RESERVED-NEXT: $x29 = ADDI $x5, 0 + ; CHECK-X28-RESERVED-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x10, implicit $x11, implicit $x29 + ; CHECK-X28-RESERVED-NEXT: $x5 = ADDI $x29, 0 + ; CHECK-X28-RESERVED-NEXT: PseudoBR %bb.1 + ; CHECK-X28-RESERVED-NEXT: {{ $}} + ; CHECK-X28-RESERVED-NEXT: bb.1: + ; CHECK-X28-RESERVED-NEXT: liveins: $x5, $x6, $x7, $x14 + ; CHECK-X28-RESERVED-NEXT: {{ $}} + ; CHECK-X28-RESERVED-NEXT: $x10 = ADD $x14, $x5 + ; CHECK-X28-RESERVED-NEXT: $x10 = ADD $x10, $x6 + ; CHECK-X28-RESERVED-NEXT: $x10 = ADD $x10, $x7 + ; CHECK-X28-RESERVED-NEXT: PseudoRET implicit $x10 bb.0: - liveins: $x10, $x11, $x5 + liveins: $x10, $x11, $x5, $x6, $x7 $x11 = ANDI $x11, 1023 $x12 = ADDI $x10, 17 $x11 = AND $x12, $x11 @@ -108,47 +118,51 @@ body: | PseudoBR %bb.1 bb.1: - liveins: $x5, $x14 + liveins: $x5, $x6, $x7, $x14 $x10 = ADD $x14, $x5 + $x10 = ADD $x10, $x6 + $x10 = ADD $x10, $x7 PseudoRET implicit $x10 ... --- name: outline_x5_live_reserved_2 tracksRegLiveness: true body: | - ; CHECK-X6-RESERVED-LABEL: name: outline_x5_live_reserved_2 - ; CHECK-X6-RESERVED: bb.0: - ; CHECK-X6-RESERVED-NEXT: liveins: $x10, $x11, $x5 - ; CHECK-X6-RESERVED-NEXT: {{ $}} - ; CHECK-X6-RESERVED-NEXT: $x7 = ADDI $x5, 0 - ; CHECK-X6-RESERVED-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x7, implicit $x10, implicit $x11 - ; CHECK-X6-RESERVED-NEXT: $x5 = ADDI $x7, 0 - ; CHECK-X6-RESERVED-NEXT: PseudoBR %bb.1 - ; CHECK-X6-RESERVED-NEXT: {{ $}} - ; CHECK-X6-RESERVED-NEXT: bb.1: - ; CHECK-X6-RESERVED-NEXT: liveins: $x5, $x14 - ; CHECK-X6-RESERVED-NEXT: {{ $}} - ; CHECK-X6-RESERVED-NEXT: $x10 = ADD $x14, $x5 - ; CHECK-X6-RESERVED-NEXT: PseudoRET implicit $x10 + ; CHECK-NONE-RESERVED-LABEL: name: outline_x5_live_reserved_2 + ; CHECK-NONE-RESERVED: bb.0: + ; CHECK-NONE-RESERVED-NEXT: liveins: $x10, $x11, $x5, $x6, $x7 + ; CHECK-NONE-RESERVED-NEXT: {{ $}} + ; CHECK-NONE-RESERVED-NEXT: $x28 = ADDI $x5, 0 + ; CHECK-NONE-RESERVED-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x10, implicit $x11, implicit $x28 + ; CHECK-NONE-RESERVED-NEXT: $x5 = ADDI $x28, 0 + ; CHECK-NONE-RESERVED-NEXT: PseudoBR %bb.1 + ; CHECK-NONE-RESERVED-NEXT: {{ $}} + ; CHECK-NONE-RESERVED-NEXT: bb.1: + ; CHECK-NONE-RESERVED-NEXT: liveins: $x5, $x6, $x7, $x14 + ; CHECK-NONE-RESERVED-NEXT: {{ $}} + ; CHECK-NONE-RESERVED-NEXT: $x10 = ADD $x14, $x5 + ; CHECK-NONE-RESERVED-NEXT: $x10 = ADD $x10, $x6 + ; CHECK-NONE-RESERVED-NEXT: $x10 = ADD $x10, $x7 + ; CHECK-NONE-RESERVED-NEXT: PseudoRET implicit $x10 ; - ; CHECK-X6-X7-RESERVED-LABEL: name: outline_x5_live_reserved_2 - ; CHECK-X6-X7-RESERVED: bb.0: - ; CHECK-X6-X7-RESERVED-NEXT: liveins: $x10, $x11, $x5 - ; CHECK-X6-X7-RESERVED-NEXT: {{ $}} - ; CHECK-X6-X7-RESERVED-NEXT: $x28 = ADDI $x5, 0 - ; CHECK-X6-X7-RESERVED-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x10, implicit $x11, implicit $x28 - ; CHECK-X6-X7-RESERVED-NEXT: $x5 = ADDI $x28, 0 - ; CHECK-X6-X7-RESERVED-NEXT: PseudoBR %bb.1 - ; CHECK-X6-X7-RESERVED-NEXT: {{ $}} - ; CHECK-X6-X7-RESERVED-NEXT: bb.1: - ; CHECK-X6-X7-RESERVED-NEXT: liveins: $x5, $x14 - ; CHECK-X6-X7-RESERVED-NEXT: {{ $}} - ; CHECK-X6-X7-RESERVED-NEXT: $x10 = ADD $x14, $x5 - ; CHECK-X6-X7-RESERVED-NEXT: PseudoRET implicit $x10 - - + ; CHECK-X28-RESERVED-LABEL: name: outline_x5_live_reserved_2 + ; CHECK-X28-RESERVED: bb.0: + ; CHECK-X28-RESERVED-NEXT: liveins: $x10, $x11, $x5, $x6, $x7 + ; CHECK-X28-RESERVED-NEXT: {{ $}} + ; CHECK-X28-RESERVED-NEXT: $x29 = ADDI $x5, 0 + ; CHECK-X28-RESERVED-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x10, implicit $x11, implicit $x29 + ; CHECK-X28-RESERVED-NEXT: $x5 = ADDI $x29, 0 + ; CHECK-X28-RESERVED-NEXT: PseudoBR %bb.1 + ; CHECK-X28-RESERVED-NEXT: {{ $}} + ; CHECK-X28-RESERVED-NEXT: bb.1: + ; CHECK-X28-RESERVED-NEXT: liveins: $x5, $x6, $x7, $x14 + ; CHECK-X28-RESERVED-NEXT: {{ $}} + ; CHECK-X28-RESERVED-NEXT: $x10 = ADD $x14, $x5 + ; CHECK-X28-RESERVED-NEXT: $x10 = ADD $x10, $x6 + ; CHECK-X28-RESERVED-NEXT: $x10 = ADD $x10, $x7 + ; CHECK-X28-RESERVED-NEXT: PseudoRET implicit $x10 bb.0: - liveins: $x10, $x11, $x5 + liveins: $x10, $x11, $x5, $x6, $x7 $x11 = ANDI $x11, 1023 $x12 = ADDI $x10, 17 $x11 = AND $x12, $x11 @@ -160,7 +174,9 @@ body: | PseudoBR %bb.1 bb.1: - liveins: $x5, $x14 + liveins: $x5, $x6, $x7, $x14 $x10 = ADD $x14, $x5 + $x10 = ADD $x10, $x6 + $x10 = ADD $x10, $x7 PseudoRET implicit $x10 ... diff --git a/llvm/test/CodeGen/RISCV/reserved-reg-errors.ll b/llvm/test/CodeGen/RISCV/reserved-reg-errors.ll index 2c406f443140a8..dd2019cee68c7d 100644 --- a/llvm/test/CodeGen/RISCV/reserved-reg-errors.ll +++ b/llvm/test/CodeGen/RISCV/reserved-reg-errors.ll @@ -1,7 +1,3 @@ -; RUN: not llc -mtriple=riscv32 -mattr=+reserve-x1 < %s 2>&1 | FileCheck %s -check-prefix=X1 -; RUN: not llc -mtriple=riscv64 -mattr=+reserve-x1 < %s 2>&1 | FileCheck %s -check-prefix=X1 -; RUN: not llc -mtriple=riscv32 -mattr=+reserve-x2 < %s 2>&1 | FileCheck %s -check-prefix=X2 -; RUN: not llc -mtriple=riscv64 -mattr=+reserve-x2 < %s 2>&1 | FileCheck %s -check-prefix=X2 ; RUN: not llc -mtriple=riscv32 -mattr=+reserve-x8 < %s 2>&1 | FileCheck %s -check-prefix=X8 ; RUN: not llc -mtriple=riscv64 -mattr=+reserve-x8 < %s 2>&1 | FileCheck %s -check-prefix=X8 ; RUN: not llc -mtriple=riscv32 -mattr=+reserve-x10 < %s 2>&1 | FileCheck %s -check-prefix=X10 @@ -16,8 +12,6 @@ ; errors are produced when no registers are reserved. define i32 @caller(i32 %a) #0 { -; X1: in function caller {{.*}} Return address register required, but has been reserved. -; X2: in function caller {{.*}} Stack pointer required, but has been reserved. ; X8: in function caller {{.*}} Frame pointer required, but has been reserved. ; X10: in function caller {{.*}} Argument register required, but has been reserved. ; X10: in function caller {{.*}} Return value register required, but has been reserved. diff --git a/llvm/test/CodeGen/RISCV/reserved-regs.ll b/llvm/test/CodeGen/RISCV/reserved-regs.ll index 045ffabf2ffc5c..7f2912636bf2cc 100644 --- a/llvm/test/CodeGen/RISCV/reserved-regs.ll +++ b/llvm/test/CodeGen/RISCV/reserved-regs.ll @@ -2,12 +2,6 @@ ; RUN: llc -mtriple=riscv64 -mattr=+reserve-x3 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X3 ; RUN: llc -mtriple=riscv32 -mattr=+reserve-x4 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X4 ; RUN: llc -mtriple=riscv64 -mattr=+reserve-x4 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X4 -; RUN: llc -mtriple=riscv32 -mattr=+reserve-x5 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X5 -; RUN: llc -mtriple=riscv64 -mattr=+reserve-x5 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X5 -; RUN: llc -mtriple=riscv32 -mattr=+reserve-x6 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X6 -; RUN: llc -mtriple=riscv64 -mattr=+reserve-x6 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X6 -; RUN: llc -mtriple=riscv32 -mattr=+reserve-x7 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X7 -; RUN: llc -mtriple=riscv64 -mattr=+reserve-x7 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X7 ; RUN: llc -mtriple=riscv32 -mattr=+reserve-x8 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X8 ; RUN: llc -mtriple=riscv64 -mattr=+reserve-x8 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X8 ; RUN: llc -mtriple=riscv32 -mattr=+reserve-x9 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X9 @@ -71,12 +65,6 @@ define void @foo() { ; X3-NOT: ld gp, ; X4-NOT: lw tp, ; X4-NOT: ld tp, -; X5-NOT: lw t0, -; X5-NOT: ld t0, -; X6-NOT: lw t1, -; X6-NOT: ld t1, -; X7-NOT: lw t2, -; X7-NOT: ld t2, ; X8-NOT: lw s0, ; X8-NOT: ld s0, ; X9-NOT: lw s1, _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
