Justin Shore wrote:
We're staging a DS3 mux to aggregate T1s back to a PA-MC-2T3-EC in a 7206VXR (G2) running 12.4(15)T7. I haven't channelized a T3 before so I'm feeling my way through this. It looks to be relatively simple but I'm getting tripped up somewhere. On the 7206:
We just solved the problem. After soldering the tech's TBird back together he hooked it up and quickly figured out that the T & R pairs were flipped. He took care of that and the T1s popped up right away. I believe it was Jonathan Herbert who first suggested that as a possible culprit so many thanks to him. That would explain why the circuit would come up with physically looped because it wouldn't matter if T & R were flipped at that point. But of course when the routers themselves would never make the connection on their own.
So at this point I'm generating clocking on the DS3 from the 7206; the 7206's DS1 are set to get clocking internally; the mux is set to get clocking off the DS3 from the 7206; and finally the CPEs are always set to line for clocking. I'm currently running with M23 on the DS3. It was suggested that I switch to cbit for better diagnostics in the event of DS3 failure. I'll test that this afternoon.
Many thanks for all the help. In the end we were tripped up by a simple L1 problem. Thanks again
Justin _______________________________________________ cisco-nsp mailing list [email protected] https://puck.nether.net/mailman/listinfo/cisco-nsp archive at http://puck.nether.net/pipermail/cisco-nsp/
