On Fri, Apr 08, 2005 at 10:31:26AM -0700, Nishanth Aravamudan wrote:
> On Fri, Apr 08, 2005 at 09:44:12AM -0700, Nishanth Aravamudan wrote:
> > On Thu, Apr 07, 2005 at 04:43:08PM -0700, Dave Hansen wrote:
> > > On Thu, 2005-04-07 at 15:47 -0700, Nishanth Aravamudan wrote:
> > > > ppc64: 8-way pSeries (1.5 GHz Power4) with 64 GB RAM
> > > > x86: 4-way NUMA-Q (360 MHz PII) with 3GB RAM
> > > >
> > > > Please ask questions/request more details, if you need them.
> > > 
> > > It would be interesting to see these on slightly more modern hardware.
> > > That ppc64 machine has *HUGE* L2/L3 caches, and the "NUMA-Q" really
> > > behaves like a regular-old 4-way PIII Xeon.  Plus, its 2MB L2 caches
> > > will hide lots of cacheline bouncing problems, and some of that is
> > > certainly going to be an issue when you bloat a data structure like
> > > 'struct page'.
> > > 
> > > I'd suggest trying these on a couple of different pieces of hardware.
> > > First, a real NUMA NUMA-Q.  A 16-processor 4-node system should do.
> > > Secondly, a non-Xeon x86 system.  These have smaller caches, and will
> > > have the cache problems show more effectively.  Finally, as large and
> > > NUMA-ish of a ppc64 system as you can get.
> > 
> > I will see what I can do as far as gaining access to benchmark systems.
> > I can't make any promises, but I will try.
> 
> I am re-running the x86 tests on a 16-way traditional NUMA-Q. The most

FWIW, this will only give results on stock 2.6.12-rc1 and w/ and w/o
Gerrit's patches. As you yourself pointed  out, the Memory RC will bomb
on NUMA-Q.

Thanks,
Nish


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