On Tue, 2010-11-02 at 15:24 +0000, [email protected] wrote: > I usually work with smaller devices (e.g. Cortex M3), so I am not to > familiar with STB CPUs up until now and i am trying to get an > overview.
Intel CE3100/4100 are Atoms SoCs. > So with x100 the video display is not rendered on an texture, right? Right. > Would picture in picture (second hardware decode and resizing) be > available then? Yes, you can decode a second video, resize it and display it somewhere on a plane in front of the "main" decoding plane. > And I got some issues with v/a async and interlacing, would that be > solved with such a solution (i.e. by the hw decoder)? I haven't tested interlaced videos. I'm assuming the hardware does the right thing™. -- Damien _______________________________________________ clutter-app-devel-list mailing list [email protected] http://lists.clutter-project.org/listinfo/clutter-app-devel-list
