Hi Bahadir,
I am also very interested in porting Codezero to OR1200 (OpenRisc 1k
implementation).
For the very begining config has to be generated for or32-elf-gcc to be
taken as a compiler, and necessary startup (bare metal) has to be re-written
in OR1k assembly.
OR1ksim will be used for simulation instead of qemu.
I will be happy to see only this compiles and giving first signs of life,
befor even thinking about OS concepts of memory mapping etc (I am still
learning L4 specifics).
BR,
Drasko
On Mon, Apr 19, 2010 at 10:55 AM, Bahadir Balban <baha...@l4dev.org> wrote:
> Ravi Kumar Pujari wrote:
> > Hello,
> >
> > I am a student of Technical University Munich, currently researching on
> SMP and
> > RISC architectures.
> > As part of my work I was interested in getting a Microkernel running on
> the
> > OpenRISC processor (from www.opencores.org).
> > I am aiming to get a SMP system running and to validate a Microkernel
> > performance on it.
>
> Hi Ravi,
>
> It sounds interesting and it would be great to see Codezero running on
> an open core.
>
> > Hence would like to port the Codezero stand of L4 kernel as the site
> suggests it
> > is a lean implementation for embedded systems and should be easily
> portable.
> >
> > As a staring point I did try to compile the v0.3 obtained from the git
> > repository (www.git.l4dev.org/codezero.git) using the gcc ported for
> OpenRISC
> > processor, just to see where all the compilation would fail and in this
> way to
> > get the list of all the functions that are ARM specific and need to be
> ported.
> > While I saw that the build is automated heavily based on the build.py and
> as
> > such it uses some hard coding in terms of architecture specific compiler
> > switches like "-march=armvX", which isnt supported for the OpenRISC port
> of gcc
> > and "arch and subarch" for path rules and hence my compilation fails on
> every
> > file :(
>
> This is due to the configuration file. We use an ARM configuration file
> which we created, and the build logic generates these flags based on the
> architecture it has parsed in the cml file. cml files are under
> config/cml/ and have a syntax of their own. Please google for cml2 for
> this.
>
> Here you go, from config/configuration.py
>
> 121 # Extract cpu from a name value pair
> 122 def get_cpu(self, name, val):
> 123 if name[:len("CONFIG_CPU_")] == "CONFIG_CPU_":
> 124 parts = name.split("_", 3)
> 125 self.cpu = parts[2].lower()
> 126
> 127 # derive gcc "-march" flag
> 128 for cputype, archflag in self.arch_to_gcc_flag:
> 129 if cputype == parts[2]:
> 130 self.gcc_arch_flag = archflag
>
> You need to create a basic configuration file for your core, and there
> are bits like this that you will need to change.
>
> > Could you please send me the SMP version of Codezero v0.3 kernel and also
> some
> > wiki/documents/hints on the code structure breakup and the necessary
> > architecture specific parts in the code that I would have to port from
> ARM to
> > OpenRISC.
>
> This is already on the site git.l4dev.org. And wiki documentation is
> under l4dev.org as well.
>
> However, we don't have specific directory documentation.
>
> Particularly you need to be confident with your core's virtual memory
> details.
>
> 1) Do you know how to create and manipulate page tables?
> 2) You need detailed assembler knowledge for implementing context
> switching, entry and exit from exceptions.
> 3) You need to write some basic timer and irq controller driver
> 4) Uart driver would be helpful.
>
> If you are capable of doing (1) and (2) the rest should be easy.
>
> > I would be thankful for this support from you.
> >
> > Thanks and Best Regards,
> >
> > Ravi Kumar
> > Graduate Student
> > Institute for Integrated Systems
> > Department of Electrical Engineering and Information Technology
> > Technische Universität München
> > 80331 Munich, Germany
>
> Good luck!
>
> --
> Bahadir
> _______________________________________________
> codezero-devel mailing list
> codezero-devel@lists.l4dev.org
> http://lists.l4dev.org/mailman/listinfo/codezero-devel
>
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