Tuesday August 11th
11am-11:50am Kelley 1007 Herman Casier AMI Semiconductor Fellow (ret.) "Technology and other limitations for analog design" Abstract: Many analog design problems are all to easily referred to as "matching" problems since they seem to be the result of processing imperfections. This is to broad a generalization. In the seminar, this "matching" problem will be unraveled into specific processing, environment and physical imperfections. Different types of imperfections have different characteristics which have to be treated differently during design. A classification for typical analog technologies is presented with examples of imperfections. The seminar will focus on non-standard textbook examples such as worst case design, avalanche breakdown, high temperature effects, package stress and dielectric relaxation. Biography: Herman Casier received his MS in electronics from the Katholieke Universiteit Leuven in 1970. As assistant at the university, he worked on bipolar technology, device modeling and mixed signal design in bipolar and MOS technologies. From 1977 to 1980, he joined BARCO N.V. as senior designer and later became responsible for new technologies. In 1980, he was one of the founders of the design house INCIR in Belgium. >From 1983 to 2002, he was with Alcatel Microelectronics, where he first held several design and R&D management positions and later became engineering officer. Until 1997 he was involved in high voltage and sensor interfaces in CMOS and BiCMOS and in the definition of high voltage technologies for automotive and industrial applications. From 1997 to 2002 he researched high speed wireline interfaces, high accuracy telecom circuits and the analog front-end of ADSL. Since 2002 and untill his retirement in 2007, he was an engineering fellow at AMI Semiconductor (now ON Semiconductor) in Oudenaarde, Belgium. His current research interests are technology limitations, high voltage, smart power circuits, high accuracy sensor interfaces, ESD, EMC and other interference protections in CMOS and DMOS technologies.
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