Author: matt
Date: 2008-02-24 17:46:34 -0700 (Sun, 24 Feb 2008)
New Revision: 7828
Modified:
usrp2/trunk/fpga/eth/rtl/verilog/MAC_top.v
Log:
debugging pins
Modified: usrp2/trunk/fpga/eth/rtl/verilog/MAC_top.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/MAC_top.v 2008-02-25 00:45:59 UTC (rev
7827)
+++ usrp2/trunk/fpga/eth/rtl/verilog/MAC_top.v 2008-02-25 00:46:34 UTC (rev
7828)
@@ -495,9 +495,9 @@
.UpdateMIIRX_DATAReg ( UpdateMIIRX_DATAReg )
);
- //assign debug0 = {{debug_rx[3:0], xon_gen, xon_gen_complete, xoff_gen,
xoff_gen_complete},
-//
{1'b0,Rx_mac_err,Rx_mac_empty,Rx_mac_rd,Rx_mac_sop,Rx_mac_eop,Rx_mac_BE[1:0]},
- // {rx_fifo_space}};
- assign debug0 = debug_tx0;
- assign debug1 = debug_tx1;
+ assign debug0 = {{debug_rx[3:0], xon_gen, xon_gen_complete, xoff_gen,
xoff_gen_complete},
+
{1'b0,Rx_mac_err,Rx_mac_empty,Rx_mac_rd,Rx_mac_sop,Rx_mac_eop,Rx_mac_BE[1:0]},
+ {rx_fifo_space}};
+ //assign debug0 = debug_tx0;
+ //assign debug1 = debug_tx1;
endmodule
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