Script 'mail_helper' called by obssrc
Hello community,
here is the log from the commit of package mcelog for openSUSE:Factory checked
in at 2023-06-17 22:19:59
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Comparing /work/SRC/openSUSE:Factory/mcelog (Old)
and /work/SRC/openSUSE:Factory/.mcelog.new.15902 (New)
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "mcelog"
Sat Jun 17 22:19:59 2023 rev:62 rq:1093247 version:194
Changes:
--------
--- /work/SRC/openSUSE:Factory/mcelog/mcelog.changes 2022-05-05
23:04:31.541417417 +0200
+++ /work/SRC/openSUSE:Factory/.mcelog.new.15902/mcelog.changes 2023-06-17
22:20:08.475475938 +0200
@@ -1,0 +2,65 @@
+Wed Jun 14 14:58:43 UTC 2023 - tr...@suse.de
+
+- Update to version 194 (jsc#PED-4218):
+ * client.c: fix build w/ musl libc
+ * mcelog: New model number for Arrowlake
+ * mcelog: Don't overwrite model number when lookup fails
+ * mcelog: Add Graniterapids, Grandridge and Sierraforest
+ * mcelog: New model number for Lunarlake
+ * mcelog: Add Emerald Rapids
+ * mcelog: Add decode support for Sapphire Rapids
+ * Update PFA_test_howto
+ * mcelog: Add support for Meteor Lake
+
+-------------------------------------------------------------------
+Thu Oct 06 14:56:44 UTC 2022 - tr...@suse.de
+
+- Includes following SLE 15 SP5 jira features:
+ * jsc#PED-671 mcelog: Update to latest release
+ * jsc#PED-686 [CPU Features] Update mcelog support for ADL-N
+ * jsc#PED-638 [CPU Features] Update mcelog support for MTL-P
+- Update to version 189:
+ * mcelog: Add another Raptor Lake CPU model
+ * Fix generation of cputype files
+ * mcelog: Add missing model numbers for Broadwell and Raptorlake
+ * mcelog: Makefile: Only touch cputype.h if needed to create it
+ * Makefile: add install-nodoc target
+ * Use env as the shebang target
+ * Add missing dependencies for cputype include files
+ * mcelog: Reverse sens of check to call resolveaddr()
+ * mcelog: Reverse the sense of the check to set memory_error_support
+ * mcelog: Drop CASE_INTEL define
+ * mcelog: Generate cpu_choices[] from table
+ * mcelog: Generate the cputype_name[] array from the table
+ * mcelog: Add CPU model numbers to table and generate switch function
+ * mcelog: Generate CPU_* enums from a table
+ * mcelog: Add two more Alderlake model numbers
+ * mcelog: Reduce default threshold for corrected error page offline
+ * Make genconfig use python3
+ * mcelog: Add support for Raptorlake
+ * Fix warnings in sysfs.c
+ * mcelog: Change "DDR4" string to "DDR" for i10nm platforms
+ * Fix logrotate syntax
+ * remove outdated mcelog.conf.5 manual file
+ * add furture print function for Python2
+ * fix python errors in genconfig.py
+ * fix the buf not freed in read_field
+ * mcelog: Print warning for locked down kernel
+ * mcelog: Handle sysfs files without length
+- Had to adopt to latest CPU identification model
+ mainline patch:
+ b54ee05056a76e mcelog: Drop CASE_INTEL define
+ and friends
+A add_new_amd_cpu_defines
+D add-defines.patch
+M Start-consolidating-AMD-specific-stuff.patch
+M add-f10h-support.patch
+M add-f11h-support.patch
+M add-f12h-support.patch
+M add-f14h-support.patch
+M add-f15h-support.patch
+M add-f16h-support.patch
+M email.patch
+M fix_setgroups_missing_call.patch
+
+-------------------------------------------------------------------
Old:
----
add-defines.patch
mcelog-181.obscpio
python3_shebang
New:
----
add_new_amd_cpu_defines
mcelog-194.obscpio
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Other differences:
------------------
++++++ mcelog.spec ++++++
--- /var/tmp/diff_new_pack.0GxPrU/_old 2023-06-17 22:20:09.435481707 +0200
+++ /var/tmp/diff_new_pack.0GxPrU/_new 2023-06-17 22:20:09.439481732 +0200
@@ -1,7 +1,7 @@
#
# spec file for package mcelog
#
-# Copyright (c) 2022 SUSE LLC
+# Copyright (c) 2023 SUSE LLC
#
# All modifications and additions to the file contributed by third parties
# remain the property of their copyright owners, unless otherwise agreed
@@ -21,7 +21,7 @@
%define _fillupdir %{_localstatedir}/adm/fillup-templates
%endif
Name: mcelog
-Version: 181
+Version: 194
Release: 0
Summary: Log Machine Check Events
License: GPL-2.0-only
@@ -35,7 +35,7 @@
Patch1: email.patch
Patch2: mcelog_invert_prefill_db_warning.patch
Patch3: Start-consolidating-AMD-specific-stuff.patch
-Patch4: patches/add-defines.patch
+Patch4: add_new_amd_cpu_defines
Patch5: patches/add-f10h-support.patch
Patch6: patches/add-f11h-support.patch
Patch7: patches/add-f12h-support.patch
@@ -44,8 +44,6 @@
Patch10: patches/add-f16h-support.patch
Patch11: mcelog-socket-path.patch
Patch12: fix_setgroups_missing_call.patch
-Patch13: python3_shebang
-BuildRequires: %{pythons}
BuildRequires: libesmtp-devel
BuildRequires: pkgconfig
BuildRequires: pkgconfig(systemd)
++++++ Start-consolidating-AMD-specific-stuff.patch ++++++
--- /var/tmp/diff_new_pack.0GxPrU/_old 2023-06-17 22:20:09.483481996 +0200
+++ /var/tmp/diff_new_pack.0GxPrU/_new 2023-06-17 22:20:09.483481996 +0200
@@ -18,23 +18,23 @@
rename k8.c => amd.c (97%)
rename k8.h => amd.h (79%)
-Index: mcelog-181/Makefile
+Index: mcelog-189/Makefile
===================================================================
---- mcelog-181.orig/Makefile
-+++ mcelog-181/Makefile
+--- mcelog-189.orig/Makefile
++++ mcelog-189/Makefile
@@ -31,7 +31,7 @@ all: mcelog
- .PHONY: install clean depend FORCE
+ .PHONY: install install-nodoc clean depend FORCE
-OBJ := p4.o k8.o mcelog.o dmi.o tsc.o core2.o bitfield.o intel.o \
+OBJ := p4.o amd.o mcelog.o dmi.o tsc.o core2.o bitfield.o intel.o \
nehalem.o dunnington.o tulsa.o config.o memutil.o msg.o \
eventloop.o leaky-bucket.o memdb.o server.o trigger.o \
client.o cache.o sysfs.o yellow.o page.o rbtree.o \
-Index: mcelog-181/amd.c
+Index: mcelog-189/amd.c
===================================================================
--- /dev/null
-+++ mcelog-181/amd.c
++++ mcelog-189/amd.c
@@ -0,0 +1,282 @@
+/* Based on K8 decoding code written for the 2.4 kernel by Andi Kleen and
+ * Eric Morton. Hacked and extended for mcelog by AK.
@@ -318,11 +318,11 @@
+ }
+ return 1;
+}
-Index: mcelog-181/amd.h
+Index: mcelog-189/amd.h
===================================================================
--- /dev/null
-+++ mcelog-181/amd.h
-@@ -0,0 +1,14 @@
++++ mcelog-189/amd.h
+@@ -0,0 +1,80 @@
+char *k8_bank_name(unsigned num);
+void decode_amd_mc(enum cputype, struct mce *mce, int *ismemerr);
+int mce_filter_k8(struct mce *m);
@@ -335,11 +335,77 @@
+#define K8_MCELOG_THRESHOLD_L3_CACHE (4 * 9 + 2)
+#define K8_MCELOG_THRESHOLD_FBDIMM (4 * 9 + 3)
+
++#define EC(x) ((x) & 0xffff)
++#define XEC(x, mask) (((x) >> 16) & mask)
++
++#define LOW_SYNDROME(x) (((x) >> 15) & 0xff)
++#define HIGH_SYNDROME(x) (((x) >> 24) & 0xff)
++
++#define TLB_ERROR(x) (((x) & 0xFFF0) == 0x0010)
++#define MEM_ERROR(x) (((x) & 0xFF00) == 0x0100)
++#define BUS_ERROR(x) (((x) & 0xF800) == 0x0800)
++#define INT_ERROR(x) (((x) & 0xF4FF) == 0x0400)
++
++#define TT(x) (((x) >> 2) & 0x3)
++#define TT_MSG(x) tt_msgs[TT(x)]
++#define II(x) (((x) >> 2) & 0x3)
++#define II_MSG(x) ii_msgs[II(x)]
++#define LL(x) ((x) & 0x3)
++#define LL_MSG(x) ll_msgs[LL(x)]
++#define TO(x) (((x) >> 8) & 0x1)
++#define TO_MSG(x) to_msgs[TO(x)]
++#define PP(x) (((x) >> 9) & 0x3)
++#define PP_MSG(x) pp_msgs[PP(x)]
++#define UU(x) (((x) >> 8) & 0x3)
++#define UU_MSG(x) uu_msgs[UU(x)]
++
++#define R4(x) (((x) >> 4) & 0xf)
++#define R4_MSG(x) ((R4(x) < 9) ? rrrr_msgs[R4(x)] :
"Wrong R4!")
++
++enum tt_ids {
++ TT_INSTR = 0,
++ TT_DATA,
++ TT_GEN,
++ TT_RESV,
++};
++
++enum ll_ids {
++ LL_RESV = 0,
++ LL_L1,
++ LL_L2,
++ LL_LG,
++};
++
++enum ii_ids {
++ II_MEM = 0,
++ II_RESV,
++ II_IO,
++ II_GEN,
++};
++
++enum rrrr_ids {
++ R4_GEN = 0,
++ R4_RD,
++ R4_WR,
++ R4_DRD,
++ R4_DWR,
++ R4_IRD,
++ R4_PREF,
++ R4_EVICT,
++ R4_SNOOP,
++};
++
+#define CASE_AMD_CPUS \
-+ case CPU_K8
-Index: mcelog-181/k8.c
++ (cputype == CPU_K8 || \
++ cputype == CPU_F10H || \
++ cputype == CPU_F11H || \
++ cputype == CPU_F12H || \
++ cputype == CPU_F14H || \
++ cputype == CPU_F15H || \
++ cputype == CPU_F16H)
+Index: mcelog-189/k8.c
===================================================================
---- mcelog-181.orig/k8.c
+--- mcelog-189.orig/k8.c
+++ /dev/null
@@ -1,281 +0,0 @@
-/* Based on K8 decoding code written for the 2.4 kernel by Andi Kleen and
@@ -623,9 +689,9 @@
- }
- return 1;
-}
-Index: mcelog-181/k8.h
+Index: mcelog-189/k8.h
===================================================================
---- mcelog-181.orig/k8.h
+--- mcelog-189.orig/k8.h
+++ /dev/null
@@ -1,11 +0,0 @@
-char *k8_bank_name(unsigned num);
@@ -639,10 +705,10 @@
-#define K8_MCELOG_THRESHOLD_LINK (4 * 9 + 1)
-#define K8_MCELOG_THRESHOLD_L3_CACHE (4 * 9 + 2)
-#define K8_MCELOG_THRESHOLD_FBDIMM (4 * 9 + 3)
-Index: mcelog-181/mcelog.c
+Index: mcelog-189/mcelog.c
===================================================================
---- mcelog-181.orig/mcelog.c
-+++ mcelog-181/mcelog.c
+--- mcelog-189.orig/mcelog.c
++++ mcelog-189/mcelog.c
@@ -41,7 +41,7 @@
#include <fnmatch.h>
#include "mcelog.h"
@@ -652,17 +718,15 @@
#include "intel.h"
#include "p4.h"
#include "dmi.h"
-@@ -453,9 +453,9 @@ static void dump_mce(struct mce *m, unsi
+@@ -346,8 +346,8 @@ static void dump_mce(struct mce *m, unsi
time_t t = m->time;
Wprintf("TIME %llu %s", m->time, ctime(&t));
}
-- switch (cputype) {
-- case CPU_K8:
+- if (cputype == CPU_K8)
- decode_k8_mc(m, &ismemerr);
-+ switch (cputype) {
-+ CASE_AMD_CPUS:
-+ decode_amd_mc(cputype, m, &ismemerr);
- break;
- CASE_INTEL_CPUS:
++ if CASE_AMD_CPUS
++ decode_amd_mc(m, &ismemerr);
+ else if (cputype >= CPU_INTEL)
decode_intel_mc(m, cputype, &ismemerr, recordlen);
+ /* else add handlers for other CPUs here */
++++++ _service ++++++
--- /var/tmp/diff_new_pack.0GxPrU/_old 2023-06-17 22:20:09.503482116 +0200
+++ /var/tmp/diff_new_pack.0GxPrU/_new 2023-06-17 22:20:09.507482141 +0200
@@ -1,7 +1,7 @@
<services>
<service name="obs_scm" mode="localonly">
<param name="scm">git</param>
- <param name="url">https://github.com/andikleen/mcelog.git</param>
+ <param
name="url">git://git.kernel.org/pub/scm/utils/cpu/mce/mcelog.git</param>
<param name="changesgenerate">enable</param>
<param name="versionrewrite-pattern">v(.*)</param>
<param name="versionformat">@PARENT_TAG@</param>
++++++ _servicedata ++++++
--- /var/tmp/diff_new_pack.0GxPrU/_old 2023-06-17 22:20:09.527482261 +0200
+++ /var/tmp/diff_new_pack.0GxPrU/_new 2023-06-17 22:20:09.531482284 +0200
@@ -3,8 +3,6 @@
<param name="url">https://github.com/andikleen/mcelog</param>
<param
name="changesrevision">ee90ff20ce6a4d5e016aa249ce8b37f359f9fda4</param></service><service
name="tar_scm">
<param
name="url">git://git.kernel.org/pub/scm/utils/cpu/mce/mcelog.git</param>
- <param
name="changesrevision">a4edca25ef3bd8780ae1dc54bc203973ec7f1640</param></service><service
name="tar_scm">
- <param
name="url">https://github.com/andikleen/mcelog.git</param>
- <param
name="changesrevision">a4edca25ef3bd8780ae1dc54bc203973ec7f1640</param></service></servicedata>
+ <param
name="changesrevision">04d51981e8805c4200f5a03b4216c8621bc52ace</param></service></servicedata>
(No newline at EOF)
++++++ add-f10h-support.patch ++++++
--- /var/tmp/diff_new_pack.0GxPrU/_old 2023-06-17 22:20:09.543482356 +0200
+++ /var/tmp/diff_new_pack.0GxPrU/_new 2023-06-17 22:20:09.547482381 +0200
@@ -8,10 +8,10 @@
mcelog.h | 1
4 files changed, 506 insertions(+), 51 deletions(-)
-Index: mcelog-181/amd.c
+Index: mcelog-189/amd.c
===================================================================
---- mcelog-181.orig/amd.c
-+++ mcelog-181/amd.c
+--- mcelog-189.orig/amd.c
++++ mcelog-189/amd.c
@@ -14,7 +14,7 @@
#include "mcelog.h"
#include "amd.h"
@@ -561,10 +561,10 @@
+ }
+ return 1;
}
-Index: mcelog-181/amd.h
+Index: mcelog-189/amd.h
===================================================================
---- mcelog-181.orig/amd.h
-+++ mcelog-181/amd.h
+--- mcelog-189.orig/amd.h
++++ mcelog-189/amd.h
@@ -1,6 +1,25 @@
+#include <stdbool.h>
+
@@ -601,7 +601,7 @@
#define EC(x) ((x) & 0xffff)
#define XEC(x, mask) (((x) >> 16) & mask)
-@@ -22,23 +43,20 @@ int mce_filter_k8(struct mce *m);
+@@ -22,20 +43,20 @@ int mce_filter_k8(struct mce *m);
#define INT_ERROR(x) (((x) & 0xF4FF) == 0x0400)
#define TT(x) (((x) >> 2) & 0x3)
@@ -624,67 +624,26 @@
#define R4(x) (((x) >> 4) & 0xf)
-#define R4_MSG(x) ((R4(x) < 9) ? rrrr_msgs[R4(x)] :
"Wrong R4!")
--
--#define CASE_AMD_CPUS \
-- case CPU_K8
+#define R4_MSG(x) ((R4(x) < 9) ? memtrans[R4(x)] :
"Wrong R4!")
enum tt_ids {
TT_INSTR = 0,
-@@ -72,3 +90,7 @@ enum rrrr_ids {
- R4_EVICT,
- R4_SNOOP,
- };
-+
-+#define CASE_AMD_CPUS \
-+ case CPU_K8: \
-+ case CPU_F10H
-Index: mcelog-181/mcelog.c
+Index: mcelog-189/mcelog.c
===================================================================
---- mcelog-181.orig/mcelog.c
-+++ mcelog-181/mcelog.c
-@@ -148,19 +148,20 @@ static void resolveaddr(unsigned long lo
-
- static int mce_filter(struct mce *m, unsigned recordlen)
- {
-- if (!filter_bogus)
-+ if (!filter_bogus)
- return 1;
-+
+--- mcelog-189.orig/mcelog.c
++++ mcelog-189/mcelog.c
+@@ -152,8 +152,8 @@ static int mce_filter(struct mce *m, uns
/* Filter out known broken MCEs */
- switch (cputype) {
-- case CPU_K8:
+ if (cputype >= CPU_INTEL)
+ return mce_filter_intel(m, recordlen);
+- else if (cputype == CPU_K8)
- return mce_filter_k8(m);
-+ CASE_AMD_CPUS:
++ else if CASE_AMD_CPUS
+ return mce_filter_amd(m);
- /* add more buggy CPUs here */
- CASE_INTEL_CPUS:
- return mce_filter_intel(m, recordlen);
- default:
- case CPU_GENERIC:
- return 1;
-- }
-+ }
- }
- static void print_tsc(int cpunum, __u64 tsc, unsigned long time)
-@@ -228,6 +229,7 @@ static char *cputype_name[] = {
- [CPU_P6OLD] = "Intel PPro/P2/P3/old Xeon",
- [CPU_CORE2] = "Intel Core", /* 65nm and 45nm */
- [CPU_K8] = "AMD K8 and derivates",
-+ [CPU_F10H] = "AMD Greyhound",
- [CPU_P4] = "Intel P4",
- [CPU_NEHALEM] = "Intel Xeon 5500 series / Core i3/5/7
(\"Nehalem/Westmere\")",
- [CPU_DUNNINGTON] = "Intel Xeon 7400 series",
-@@ -268,6 +270,7 @@ static struct config_choice cpu_choices[
- { "p6old", CPU_P6OLD },
- { "core2", CPU_CORE2 },
- { "k8", CPU_K8 },
-+ { "f10h", CPU_F10H },
- { "p4", CPU_P4 },
- { "dunnington", CPU_DUNNINGTON },
- { "xeon74xx", CPU_DUNNINGTON },
-@@ -390,9 +393,7 @@ static enum cputype setup_cpuid(u32 cpuv
+ return 1;
+ }
+@@ -283,9 +283,7 @@ static enum cputype setup_cpuid(u32 cpuv
case X86_VENDOR_INTEL:
return select_intel_cputype(family, model);
case X86_VENDOR_AMD:
@@ -695,7 +654,16 @@
default:
Eprintf("Unknown CPU type vendor %u family %u model %u",
cpuvendor, family, model);
-@@ -581,14 +582,9 @@ int is_cpu_supported(void)
+@@ -347,7 +345,7 @@ static void dump_mce(struct mce *m, unsi
+ Wprintf("TIME %llu %s", m->time, ctime(&t));
+ }
+ if CASE_AMD_CPUS
+- decode_amd_mc(m, &ismemerr);
++ decode_amd_mc(cputype, m, &ismemerr);
+ else if (cputype >= CPU_INTEL)
+ decode_intel_mc(m, cputype, &ismemerr, recordlen);
+ /* else add handlers for other CPUs here */
+@@ -463,14 +461,9 @@ int is_cpu_supported(void)
}
if (seen == ALL) {
@@ -713,16 +681,4 @@
Eprintf("ERROR: Hygon Processor family %d:
mcelog does not support this processor. Please use the edac_mce_amd module
instead.\n", family);
return 0;
} else if (!strcmp(vendor,"GenuineIntel"))
-Index: mcelog-181/mcelog.h
-===================================================================
---- mcelog-181.orig/mcelog.h
-+++ mcelog-181/mcelog.h
-@@ -119,6 +119,7 @@ enum cputype {
- CPU_P6OLD,
- CPU_CORE2, /* 65nm and 45nm */
- CPU_K8,
-+ CPU_F10H,
- CPU_P4,
- CPU_NEHALEM,
- CPU_DUNNINGTON,
++++++ add-f11h-support.patch ++++++
--- /var/tmp/diff_new_pack.0GxPrU/_old 2023-06-17 22:20:09.563482477 +0200
+++ /var/tmp/diff_new_pack.0GxPrU/_new 2023-06-17 22:20:09.567482501 +0200
@@ -8,10 +8,10 @@
mcelog.h | 1 +
4 files changed, 26 insertions(+), 1 deletion(-)
-Index: mcelog-181/amd.c
+Index: mcelog-189/amd.c
===================================================================
---- mcelog-181.orig/amd.c
-+++ mcelog-181/amd.c
+--- mcelog-189.orig/amd.c
++++ mcelog-189/amd.c
@@ -155,6 +155,8 @@ enum cputype select_amd_cputype(u32 fami
return CPU_K8;
case 0x10:
@@ -61,47 +61,4 @@
default:
Eprintf("Huh? What family is it: 0x%x?!\n", cpu);
return;
-Index: mcelog-181/amd.h
-===================================================================
---- mcelog-181.orig/amd.h
-+++ mcelog-181/amd.h
-@@ -93,4 +93,5 @@ enum rrrr_ids {
-
- #define CASE_AMD_CPUS \
- case CPU_K8: \
-- case CPU_F10H
-+ case CPU_F10H: \
-+ case CPU_F11H
-Index: mcelog-181/mcelog.c
-===================================================================
---- mcelog-181.orig/mcelog.c
-+++ mcelog-181/mcelog.c
-@@ -230,6 +230,7 @@ static char *cputype_name[] = {
- [CPU_CORE2] = "Intel Core", /* 65nm and 45nm */
- [CPU_K8] = "AMD K8 and derivates",
- [CPU_F10H] = "AMD Greyhound",
-+ [CPU_F11H] = "AMD Griffin",
- [CPU_P4] = "Intel P4",
- [CPU_NEHALEM] = "Intel Xeon 5500 series / Core i3/5/7
(\"Nehalem/Westmere\")",
- [CPU_DUNNINGTON] = "Intel Xeon 7400 series",
-@@ -271,6 +272,7 @@ static struct config_choice cpu_choices[
- { "core2", CPU_CORE2 },
- { "k8", CPU_K8 },
- { "f10h", CPU_F10H },
-+ { "f11h", CPU_F11H },
- { "p4", CPU_P4 },
- { "dunnington", CPU_DUNNINGTON },
- { "xeon74xx", CPU_DUNNINGTON },
-Index: mcelog-181/mcelog.h
-===================================================================
---- mcelog-181.orig/mcelog.h
-+++ mcelog-181/mcelog.h
-@@ -120,6 +120,7 @@ enum cputype {
- CPU_CORE2, /* 65nm and 45nm */
- CPU_K8,
- CPU_F10H,
-+ CPU_F11H,
- CPU_P4,
- CPU_NEHALEM,
- CPU_DUNNINGTON,
++++++ add-f12h-support.patch ++++++
--- /var/tmp/diff_new_pack.0GxPrU/_old 2023-06-17 22:20:09.579482573 +0200
+++ /var/tmp/diff_new_pack.0GxPrU/_new 2023-06-17 22:20:09.583482597 +0200
@@ -8,10 +8,10 @@
mcelog.h | 1 +
4 files changed, 17 insertions(+), 1 deletion(-)
-Index: mcelog-181/amd.c
+Index: mcelog-189/amd.c
===================================================================
---- mcelog-181.orig/amd.c
-+++ mcelog-181/amd.c
+--- mcelog-189.orig/amd.c
++++ mcelog-189/amd.c
@@ -157,6 +157,8 @@ enum cputype select_amd_cputype(u32 fami
return CPU_F10H;
case 0x11:
@@ -44,10 +44,10 @@
default:
Eprintf("Huh? What family is it: 0x%x?!\n", cpu);
return;
-Index: mcelog-181/amd.h
+Index: mcelog-189/amd.h
===================================================================
---- mcelog-181.orig/amd.h
-+++ mcelog-181/amd.h
+--- mcelog-189.orig/amd.h
++++ mcelog-189/amd.h
@@ -9,6 +9,7 @@ enum amdcpu {
AMD_K8 = 0,
AMD_F10H,
@@ -56,43 +56,4 @@
AMD_F14H,
AMD_F15H,
AMD_F16H,
-@@ -94,4 +95,5 @@ enum rrrr_ids {
- #define CASE_AMD_CPUS \
- case CPU_K8: \
- case CPU_F10H: \
-- case CPU_F11H
-+ case CPU_F11H: \
-+ case CPU_F12H
-Index: mcelog-181/mcelog.c
-===================================================================
---- mcelog-181.orig/mcelog.c
-+++ mcelog-181/mcelog.c
-@@ -231,6 +231,7 @@ static char *cputype_name[] = {
- [CPU_K8] = "AMD K8 and derivates",
- [CPU_F10H] = "AMD Greyhound",
- [CPU_F11H] = "AMD Griffin",
-+ [CPU_F12H] = "AMD Llano",
- [CPU_P4] = "Intel P4",
- [CPU_NEHALEM] = "Intel Xeon 5500 series / Core i3/5/7
(\"Nehalem/Westmere\")",
- [CPU_DUNNINGTON] = "Intel Xeon 7400 series",
-@@ -273,6 +274,7 @@ static struct config_choice cpu_choices[
- { "k8", CPU_K8 },
- { "f10h", CPU_F10H },
- { "f11h", CPU_F11H },
-+ { "f12h", CPU_F12H },
- { "p4", CPU_P4 },
- { "dunnington", CPU_DUNNINGTON },
- { "xeon74xx", CPU_DUNNINGTON },
-Index: mcelog-181/mcelog.h
-===================================================================
---- mcelog-181.orig/mcelog.h
-+++ mcelog-181/mcelog.h
-@@ -121,6 +121,7 @@ enum cputype {
- CPU_K8,
- CPU_F10H,
- CPU_F11H,
-+ CPU_F12H,
- CPU_P4,
- CPU_NEHALEM,
- CPU_DUNNINGTON,
++++++ add-f14h-support.patch ++++++
--- /var/tmp/diff_new_pack.0GxPrU/_old 2023-06-17 22:20:09.595482669 +0200
+++ /var/tmp/diff_new_pack.0GxPrU/_new 2023-06-17 22:20:09.599482693 +0200
@@ -8,10 +8,10 @@
mcelog.h | 1
4 files changed, 93 insertions(+), 1 deletion(-)
-Index: mcelog-181/amd.c
+Index: mcelog-189/amd.c
===================================================================
---- mcelog-181.orig/amd.c
-+++ mcelog-181/amd.c
+--- mcelog-189.orig/amd.c
++++ mcelog-189/amd.c
@@ -159,6 +159,8 @@ enum cputype select_amd_cputype(u32 fami
return CPU_F11H;
case 0x12:
@@ -135,47 +135,4 @@
default:
Eprintf("Huh? What family is it: 0x%x?!\n", cpu);
return;
-Index: mcelog-181/amd.h
-===================================================================
---- mcelog-181.orig/amd.h
-+++ mcelog-181/amd.h
-@@ -96,4 +96,5 @@ enum rrrr_ids {
- case CPU_K8: \
- case CPU_F10H: \
- case CPU_F11H: \
-- case CPU_F12H
-+ case CPU_F12H: \
-+ case CPU_F14H
-Index: mcelog-181/mcelog.c
-===================================================================
---- mcelog-181.orig/mcelog.c
-+++ mcelog-181/mcelog.c
-@@ -232,6 +232,7 @@ static char *cputype_name[] = {
- [CPU_F10H] = "AMD Greyhound",
- [CPU_F11H] = "AMD Griffin",
- [CPU_F12H] = "AMD Llano",
-+ [CPU_F14H] = "AMD Bobcat",
- [CPU_P4] = "Intel P4",
- [CPU_NEHALEM] = "Intel Xeon 5500 series / Core i3/5/7
(\"Nehalem/Westmere\")",
- [CPU_DUNNINGTON] = "Intel Xeon 7400 series",
-@@ -275,6 +276,7 @@ static struct config_choice cpu_choices[
- { "f10h", CPU_F10H },
- { "f11h", CPU_F11H },
- { "f12h", CPU_F12H },
-+ { "f14h", CPU_F14H },
- { "p4", CPU_P4 },
- { "dunnington", CPU_DUNNINGTON },
- { "xeon74xx", CPU_DUNNINGTON },
-Index: mcelog-181/mcelog.h
-===================================================================
---- mcelog-181.orig/mcelog.h
-+++ mcelog-181/mcelog.h
-@@ -122,6 +122,7 @@ enum cputype {
- CPU_F10H,
- CPU_F11H,
- CPU_F12H,
-+ CPU_F14H,
- CPU_P4,
- CPU_NEHALEM,
- CPU_DUNNINGTON,
++++++ add-f15h-support.patch ++++++
--- /var/tmp/diff_new_pack.0GxPrU/_old 2023-06-17 22:20:09.607482741 +0200
+++ /var/tmp/diff_new_pack.0GxPrU/_new 2023-06-17 22:20:09.611482765 +0200
@@ -8,10 +8,10 @@
mcelog.h | 1
4 files changed, 165 insertions(+), 1 deletion(-)
-Index: mcelog-181/amd.c
+Index: mcelog-189/amd.c
===================================================================
---- mcelog-181.orig/amd.c
-+++ mcelog-181/amd.c
+--- mcelog-189.orig/amd.c
++++ mcelog-189/amd.c
@@ -72,6 +72,43 @@ static char *nbextendederr[] = {
"L3 Cache LRU Error"
};
@@ -221,47 +221,4 @@
default:
Eprintf("Huh? What family is it: 0x%x?!\n", cpu);
return;
-Index: mcelog-181/amd.h
-===================================================================
---- mcelog-181.orig/amd.h
-+++ mcelog-181/amd.h
-@@ -97,4 +97,5 @@ enum rrrr_ids {
- case CPU_F10H: \
- case CPU_F11H: \
- case CPU_F12H: \
-- case CPU_F14H
-+ case CPU_F14H: \
-+ case CPU_F15H
-Index: mcelog-181/mcelog.c
-===================================================================
---- mcelog-181.orig/mcelog.c
-+++ mcelog-181/mcelog.c
-@@ -233,6 +233,7 @@ static char *cputype_name[] = {
- [CPU_F11H] = "AMD Griffin",
- [CPU_F12H] = "AMD Llano",
- [CPU_F14H] = "AMD Bobcat",
-+ [CPU_F15H] = "AMD Bulldozer",
- [CPU_P4] = "Intel P4",
- [CPU_NEHALEM] = "Intel Xeon 5500 series / Core i3/5/7
(\"Nehalem/Westmere\")",
- [CPU_DUNNINGTON] = "Intel Xeon 7400 series",
-@@ -277,6 +278,7 @@ static struct config_choice cpu_choices[
- { "f11h", CPU_F11H },
- { "f12h", CPU_F12H },
- { "f14h", CPU_F14H },
-+ { "f15h", CPU_F15H },
- { "p4", CPU_P4 },
- { "dunnington", CPU_DUNNINGTON },
- { "xeon74xx", CPU_DUNNINGTON },
-Index: mcelog-181/mcelog.h
-===================================================================
---- mcelog-181.orig/mcelog.h
-+++ mcelog-181/mcelog.h
-@@ -123,6 +123,7 @@ enum cputype {
- CPU_F11H,
- CPU_F12H,
- CPU_F14H,
-+ CPU_F15H,
- CPU_P4,
- CPU_NEHALEM,
- CPU_DUNNINGTON,
++++++ add-f16h-support.patch ++++++
--- /var/tmp/diff_new_pack.0GxPrU/_old 2023-06-17 22:20:09.619482813 +0200
+++ /var/tmp/diff_new_pack.0GxPrU/_new 2023-06-17 22:20:09.623482838 +0200
@@ -8,10 +8,10 @@
mcelog.h | 1 +
4 files changed, 58 insertions(+), 1 deletion(-)
-Index: mcelog-181/amd.c
+Index: mcelog-189/amd.c
===================================================================
---- mcelog-181.orig/amd.c
-+++ mcelog-181/amd.c
+--- mcelog-189.orig/amd.c
++++ mcelog-189/amd.c
@@ -200,6 +200,8 @@ enum cputype select_amd_cputype(u32 fami
return CPU_F14H;
case 0x15:
@@ -93,47 +93,4 @@
default:
Eprintf("Huh? What family is it: 0x%x?!\n", cpu);
return;
-Index: mcelog-181/amd.h
-===================================================================
---- mcelog-181.orig/amd.h
-+++ mcelog-181/amd.h
-@@ -98,4 +98,5 @@ enum rrrr_ids {
- case CPU_F11H: \
- case CPU_F12H: \
- case CPU_F14H: \
-- case CPU_F15H
-+ case CPU_F15H: \
-+ case CPU_F16H
-Index: mcelog-181/mcelog.c
-===================================================================
---- mcelog-181.orig/mcelog.c
-+++ mcelog-181/mcelog.c
-@@ -234,6 +234,7 @@ static char *cputype_name[] = {
- [CPU_F12H] = "AMD Llano",
- [CPU_F14H] = "AMD Bobcat",
- [CPU_F15H] = "AMD Bulldozer",
-+ [CPU_F16H] = "AMD Jaguar",
- [CPU_P4] = "Intel P4",
- [CPU_NEHALEM] = "Intel Xeon 5500 series / Core i3/5/7
(\"Nehalem/Westmere\")",
- [CPU_DUNNINGTON] = "Intel Xeon 7400 series",
-@@ -279,6 +280,7 @@ static struct config_choice cpu_choices[
- { "f12h", CPU_F12H },
- { "f14h", CPU_F14H },
- { "f15h", CPU_F15H },
-+ { "f16h", CPU_F16H },
- { "p4", CPU_P4 },
- { "dunnington", CPU_DUNNINGTON },
- { "xeon74xx", CPU_DUNNINGTON },
-Index: mcelog-181/mcelog.h
-===================================================================
---- mcelog-181.orig/mcelog.h
-+++ mcelog-181/mcelog.h
-@@ -124,6 +124,7 @@ enum cputype {
- CPU_F12H,
- CPU_F14H,
- CPU_F15H,
-+ CPU_F16H,
- CPU_P4,
- CPU_NEHALEM,
- CPU_DUNNINGTON,
++++++ add_new_amd_cpu_defines ++++++
Index: mcelog-189/mkcputype
===================================================================
--- mcelog-189.orig/mkcputype
+++ mcelog-189/mkcputype
@@ -5,6 +5,12 @@ awk -F\| 'BEGIN {
print "enum cputype {" > "cputype.tmp"
print "\tCPU_GENERIC," > "cputype.tmp"
print "\tCPU_K8," > "cputype.tmp"
+ print "\tCPU_F10H," > "cputype.tmp"
+ print "\tCPU_F11H," > "cputype.tmp"
+ print "\tCPU_F12H," > "cputype.tmp"
+ print "\tCPU_F14H," > "cputype.tmp"
+ print "\tCPU_F15H," > "cputype.tmp"
+ print "\tCPU_F16H," > "cputype.tmp"
print "\n\n/* Insert any new non-intel CPU models before this line
*/\n\n" > "cputype.tmp"
print "\tCPU_INTEL," > "cputype.tmp"
@@ -44,6 +50,12 @@ END {
print "char *cputype_name[] = {" > "lookup_intel_cputype.tmp"
print "\t[CPU_GENERIC] = \"generic CPU\"," > "lookup_intel_cputype.tmp"
print "\t[CPU_K8] = \"AMD K8 and derivates\"," >
"lookup_intel_cputype.tmp"
+ print "\t[CPU_F10H] = \"AMD Greyhound\"," > "lookup_intel_cputype.tmp"
+ print "\t[CPU_F11H] = \"AMD Griffin\"," > "lookup_intel_cputype.tmp"
+ print "\t[CPU_F12H] = \"AMD Llano\"," > "lookup_intel_cputype.tmp"
+ print "\t[CPU_F14H] = \"AMD Bobcat\"," > "lookup_intel_cputype.tmp"
+ print "\t[CPU_F15H] = \"AMD Bulldozer\"," > "lookup_intel_cputype.tmp"
+ print "\t[CPU_F16H] = \"AMD Jaguar\"," > "lookup_intel_cputype.tmp"
print "\t[CPU_INTEL] = \"Intel generic architectural MCA\"," >
"lookup_intel_cputype.tmp"
print "\t[CPU_P4] = \"Intel P4\"," > "lookup_intel_cputype.tmp"
print "\t[CPU_TULSA] = \"Intel Xeon 7100 series\"," >
"lookup_intel_cputype.tmp"
++++++ email.patch ++++++
--- /var/tmp/diff_new_pack.0GxPrU/_old 2023-06-17 22:20:09.643482958 +0200
+++ /var/tmp/diff_new_pack.0GxPrU/_new 2023-06-17 22:20:09.647482981 +0200
@@ -7,23 +7,24 @@
msg.c | 8 ++
6 files changed, 346 insertions(+), 3 deletions(-)
-Index: mcelog-181/Makefile
+Index: mcelog-194/Makefile
===================================================================
---- mcelog-181.orig/Makefile
-+++ mcelog-181/Makefile
+--- mcelog-194.orig/Makefile
++++ mcelog-194/Makefile
@@ -1,3 +1,4 @@
+CONFIG_EMAIL := 1
CFLAGS := -g -Os
prefix := /usr
etcprefix :=
-@@ -38,15 +39,23 @@ OBJ := p4.o k8.o mcelog.o dmi.o tsc.o co
+@@ -38,16 +39,24 @@ OBJ := p4.o k8.o mcelog.o dmi.o tsc.o co
broadwell_de.o broadwell_epex.o skylake_xeon.o \
- denverton.o i10nm.o \
- msr.o bus.o unknown.o
+ denverton.o i10nm.o sapphire.o \
+ msr.o bus.o unknown.o lookup_intel_cputype.o
+EMAIL_OBJ := email.o
CLEAN := mcelog dmi tsc dbquery .depend .depend.X dbquery.o \
-- version.o version.c version.tmp
-+ ${EMAIL_OBJ} version.o version.c version.tmp
+ version.o version.c version.tmp cputype.h cputype.tmp \
+- lookup_intel_cputype.c lookup_intel_cputype.tmp
++ lookup_intel_cputype.c lookup_intel_cputype.tmp ${EMAIL_OBJ}
DOC := mce.pdf
ADD_DEFINES :=
@@ -40,8 +41,8 @@
+ $(CC) $(LDFLAGS) $^ ${LIBS} -o $@
# dbquery intentionally not installed by default
- install: mcelog mcelog.conf mcelog.conf.5 mcelog.triggers.5
-@@ -81,7 +90,7 @@ dbquery: db.o dbquery.o memutil.o
+ install: install-nodoc mcelog.conf.5 mcelog.triggers.5
+@@ -85,7 +94,7 @@ dbquery: db.o dbquery.o memutil.o
depend: .depend
%.o: %.c
@@ -50,10 +51,10 @@
version.tmp: FORCE
( printf "char version[] = \"" ; \
-Index: mcelog-181/email.c
+Index: mcelog-194/email.c
===================================================================
--- /dev/null
-+++ mcelog-181/email.c
++++ mcelog-194/email.c
@@ -0,0 +1,200 @@
+#include <unistd.h>
+#include <signal.h>
@@ -255,10 +256,10 @@
+ smtp_destroy_session (session);
+ return 0;
+}
-Index: mcelog-181/email.h
+Index: mcelog-194/email.h
===================================================================
--- /dev/null
-+++ mcelog-181/email.h
++++ mcelog-194/email.h
@@ -0,0 +1,34 @@
+#ifndef _MCELOG_EMAIL_H_
+#define _MCELOG_EMAIL_H_
@@ -294,10 +295,10 @@
+#endif
+
+#endif
-Index: mcelog-181/mcelog.c
+Index: mcelog-194/mcelog.c
===================================================================
---- mcelog-181.orig/mcelog.c
-+++ mcelog-181/mcelog.c
+--- mcelog-194.orig/mcelog.c
++++ mcelog-194/mcelog.c
@@ -37,6 +37,7 @@
#include <assert.h>
#include <signal.h>
@@ -325,7 +326,7 @@
static char *inputfile;
char *processor_flags;
static int foreground;
-@@ -1024,6 +1028,7 @@ void usage(void)
+@@ -906,6 +910,7 @@ void usage(void)
"--max-corr-err-counters Max page correctable error counters\n"
"--help Display this message.\n"
);
@@ -333,7 +334,7 @@
printf("\n");
print_cputypes();
}
-@@ -1095,6 +1100,7 @@ static struct option options[] = {
+@@ -977,6 +982,7 @@ static struct option options[] = {
{ "max-corr-err-counters", 1, NULL, O_MAX_CORR_ERR_COUNTERS },
{ "help", 0, NULL, O_HELP },
{ "is-cpu-supported", 0, NULL, O_IS_CPU_SUPPORTED },
@@ -341,7 +342,7 @@
{}
};
-@@ -1289,11 +1295,86 @@ static void drop_cred(void)
+@@ -1171,11 +1177,86 @@ static void drop_cred(void)
}
}
@@ -428,7 +429,7 @@
if (recordlen == 0) {
Wprintf("no data in mce record\n");
-@@ -1320,12 +1401,16 @@ static void process(int fd, unsigned rec
+@@ -1202,12 +1283,16 @@ static void process(int fd, unsigned rec
finish = 1;
if (!mce_filter(mce, recordlen))
continue;
@@ -445,7 +446,7 @@
flushlog();
}
-@@ -1439,6 +1524,8 @@ int main(int ac, char **av)
+@@ -1321,6 +1406,8 @@ int main(int ac, char **av)
noargs(ac, av);
fprintf(stderr, "mcelog %s\n", MCELOG_VERSION);
exit(0);
@@ -454,7 +455,7 @@
} else if (opt == 0)
break;
}
-@@ -1473,6 +1560,10 @@ int main(int ac, char **av)
+@@ -1355,6 +1442,10 @@ int main(int ac, char **av)
usage();
exit(1);
}
@@ -465,11 +466,11 @@
checkdmi();
general_setup();
-Index: mcelog-181/mcelog.h
+Index: mcelog-194/mcelog.h
===================================================================
---- mcelog-181.orig/mcelog.h
-+++ mcelog-181/mcelog.h
-@@ -157,6 +157,7 @@ enum cputype {
+--- mcelog-194.orig/mcelog.h
++++ mcelog-194/mcelog.h
+@@ -118,6 +118,7 @@ extern int open_logfile(char *fn);
enum option_ranges {
O_COMMON = 500,
O_DISKDB = 1000,
@@ -477,10 +478,10 @@
};
enum syslog_opt {
-Index: mcelog-181/msg.c
+Index: mcelog-194/msg.c
===================================================================
---- mcelog-181.orig/msg.c
-+++ mcelog-181/msg.c
+--- mcelog-194.orig/msg.c
++++ mcelog-194/msg.c
@@ -8,10 +8,13 @@
#include "mcelog.h"
#include "msg.h"
++++++ fix_setgroups_missing_call.patch ++++++
--- /var/tmp/diff_new_pack.0GxPrU/_old 2023-06-17 22:20:09.655483030 +0200
+++ /var/tmp/diff_new_pack.0GxPrU/_new 2023-06-17 22:20:09.659483053 +0200
@@ -2,10 +2,10 @@
mcelog.c | 9 +++++++++
1 file changed, 9 insertions(+)
-Index: mcelog-181/mcelog.c
+Index: mcelog-189/mcelog.c
===================================================================
---- mcelog-181.orig/mcelog.c
-+++ mcelog-181/mcelog.c
+--- mcelog-189.orig/mcelog.c
++++ mcelog-189/mcelog.c
@@ -37,6 +37,7 @@
#include <assert.h>
#include <signal.h>
@@ -14,7 +14,7 @@
#include <sys/wait.h>
#include <fnmatch.h>
#include "mcelog.h"
-@@ -1286,6 +1287,14 @@ static void general_setup(void)
+@@ -1155,6 +1156,14 @@ static void general_setup(void)
static void drop_cred(void)
{
++++++ mcelog-181.obscpio -> mcelog-194.obscpio ++++++
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/mcelog-181/Makefile new/mcelog-194/Makefile
--- old/mcelog-181/Makefile 2022-04-18 23:13:27.000000000 +0200
+++ new/mcelog-194/Makefile 2023-06-12 19:48:06.000000000 +0200
@@ -28,7 +28,7 @@
all: mcelog
-.PHONY: install clean depend FORCE
+.PHONY: install install-nodoc clean depend FORCE
OBJ := p4.o k8.o mcelog.o dmi.o tsc.o core2.o bitfield.o intel.o \
nehalem.o dunnington.o tulsa.o config.o memutil.o msg.o \
@@ -36,10 +36,11 @@
client.o cache.o sysfs.o yellow.o page.o rbtree.o \
sandy-bridge.o ivy-bridge.o haswell.o \
broadwell_de.o broadwell_epex.o skylake_xeon.o \
- denverton.o i10nm.o \
- msr.o bus.o unknown.o
+ denverton.o i10nm.o sapphire.o \
+ msr.o bus.o unknown.o lookup_intel_cputype.o
CLEAN := mcelog dmi tsc dbquery .depend .depend.X dbquery.o \
- version.o version.c version.tmp
+ version.o version.c version.tmp cputype.h cputype.tmp \
+ lookup_intel_cputype.c lookup_intel_cputype.tmp
DOC := mce.pdf
ADD_DEFINES :=
@@ -49,16 +50,11 @@
mcelog: ${OBJ} version.o
# dbquery intentionally not installed by default
-install: mcelog mcelog.conf mcelog.conf.5 mcelog.triggers.5
- mkdir -p $(DESTDIR)${etcprefix}/etc/mcelog $(DESTDIR)${prefix}/sbin
$(DESTDIR)$(MANDIR)/man5 $(DESTDIR)$(MANDIR)/man8
- install -m 755 -p mcelog $(DESTDIR)${prefix}/sbin/mcelog
+install: install-nodoc mcelog.conf.5 mcelog.triggers.5
+ mkdir -p $(DESTDIR)$(MANDIR)/man5 $(DESTDIR)$(MANDIR)/man8
install -m 644 -p mcelog.8 $(DESTDIR)$(MANDIR)/man8
install -m 644 -p mcelog.conf.5 $(DESTDIR)$(MANDIR)/man5
install -m 644 -p mcelog.triggers.5 $(DESTDIR)$(MANDIR)/man5
- install -m 644 -p -b mcelog.conf
$(DESTDIR)${etcprefix}/etc/mcelog/mcelog.conf
- for i in ${TRIGGERS} ; do
\
- install -m 755 -p -b triggers/$$i
$(DESTDIR)${etcprefix}/etc/mcelog ; \
- done
ifdef DOCDIR
install -d 755 $(DESTDIR)${DOCDIR}
install -m 644 -p ${DOC} $(DESTDIR)${DOCDIR}
@@ -67,6 +63,14 @@
echo "Consider defining DOCDIR to install additional documentation"
endif
+install-nodoc: mcelog mcelog.conf
+ mkdir -p $(DESTDIR)${etcprefix}/etc/mcelog $(DESTDIR)${prefix}/sbin
+ install -m 755 -p mcelog $(DESTDIR)${prefix}/sbin/mcelog
+ install -m 644 -p -b mcelog.conf
$(DESTDIR)${etcprefix}/etc/mcelog/mcelog.conf
+ for i in ${TRIGGERS} ; do
\
+ install -m 755 -p -b triggers/$$i
$(DESTDIR)${etcprefix}/etc/mcelog ; \
+ done
+
mcelog.conf.5: mcelog.conf config-intro.man
./genconfig.py mcelog.conf config-intro.man > mcelog.conf.5
@@ -102,7 +106,19 @@
version.c: version.tmp
cmp version.tmp version.c || mv version.tmp version.c
+cputype.tmp lookup_intel_cputype.tmp &: cputype.table
+ ./mkcputype
+
+cputype.h: cputype.tmp
+ cmp cputype.tmp cputype.h || mv cputype.tmp cputype.h
+
+lookup_intel_cputype.c: lookup_intel_cputype.tmp
+ cmp lookup_intel_cputype.c lookup_intel_cputype.tmp || mv
lookup_intel_cputype.tmp lookup_intel_cputype.c
+
+lookup_intel_cputype.o: cputype.h config.h
+
.depend: ${SRC}
+ [ -f cputype.h ] || touch cputype.h
${CC} -MM -I. ${SRC} > .depend.X && mv .depend.X .depend
include .depend
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/mcelog-181/client.c new/mcelog-194/client.c
--- old/mcelog-181/client.c 2022-04-18 23:13:27.000000000 +0200
+++ new/mcelog-194/client.c 2023-06-12 19:48:06.000000000 +0200
@@ -19,6 +19,7 @@
#include <sys/socket.h>
#include <sys/un.h>
#include <unistd.h>
+#include <string.h>
#include "mcelog.h"
#include "client.h"
#include "paths.h"
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/mcelog-181/cputype.table new/mcelog-194/cputype.table
--- old/mcelog-181/cputype.table 1970-01-01 01:00:00.000000000 +0100
+++ new/mcelog-194/cputype.table 2023-06-12 19:48:06.000000000 +0200
@@ -0,0 +1,39 @@
+CPU_ALDERLAKE|0x97,0x9A,0xBE|Alderlake|alderlake
+CPU_ARROWLAKE|0xC6|Arrowlake|arrowlake
+CPU_ATOM|0x1c,0x26,0x27,0x35,0x36,0x37,0x4a,0x4c,0x4d,0x5a,0x5d|ATOM|atom
+CPU_BROADWELL|0x3d,0x47|Broadwell|broadwell
+CPU_BROADWELL_DE|0x56|Intel Xeon (Broadwell) D family|broadwell-d
+CPU_BROADWELL_EPEX|0x4f|Intel Xeon v4 (Broadwell)
EP/EX|broadwell-ep,broadwell-ex,xeon-v4
+CPU_COMETLAKE|0xa5,0xa6|Cometlake|cometlake
+CPU_CORE2|0xf,0x17|Intel
Core|core2,xeon3100,xeon3200,xeon5100,xeon5200,xeon7200
+CPU_DENVERTON|0x5f|Denverton|denverton
+CPU_DUNNINGTON|0x1d|Intel Xeon 7400 series|dunnington,xeon7400,xeon74xx
+CPU_EMERALDRAPIDS|0xcf|Emeraldrapids server|emeraldrapids_server
+CPU_GRANDRIDGE|0xb6|Grandridge|grandridge
+CPU_GRANITERAPIDS|0xad,0xae|Graniterapids|graniterapids
+CPU_HASWELL|0x3c,0x45,0x46|Intel Xeon v3 (Haswell)
EP/EX|haswell-ep,haswell-ex,xeon-v3
+CPU_HASWELL_EPEX|0x3f|Haswell|haswell
+CPU_ICELAKE|0x7D,0x7E,0x9D|Icelake server D Family|icelake
+CPU_ICELAKE_DE|0x6C|Icelake|icelake-d
+CPU_ICELAKE_XEON|0x6A|Icelake server|icelake_server
+CPU_IVY_BRIDGE|0x3a|Intel Xeon v2 (Ivy Bridge)
EP/EX|ivybridge-ep,ivybridge-ex,xeon-v2
+CPU_IVY_BRIDGE_EPEX|0x3e|Ivy Bridge|ivybridge
+CPU_KABYLAKE|0x8E,0x9E|Kabylake|kabylake
+CPU_KNIGHTS_LANDING|0x57|Knights Landing|knightslanding
+CPU_KNIGHTS_MILL|0x85|Knights Mill|knightsmill
+CPU_LAKEFIELD|0x8A|Lakefield|lakefield
+CPU_LUNARLAKE|0xBD|Lunarlake|lunarlake
+CPU_METEORLAKE|0xac,0xaa|Meteorlake|meteorlake
+CPU_NEHALEM|0x1a,0x2c,0x1e,0x25|Intel Xeon 5500 series / Core i3/5/7
(\"Nehalem/Westmere\")|core_i3,core_i5,core_i7,nehalem,westmere,xeon5500
+CPU_P6OLD|0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE|Intel
PPro/P2/P3/old Xeon|p6old
+CPU_RAPTORLAKE|0xb7,0xba,0xbf|Raptorlake|raptorlake
+CPU_ROCKETLAKE|0xA7|Rocketlake|rocketlake
+CPU_SANDY_BRIDGE|0x2a|Sandy Bridge EP|sandybridge
+CPU_SANDY_BRIDGE_EP|0x2d|Sandy Bridge|sandybridge-ep
+CPU_SAPPHIRERAPIDS|0x8F|Sapphirerapids server|sapphirerapids_server
+CPU_SIERRAFOREST|0xaf|Sierraforest|sierraforest
+CPU_SKYLAKE|0x4e,0x5e|Skylake|skylake
+CPU_SKYLAKE_XEON|0x55|Skylake server|cascadelake_server,skylake_server
+CPU_TIGERLAKE|0x8C,0x8D|Tigerlake|tigerlake
+CPU_TREMONT_D|0x86|Tremont microserver|snowridge
+CPU_XEON75XX|0x2e,0x2f|Intel Xeon 7500 series|xeon7500,xeon75xx
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/mcelog-181/genconfig.py new/mcelog-194/genconfig.py
--- old/mcelog-181/genconfig.py 2022-04-18 23:13:27.000000000 +0200
+++ new/mcelog-194/genconfig.py 2023-06-12 19:48:06.000000000 +0200
@@ -1,7 +1,6 @@
-#!/usr/bin/python
+#!/usr/bin/env python3
# generate man config documentation from mcelog.conf example
# genconfig.py mcelog.conf intro.html
-from __future__ import print_function
import sys
import re
import argparse
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/mcelog-181/i10nm.c new/mcelog-194/i10nm.c
--- old/mcelog-181/i10nm.c 2022-04-18 23:13:27.000000000 +0200
+++ new/mcelog-194/i10nm.c 2023-06-12 19:48:06.000000000 +0200
@@ -353,13 +353,6 @@
[13 ... 15] = BT_IMC,
};
-static enum banktype sapphire[32] = {
- [4] = BT_PCU,
- [5] = BT_UPI,
- [12] = BT_M2M,
- [13 ... 20] = BT_IMC,
-};
-
void i10nm_decode_model(int cputype, int bank, u64 status, u64 misc)
{
enum banktype banktype;
@@ -375,9 +368,6 @@
case CPU_TREMONT_D:
banktype = tremont[bank];
break;
- case CPU_SAPPHIRERAPIDS:
- banktype = sapphire[bank];
- break;
default:
return;
}
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/mcelog-181/intel.c new/mcelog-194/intel.c
--- old/mcelog-181/intel.c 2022-04-18 23:13:27.000000000 +0200
+++ new/mcelog-194/intel.c 2023-06-12 19:48:06.000000000 +0200
@@ -27,29 +27,24 @@
#include "haswell.h"
#include "skylake_xeon.h"
#include "i10nm.h"
+#include "sapphire.h"
int memory_error_support;
void intel_cpu_init(enum cputype cpu)
{
- if (cpu == CPU_NEHALEM || cpu == CPU_XEON75XX || cpu == CPU_INTEL ||
- cpu == CPU_SANDY_BRIDGE || cpu == CPU_SANDY_BRIDGE_EP ||
- cpu == CPU_IVY_BRIDGE || cpu == CPU_IVY_BRIDGE_EPEX ||
- cpu == CPU_HASWELL || cpu == CPU_HASWELL_EPEX || cpu ==
CPU_BROADWELL ||
- cpu == CPU_BROADWELL_DE || cpu == CPU_BROADWELL_EPEX ||
- cpu == CPU_KNIGHTS_LANDING || cpu == CPU_KNIGHTS_MILL ||
- cpu == CPU_SKYLAKE || cpu == CPU_SKYLAKE_XEON ||
- cpu == CPU_KABYLAKE || cpu == CPU_DENVERTON || cpu == CPU_ICELAKE ||
- cpu == CPU_ICELAKE_XEON || cpu == CPU_ICELAKE_DE ||
- cpu == CPU_TREMONT_D || cpu == CPU_COMETLAKE ||
- cpu == CPU_TIGERLAKE || cpu == CPU_ROCKETLAKE ||
- cpu == CPU_ALDERLAKE || cpu == CPU_LAKEFIELD ||
- cpu == CPU_SAPPHIRERAPIDS || cpu == CPU_RAPTORLAKE)
+ if (cpu == CPU_ATOM || cpu == CPU_CORE2 || cpu == CPU_DUNNINGTON ||
+ cpu == CPU_GENERIC || cpu == CPU_K8 || cpu == CPU_P4 ||
+ cpu == CPU_P6OLD || cpu == CPU_TULSA)
+ memory_error_support = 0;
+ else
memory_error_support = 1;
}
enum cputype select_intel_cputype(int family, int model)
{
+ int ret;
+
if (family == 15) {
if (model == 6)
return CPU_TULSA;
@@ -59,74 +54,9 @@
if (model >= 0x1a && model != 28)
memory_error_support = 1;
- if (model < 0xf)
- return CPU_P6OLD;
- else if (model == 0xf || model == 0x17) /* Merom/Penryn */
- return CPU_CORE2;
- else if (model == 0x1d)
- return CPU_DUNNINGTON;
- else if (model == 0x1a || model == 0x2c || model == 0x1e ||
- model == 0x25)
- return CPU_NEHALEM;
- else if (model == 0x2e || model == 0x2f)
- return CPU_XEON75XX;
- else if (model == 0x2a)
- return CPU_SANDY_BRIDGE;
- else if (model == 0x2d)
- return CPU_SANDY_BRIDGE_EP;
- else if (model == 0x3a)
- return CPU_IVY_BRIDGE;
- else if (model == 0x3e)
- return CPU_IVY_BRIDGE_EPEX;
- else if (model == 0x3c || model == 0x45 || model == 0x46)
- return CPU_HASWELL;
- else if (model == 0x3f)
- return CPU_HASWELL_EPEX;
- else if (model == 0x3d)
- return CPU_BROADWELL;
- else if (model == 0x4f)
- return CPU_BROADWELL_EPEX;
- else if (model == 0x56)
- return CPU_BROADWELL_DE;
- else if (model == 0x57)
- return CPU_KNIGHTS_LANDING;
- else if (model == 0x85)
- return CPU_KNIGHTS_MILL;
- else if (model == 0x1c || model == 0x26 || model == 0x27 ||
- model == 0x35 || model == 0x36 || model == 0x36 ||
- model == 0x37 || model == 0x4a || model == 0x4c ||
- model == 0x4d || model == 0x5a || model == 0x5d)
- return CPU_ATOM;
- else if (model == 0x4e || model == 0x5e)
- return CPU_SKYLAKE;
- else if (model == 0x55)
- return CPU_SKYLAKE_XEON;
- else if (model == 0x8E || model == 0x9E)
- return CPU_KABYLAKE;
- else if (model == 0x5f)
- return CPU_DENVERTON;
- else if (model == 0x7D || model == 0x7E || model == 0x9D)
- return CPU_ICELAKE;
- else if (model == 0x6A)
- return CPU_ICELAKE_XEON;
- else if (model == 0x6C)
- return CPU_ICELAKE_DE;
- else if (model == 0x86)
- return CPU_TREMONT_D;
- else if (model == 0xa5 || model == 0xa6)
- return CPU_COMETLAKE;
- else if (model == 0x8C || model == 0x8D)
- return CPU_TIGERLAKE;
- else if (model == 0xA7)
- return CPU_ROCKETLAKE;
- else if (model == 0x97)
- return CPU_ALDERLAKE;
- else if (model == 0x8A)
- return CPU_LAKEFIELD;
- else if (model == 0x8F)
- return CPU_SAPPHIRERAPIDS;
- else if (model == 0xb7)
- return CPU_RAPTORLAKE;
+ ret = lookup_intel_cputype(model);
+ if (ret != -1)
+ return ret;
if (model > 0x1a) {
Eprintf("Family 6 Model %u CPU: only decoding
architectural errors\n",
model);
@@ -144,11 +74,7 @@
int is_intel_cpu(int cpu)
{
- switch (cpu) {
- CASE_INTEL_CPUS:
- return 1;
- }
- return 0;
+ return cpu >= CPU_INTEL;
}
static int intel_memory_error(struct mce *m, unsigned recordlen)
@@ -179,9 +105,12 @@
case CPU_ICELAKE_XEON:
case CPU_ICELAKE_DE:
case CPU_TREMONT_D:
- case CPU_SAPPHIRERAPIDS:
i10nm_memerr_misc(m, channel, dimm);
break;
+ case CPU_SAPPHIRERAPIDS:
+ case CPU_EMERALDRAPIDS:
+ sapphire_memerr_misc(m, channel, dimm);
+ break;
default:
break;
}
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/mcelog-181/intel.h new/mcelog-194/intel.h
--- old/mcelog-181/intel.h 2022-04-18 23:13:27.000000000 +0200
+++ new/mcelog-194/intel.h 2023-06-12 19:48:06.000000000 +0200
@@ -4,40 +4,3 @@
void intel_cpu_init(enum cputype cpu);
extern int memory_error_support;
-
-#define CASE_INTEL_CPUS \
- case CPU_P6OLD: \
- case CPU_CORE2: \
- case CPU_NEHALEM: \
- case CPU_DUNNINGTON: \
- case CPU_TULSA: \
- case CPU_P4: \
- case CPU_INTEL: \
- case CPU_XEON75XX: \
- case CPU_SANDY_BRIDGE_EP: \
- case CPU_SANDY_BRIDGE: \
- case CPU_IVY_BRIDGE: \
- case CPU_IVY_BRIDGE_EPEX: \
- case CPU_HASWELL: \
- case CPU_HASWELL_EPEX: \
- case CPU_BROADWELL: \
- case CPU_BROADWELL_DE: \
- case CPU_BROADWELL_EPEX: \
- case CPU_ATOM: \
- case CPU_KNIGHTS_LANDING: \
- case CPU_KNIGHTS_MILL: \
- case CPU_SKYLAKE: \
- case CPU_SKYLAKE_XEON: \
- case CPU_KABYLAKE: \
- case CPU_DENVERTON: \
- case CPU_ICELAKE_XEON: \
- case CPU_ICELAKE_DE: \
- case CPU_TREMONT_D: \
- case CPU_COMETLAKE: \
- case CPU_TIGERLAKE: \
- case CPU_ROCKETLAKE: \
- case CPU_ALDERLAKE: \
- case CPU_LAKEFIELD: \
- case CPU_SAPPHIRERAPIDS: \
- case CPU_RAPTORLAKE
-
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/mcelog-181/mcelog.c new/mcelog-194/mcelog.c
--- old/mcelog-181/mcelog.c 2022-04-18 23:13:27.000000000 +0200
+++ new/mcelog-194/mcelog.c 2023-06-12 19:48:06.000000000 +0200
@@ -123,16 +123,14 @@
if (bank >= MCE_EXTENDED_BANK)
return extended_bankname(bank);
- switch (cputype) {
- case CPU_K8:
- return k8_bank_name(bank);
- CASE_INTEL_CPUS:
+ if (cputype >= CPU_INTEL)
return intel_bank_name(bank);
+ else if (cputype == CPU_K8)
+ return k8_bank_name(bank);
+
/* add banks of other cpu types here */
- default:
- sprintf(numeric, "BANK %d", bank);
- return numeric;
- }
+ sprintf(numeric, "BANK %d", bank);
+ return numeric;
}
static void resolveaddr(unsigned long long addr)
@@ -146,17 +144,14 @@
{
if (!filter_bogus)
return 1;
+
/* Filter out known broken MCEs */
- switch (cputype) {
- case CPU_K8:
- return mce_filter_k8(m);
- /* add more buggy CPUs here */
- CASE_INTEL_CPUS:
+ if (cputype >= CPU_INTEL)
return mce_filter_intel(m, recordlen);
- default:
- case CPU_GENERIC:
- return 1;
- }
+ else if (cputype == CPU_K8)
+ return mce_filter_k8(m);
+
+ return 1;
}
static void print_tsc(int cpunum, __u64 tsc, unsigned long time)
@@ -219,109 +214,7 @@
return c.v;
}
-static char *cputype_name[] = {
- [CPU_GENERIC] = "generic CPU",
- [CPU_P6OLD] = "Intel PPro/P2/P3/old Xeon",
- [CPU_CORE2] = "Intel Core", /* 65nm and 45nm */
- [CPU_K8] = "AMD K8 and derivates",
- [CPU_P4] = "Intel P4",
- [CPU_NEHALEM] = "Intel Xeon 5500 series / Core i3/5/7
(\"Nehalem/Westmere\")",
- [CPU_DUNNINGTON] = "Intel Xeon 7400 series",
- [CPU_TULSA] = "Intel Xeon 7100 series",
- [CPU_INTEL] = "Intel generic architectural MCA",
- [CPU_XEON75XX] = "Intel Xeon 7500 series",
- [CPU_SANDY_BRIDGE] = "Sandy Bridge", /* Fill in better name */
- [CPU_SANDY_BRIDGE_EP] = "Sandy Bridge EP", /* Fill in better name */
- [CPU_IVY_BRIDGE] = "Ivy Bridge", /* Fill in better name */
- [CPU_IVY_BRIDGE_EPEX] = "Intel Xeon v2 (Ivy Bridge) EP/EX", /* Fill in
better name */
- [CPU_HASWELL] = "Haswell", /* Fill in better name */
- [CPU_HASWELL_EPEX] = "Intel Xeon v3 (Haswell) EP/EX",
- [CPU_BROADWELL] = "Broadwell",
- [CPU_BROADWELL_DE] = "Intel Xeon (Broadwell) D family",
- [CPU_BROADWELL_EPEX] = "Intel Xeon v4 (Broadwell) EP/EX",
- [CPU_KNIGHTS_LANDING] = "Knights Landing",
- [CPU_KNIGHTS_MILL] = "Knights Mill",
- [CPU_ATOM] = "ATOM",
- [CPU_SKYLAKE] = "Skylake",
- [CPU_SKYLAKE_XEON] = "Skylake server",
- [CPU_KABYLAKE] = "Kabylake",
- [CPU_DENVERTON] = "Denverton",
- [CPU_ICELAKE] = "Icelake",
- [CPU_ICELAKE_XEON] = "Icelake server",
- [CPU_ICELAKE_DE] = "Icelake server D Family",
- [CPU_TREMONT_D] = "Tremont microserver",
- [CPU_COMETLAKE] = "Cometlake",
- [CPU_TIGERLAKE] = "Tigerlake",
- [CPU_ROCKETLAKE] = "Rocketlake",
- [CPU_ALDERLAKE] = "Alderlake",
- [CPU_LAKEFIELD] = "Lakefield",
- [CPU_SAPPHIRERAPIDS] = "Sapphirerapids server",
- [CPU_RAPTORLAKE] = "Raptorlake",
-};
-
-static struct config_choice cpu_choices[] = {
- { "generic", CPU_GENERIC },
- { "p6old", CPU_P6OLD },
- { "core2", CPU_CORE2 },
- { "k8", CPU_K8 },
- { "p4", CPU_P4 },
- { "dunnington", CPU_DUNNINGTON },
- { "xeon74xx", CPU_DUNNINGTON },
- { "xeon7400", CPU_DUNNINGTON },
- { "xeon5500", CPU_NEHALEM },
- { "xeon5200", CPU_CORE2 },
- { "xeon5000", CPU_P4 },
- { "xeon5100", CPU_CORE2 },
- { "xeon3100", CPU_CORE2 },
- { "xeon3200", CPU_CORE2 },
- { "core_i7", CPU_NEHALEM },
- { "core_i5", CPU_NEHALEM },
- { "core_i3", CPU_NEHALEM },
- { "nehalem", CPU_NEHALEM },
- { "westmere", CPU_NEHALEM },
- { "xeon71xx", CPU_TULSA },
- { "xeon7100", CPU_TULSA },
- { "tulsa", CPU_TULSA },
- { "intel", CPU_INTEL },
- { "xeon75xx", CPU_XEON75XX },
- { "xeon7500", CPU_XEON75XX },
- { "xeon7200", CPU_CORE2 },
- { "xeon7100", CPU_P4 },
- { "sandybridge", CPU_SANDY_BRIDGE }, /* Fill in better name */
- { "sandybridge-ep", CPU_SANDY_BRIDGE_EP }, /* Fill in better name */
- { "ivybridge", CPU_IVY_BRIDGE }, /* Fill in better name */
- { "ivybridge-ep", CPU_IVY_BRIDGE_EPEX },
- { "ivybridge-ex", CPU_IVY_BRIDGE_EPEX },
- { "haswell", CPU_HASWELL }, /* Fill in better name */
- { "haswell-ep", CPU_HASWELL_EPEX },
- { "haswell-ex", CPU_HASWELL_EPEX },
- { "broadwell", CPU_BROADWELL },
- { "broadwell-d", CPU_BROADWELL_DE },
- { "broadwell-ep", CPU_BROADWELL_EPEX },
- { "broadwell-ex", CPU_BROADWELL_EPEX },
- { "knightslanding", CPU_KNIGHTS_LANDING },
- { "knightsmill", CPU_KNIGHTS_MILL },
- { "xeon-v2", CPU_IVY_BRIDGE_EPEX },
- { "xeon-v3", CPU_HASWELL_EPEX },
- { "xeon-v4", CPU_BROADWELL_EPEX },
- { "atom", CPU_ATOM },
- { "skylake", CPU_SKYLAKE },
- { "skylake_server", CPU_SKYLAKE_XEON },
- { "cascadelake_server", CPU_SKYLAKE_XEON },
- { "kabylake", CPU_KABYLAKE },
- { "denverton", CPU_DENVERTON },
- { "icelake_server", CPU_ICELAKE_XEON },
- { "icelake-d", CPU_ICELAKE_DE },
- { "snowridge", CPU_TREMONT_D },
- { "cometlake", CPU_COMETLAKE },
- { "tigerlake", CPU_TIGERLAKE },
- { "rocketlake", CPU_ROCKETLAKE },
- { "alderlake", CPU_ALDERLAKE },
- { "lakefield", CPU_LAKEFIELD },
- { "sapphirerapids_server", CPU_SAPPHIRERAPIDS },
- { "raptorlake", CPU_RAPTORLAKE },
- { NULL }
-};
+extern struct config_choice cpu_choices[];
static void print_cputypes(void)
{
@@ -449,17 +342,12 @@
time_t t = m->time;
Wprintf("TIME %llu %s", m->time, ctime(&t));
}
- switch (cputype) {
- case CPU_K8:
+ if (cputype == CPU_K8)
decode_k8_mc(m, &ismemerr);
- break;
- CASE_INTEL_CPUS:
+ else if (cputype >= CPU_INTEL)
decode_intel_mc(m, cputype, &ismemerr, recordlen);
- break;
- /* add handlers for other CPUs here */
- default:
- break;
- }
+ /* else add handlers for other CPUs here */
+
/* decode all status bits here */
Wprintf("STATUS %llx MCGSTATUS %llx\n", m->status, m->mcgstatus);
n = 0;
@@ -487,17 +375,11 @@
mod,
step);
}
- if (cputype != CPU_SANDY_BRIDGE_EP && cputype != CPU_IVY_BRIDGE_EPEX &&
- cputype != CPU_HASWELL_EPEX && cputype != CPU_BROADWELL &&
- cputype != CPU_BROADWELL_DE && cputype != CPU_BROADWELL_EPEX &&
- cputype != CPU_KNIGHTS_LANDING && cputype != CPU_KNIGHTS_MILL &&
- cputype != CPU_SKYLAKE && cputype != CPU_SKYLAKE_XEON &&
- cputype != CPU_KABYLAKE && cputype != CPU_DENVERTON &&
- cputype != CPU_ICELAKE_XEON && cputype != CPU_ICELAKE_DE &&
- cputype != CPU_TREMONT_D && cputype != CPU_COMETLAKE &&
- cputype != CPU_TIGERLAKE && cputype != CPU_ROCKETLAKE &&
- cputype != CPU_ALDERLAKE && cputype != CPU_LAKEFIELD &&
- cputype != CPU_SAPPHIRERAPIDS && cputype != CPU_RAPTORLAKE)
+ if (cputype == CPU_ATOM || cputype == CPU_CORE2 || cputype ==
CPU_DUNNINGTON ||
+ cputype == CPU_GENERIC || cputype == CPU_HASWELL || cputype ==
CPU_ICELAKE ||
+ cputype == CPU_INTEL || cputype == CPU_IVY_BRIDGE || cputype ==
CPU_K8 ||
+ cputype == CPU_NEHALEM || cputype == CPU_P4 || cputype == CPU_P6OLD
||
+ cputype == CPU_SANDY_BRIDGE || cputype == CPU_TULSA || cputype ==
CPU_XEON75XX)
resolveaddr(m->addr);
}
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/mcelog-181/mcelog.conf new/mcelog-194/mcelog.conf
--- old/mcelog-181/mcelog.conf 2022-04-18 23:13:27.000000000 +0200
+++ new/mcelog-194/mcelog.conf 2023-06-12 19:48:06.000000000 +0200
@@ -109,12 +109,16 @@
# Errors per DIMM exceeds the threshold.
# Note when the hardware does not report DIMMs this might also
# be per channel.
-# The default of 10/24h is reasonable for server quality
-# DDR3 DIMMs as of 2009/10.
+# The default of 10/24h was reasonable for server quality
+# DDR3 DIMMs as of 2009/10. Newer systems can benefit from
+# more aggressive page offline when corrected errors are seen
+# See:
+#
https://www.intel.com/content/dam/www/public/us/en/documents/intel-and-samsung-mrt-improving-memory-reliability-at-data-centers.pdf
+# for details.
#uc-error-trigger = dimm-error-trigger
uc-error-threshold = 1 / 24h
#ce-error-trigger = dimm-error-trigger
-ce-error-threshold = 10 / 24h
+ce-error-threshold = 2 / 24h
[socket]
# Enable memory error accounting per socket.
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/mcelog-181/mcelog.h new/mcelog-194/mcelog.h
--- old/mcelog-181/mcelog.h 2022-04-18 23:13:27.000000000 +0200
+++ new/mcelog-194/mcelog.h 2023-06-12 19:48:06.000000000 +0200
@@ -113,46 +113,7 @@
extern int open_logfile(char *fn);
-/* Don't forget to update mcelog.c:cputype_name[] too */
-enum cputype {
- CPU_GENERIC,
- CPU_P6OLD,
- CPU_CORE2, /* 65nm and 45nm */
- CPU_K8,
- CPU_P4,
- CPU_NEHALEM,
- CPU_DUNNINGTON,
- CPU_TULSA,
- CPU_INTEL, /* Intel architectural errors */
- CPU_XEON75XX,
- CPU_SANDY_BRIDGE,
- CPU_SANDY_BRIDGE_EP,
- CPU_IVY_BRIDGE,
- CPU_IVY_BRIDGE_EPEX,
- CPU_HASWELL,
- CPU_HASWELL_EPEX,
- CPU_BROADWELL,
- CPU_BROADWELL_DE,
- CPU_BROADWELL_EPEX,
- CPU_KNIGHTS_LANDING,
- CPU_KNIGHTS_MILL,
- CPU_ATOM,
- CPU_SKYLAKE,
- CPU_SKYLAKE_XEON,
- CPU_KABYLAKE,
- CPU_DENVERTON,
- CPU_ICELAKE,
- CPU_ICELAKE_XEON,
- CPU_ICELAKE_DE,
- CPU_TREMONT_D,
- CPU_COMETLAKE,
- CPU_TIGERLAKE,
- CPU_ROCKETLAKE,
- CPU_ALDERLAKE,
- CPU_LAKEFIELD,
- CPU_SAPPHIRERAPIDS,
- CPU_RAPTORLAKE,
-};
+#include "cputype.h"
enum option_ranges {
O_COMMON = 500,
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/mcelog-181/mkcputype new/mcelog-194/mkcputype
--- old/mcelog-181/mkcputype 1970-01-01 01:00:00.000000000 +0100
+++ new/mcelog-194/mkcputype 2023-06-12 19:48:06.000000000 +0200
@@ -0,0 +1,65 @@
+#!/bin/bash
+
+awk -F\| 'BEGIN {
+ print "/* Do not edit. Autogenerated from cputype.table */" >
"cputype.tmp"
+ print "enum cputype {" > "cputype.tmp"
+ print "\tCPU_GENERIC," > "cputype.tmp"
+ print "\tCPU_K8," > "cputype.tmp"
+
+ print "\n\n/* Insert any new non-intel CPU models before this line
*/\n\n" > "cputype.tmp"
+ print "\tCPU_INTEL," > "cputype.tmp"
+ print "\tCPU_P4," > "cputype.tmp"
+ print "\tCPU_TULSA," > "cputype.tmp"
+
+ print "/* Do not edit. Autogenerated from cputype.table */" >
"lookup_intel_cputype.tmp"
+ print "#include <stddef.h>\n" > "lookup_intel_cputype.tmp"
+ print "#include \"cputype.h\"\n" > "lookup_intel_cputype.tmp"
+ print "#include \"config.h\"\n" > "lookup_intel_cputype.tmp"
+ print "enum cputype lookup_intel_cputype(int model)" >
"lookup_intel_cputype.tmp"
+ print "{" > "lookup_intel_cputype.tmp"
+ print "\tswitch (model) {" > "lookup_intel_cputype.tmp"
+}
+{
+ printf("\t%s,\n", $1) > "cputype.tmp"
+
+ n = split($2, model, ",")
+ for (i = 1; i <= n; i++)
+ printf("\tcase %s:\n", model[i]) > "lookup_intel_cputype.tmp"
+ printf("\t\treturn %s;\n", $1) > "lookup_intel_cputype.tmp"
+
+ cputype_name = cputype_name "\t[" $1 "] = \"" $3 "\",\n"
+
+ n = split($4, choice, ",")
+ for (i = 1; i <= n; i++)
+ cpu_choices = cpu_choices "\t{ \"" choice[i] "\"," $1 " },\n"
+}
+END {
+ print "};\n" > "cputype.tmp"
+ print "enum cputype lookup_intel_cputype(int model);" > "cputype.tmp"
+ print "extern char *cputype_name[];" > "cputype.tmp"
+
+ print "\tdefault:\n\t\treturn -1;" > "lookup_intel_cputype.tmp"
+ print "\t}\n}\n" > "lookup_intel_cputype.tmp"
+
+ print "char *cputype_name[] = {" > "lookup_intel_cputype.tmp"
+ print "\t[CPU_GENERIC] = \"generic CPU\"," > "lookup_intel_cputype.tmp"
+ print "\t[CPU_K8] = \"AMD K8 and derivates\"," >
"lookup_intel_cputype.tmp"
+ print "\t[CPU_INTEL] = \"Intel generic architectural MCA\"," >
"lookup_intel_cputype.tmp"
+ print "\t[CPU_P4] = \"Intel P4\"," > "lookup_intel_cputype.tmp"
+ print "\t[CPU_TULSA] = \"Intel Xeon 7100 series\"," >
"lookup_intel_cputype.tmp"
+ print cputype_name > "lookup_intel_cputype.tmp"
+ print "};\n" > "lookup_intel_cputype.tmp"
+
+ print "struct config_choice cpu_choices[] = {" >
"lookup_intel_cputype.tmp"
+ print "\t{ \"generic\", CPU_GENERIC }," > "lookup_intel_cputype.tmp"
+ print "\t{ \"k8\", CPU_K8 }," > "lookup_intel_cputype.tmp"
+ print "\t{ \"intel\", CPU_INTEL }," > "lookup_intel_cputype.tmp"
+ print "\t{ \"p4\", CPU_P4 }," > "lookup_intel_cputype.tmp"
+ print "\t{ \"xeon5000\", CPU_P4 }," > "lookup_intel_cputype.tmp"
+ print "\t{ \"xeon7100\", CPU_P4 }," > "lookup_intel_cputype.tmp"
+ print "\t{ \"tulsa\", CPU_TULSA }," > "lookup_intel_cputype.tmp"
+ print "\t{ \"xeon7100\", CPU_TULSA }," > "lookup_intel_cputype.tmp"
+ print "\t{ \"xeon71xx\", CPU_TULSA }," > "lookup_intel_cputype.tmp"
+ printf("%s", cpu_choices) > "lookup_intel_cputype.tmp"
+ print "\t{ NULL }\n};" > "lookup_intel_cputype.tmp"
+}' cputype.table
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/mcelog-181/p4.c new/mcelog-194/p4.c
--- old/mcelog-181/p4.c 2022-04-18 23:13:27.000000000 +0200
+++ new/mcelog-194/p4.c 2023-06-12 19:48:06.000000000 +0200
@@ -41,6 +41,7 @@
#include "skylake_xeon.h"
#include "denverton.h"
#include "i10nm.h"
+#include "sapphire.h"
/* decode mce for P4/Xeon and Core2 family */
@@ -308,8 +309,9 @@
case CPU_SKYLAKE_XEON:
return skylake_s_ce_type(bank, status, misc);
case CPU_ICELAKE_XEON:
- case CPU_SAPPHIRERAPIDS:
return i10nm_ce_type(bank, status, misc);
+ case CPU_SAPPHIRERAPIDS:
+ case CPU_EMERALDRAPIDS:
default:
return 0;
}
@@ -460,9 +462,12 @@
case CPU_ICELAKE_XEON:
case CPU_ICELAKE_DE:
case CPU_TREMONT_D:
- case CPU_SAPPHIRERAPIDS:
i10nm_decode_model(cputype, log->bank, log->status, log->misc);
break;
+ case CPU_SAPPHIRERAPIDS:
+ case CPU_EMERALDRAPIDS:
+ sapphire_decode_model(cputype, log->bank, log->status,
log->misc);
+ break;
case CPU_DENVERTON:
denverton_decode_model(cputype, log->bank, log->status,
log->misc);
break;
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/mcelog-181/sapphire.c new/mcelog-194/sapphire.c
--- old/mcelog-181/sapphire.c 1970-01-01 01:00:00.000000000 +0100
+++ new/mcelog-194/sapphire.c 2023-06-12 19:48:06.000000000 +0200
@@ -0,0 +1,474 @@
+/* Copyright (C) 2023 Intel Corporation
+ Decode Intel Xeon 4th generation specific machine check errors.
+
+ mcelog is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public
+ License as published by the Free Software Foundation; version
+ 2.
+
+ mcelog is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should find a copy of v2 of the GNU General Public License somewhere
+ on your Linux system; if not, write to the Free Software Foundation,
+ Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+ Author: Tony Luck
+*/
+
+#include "mcelog.h"
+#include "bitfield.h"
+#include "sapphire.h"
+#include "memdb.h"
+
+static char *pcu_1[] = {
+ [0x0D] = "MCA_LLC_BIST_ACTIVE_TIMEOUT",
+ [0x0E] = "MCA_DMI_TRAINING_TIMEOUT",
+ [0x0F] = "MCA_DMI_STRAP_SET_ARRIVAL_TIMEOUT",
+ [0x10] = "MCA_DMI_CPU_RESET_ACK_TIMEOUT",
+ [0x11] = "MCA_MORE_THAN_ONE_LT_AGENT",
+ [0x14] = "MCA_INCOMPATIBLE_PCH_TYPE",
+ [0x1E] = "MCA_BIOS_RST_CPL_INVALID_SEQ",
+ [0x1F] = "MCA_BIOS_INVALID_PKG_STATE_CONFIG",
+ [0x2D] = "MCA_PCU_PMAX_CALIB_ERROR",
+ [0x2E] = "MCA_TSC100_SYNC_TIMEOUT",
+ [0x3A] = "MCA_GPSB_TIMEOUT",
+ [0x3B] = "MCA_PMSB_TIMEOUT",
+ [0x3E] = "MCA_IOSFSB_PMREQ_CMP_TIMEOUT",
+ [0x40] = "MCA_SVID_VCCIN_VR_ICC_MAX_FAILURE",
+ [0x42] = "MCA_SVID_VCCIN_VR_VOUT_FAILURE",
+ [0x43] = "MCA_SVID_CPU_VR_CAPABILITY_ERROR",
+ [0x44] = "MCA_SVID_CRITICAL_VR_FAILED",
+ [0x45] = "MCA_SVID_SA_ITD_ERROR",
+ [0x46] = "MCA_SVID_READ_REG_FAILED",
+ [0x47] = "MCA_SVID_WRITE_REG_FAILED",
+ [0x4A] = "MCA_SVID_PKGC_REQUEST_FAILED",
+ [0x4B] = "MCA_SVID_IMON_REQUEST_FAILED",
+ [0x4C] = "MCA_SVID_ALERT_REQUEST_FAILED",
+ [0x4D] = "MCA_SVID_MCP_VR_RAMP_ERROR",
+ [0x56] = "MCA_FIVR_PD_HARDERR",
+ [0x58] = "MCA_WATCHDOG_TIMEOUT_PKGC_SECONDARY",
+ [0x59] = "MCA_WATCHDOG_TIMEOUT_PKGC_MAIN",
+ [0x5A] = "MCA_WATCHDOG_TIMEOUT_PKGS_MAIN",
+ [0x5B] = "MCA_WATCHDOG_TIMEOUT_MSG_CH_FSM",
+ [0x5C] = "MCA_WATCHDOG_TIMEOUT_BULK_CR_FSM",
+ [0x5D] = "MCA_WATCHDOG_TIMEOUT_IOSFSB_FSM",
+ [0x60] = "MCA_PKGS_SAFE_WP_TIMEOUT",
+ [0x61] = "MCA_PKGS_CPD_UNCPD_TIMEOUT",
+ [0x62] = "MCA_PKGS_INVALID_REQ_PCH",
+ [0x63] = "MCA_PKGS_INVALID_REQ_INTERNAL",
+ [0x64] = "MCA_PKGS_INVALID_RSP_INTERNAL",
+ [0x65 ... 0x7A] = "MCA_PKGS_RESET_PREP_TIMEOUT",
+ [0x7B] = "MCA_PKGS_SMBUS_VPP_PAUSE_TIMEOUT",
+ [0x7C] = "MCA_PKGS_SMBUS_MCP_PAUSE_TIMEOUT",
+ [0x7D] = "MCA_PKGS_SMBUS_SPD_PAUSE_TIMEOUT",
+ [0x80] = "MCA_PKGC_DISP_BUSY_TIMEOUT",
+ [0x81] = "MCA_PKGC_INVALID_RSP_PCH",
+ [0x83] = "MCA_PKGC_WATCHDOG_HANG_CBZ_DOWN",
+ [0x84] = "MCA_PKGC_WATCHDOG_HANG_CBZ_UP",
+ [0x87] = "MCA_PKGC_WATCHDOG_HANG_C2_BLKMASTER",
+ [0x88] = "MCA_PKGC_WATCHDOG_HANG_C2_PSLIMIT",
+ [0x89] = "MCA_PKGC_WATCHDOG_HANG_SETDISP",
+ [0x8B] = "MCA_PKGC_ALLOW_L1_ERROR",
+ [0x90] = "MCA_RECOVERABLE_DIE_THERMAL_TOO_HOT",
+ [0xA0] = "MCA_ADR_SIGNAL_TIMEOUT",
+ [0xA1] = "MCA_BCLK_FREQ_OC_ABOVE_THRESHOLD",
+ [0xB0] = "MCA_DISPATCHER_RUN_BUSY_TIMEOUT",
+ [0xC0] = "MCA_DISPATCHER_RUN_BUSY_TIMEOUT",
+};
+
+static char *pcu_2[] = {
+ [0x04] = "Clock/power IP response timeout",
+ [0x05] = "SMBus controller raised SMI",
+ [0x09] = "PM controller received invalid transaction",
+};
+
+static char *pcu_3[] = {
+ [0x01] = "Instruction address out of valid space",
+ [0x02] = "Double bit RAM error on Instruction Fetch",
+ [0x03] = "Invalid OpCode seen",
+ [0x04] = "Stack Underflow",
+ [0x05] = "Stack Overflow",
+ [0x06] = "Data address out of valid space",
+ [0x07] = "Double bit RAM error on Data Fetch",
+};
+
+static char *pcu_4[] = {
+ [0x01] = "MCE when CR4.MCE is clear",
+ [0x02] = "MCE when MCIP bit is set",
+ [0x03] = "MCE under WPS",
+ [0x04] = "Unrecoverable error during security flow execution",
+ [0x05] = "SW triple fault shutdown",
+ [0x06] = "VMX exit consistency check failures",
+ [0x07] = "RSM consistency check failures",
+ [0x08] = "Invalid conditions on protected mode SMM entry",
+ [0x09] = "Unrecoverable error during security flow execution",
+};
+
+static struct field pcu1[] = {
+ FIELD(0, pcu_1),
+ {}
+};
+
+static struct field pcu2[] = {
+ FIELD(0, pcu_2),
+ {}
+};
+
+static struct field pcu3[] = {
+ FIELD(0, pcu_3),
+ {}
+};
+
+static struct field pcu4[] = {
+ FIELD(0, pcu_4),
+ {}
+};
+
+static struct field upi1[] = {
+ SBITFIELD(22, "Phy Control Error"),
+ SBITFIELD(23, "Unexpected Retry.Ack flit"),
+ SBITFIELD(24, "Unexpected Retry.Req flit"),
+ SBITFIELD(25, "RF parity error"),
+ SBITFIELD(26, "Routeback Table error"),
+ SBITFIELD(27, "Unexpected Tx Protocol flit (EOP, Header or Data)"),
+ SBITFIELD(28, "Rx Header-or-Credit BGF credit overflow/underflow"),
+ SBITFIELD(29, "Link Layer Reset still in progress when Phy enters L0"),
+ SBITFIELD(30, "Link Layer reset initiated while protocol traffic not
idle"),
+ SBITFIELD(31, "Link Layer Tx Parity Error"),
+ {}
+};
+
+static char *upi_2[] = {
+ [0x00] = "Phy Initialization Failure",
+ [0x01] = "Phy Detected Drift Buffer Alarm",
+ [0x02] = "Phy Detected Latency Buffer Rollover",
+ [0x10] = "LL Rx detected CRC error: unsuccessful LLR (entered Abort
state)",
+ [0x11] = "LL Rx Unsupported/Undefined packet",
+ [0x12] = "LL or Phy Control Error",
+ [0x13] = "LL Rx Parameter Exception",
+ [0x15] = "UC LL Rx SGX MAC Error",
+ [0x1F] = "LL Detected Control Error",
+ [0x20] = "Phy Initialization Abort",
+ [0x21] = "Phy Inband Reset",
+ [0x22] = "Phy Lane failure, recovery in x8 width",
+ [0x23] = "Phy L0c error corrected without Phy reset",
+ [0x24] = "Phy L0c error triggering Phy reset",
+ [0x25] = "Phy L0p exit error corrected with reset",
+ [0x30] = "LL Rx detected CRC error: successful LLR without Phy Reinit",
+ [0x31] = "LL Rx detected CRC error: successful LLR with Phy Reinit",
+};
+
+static struct field upi2[] = {
+ FIELD(0, upi_2),
+ {}
+};
+
+static char *m2m_0[] = {
+ [0x01] = "Read ECC error",
+ [0x02] = "Bucket1 error",
+ [0x03] = "RdTrkr Parity error",
+ [0x05] = "Prefetch channel mismatch",
+ [0x07] = "Read completion parity error",
+ [0x08] = "Response parity error",
+ [0x09] = "Timeout error",
+ [0x0A] = "CMI reserved credit pool error",
+ [0x0B] = "CMI total credit count error",
+ [0x0C] = "CMI credit oversubscription error",
+};
+
+static struct field m2m[] = {
+ FIELD(0, m2m_0),
+ {}
+};
+
+static char *imc_0[] = {
+ [0x01] = "Address parity error",
+ [0x02] = "Data parity error",
+ [0x03] = "Data ECC error",
+ [0x04] = "Data byte enable parity error",
+ [0x07] = "Transaction ID parity error",
+ [0x08] = "Corrected patrol scrub error",
+ [0x10] = "Uncorrected patrol scrub error",
+ [0x20] = "Corrected spare error",
+ [0x40] = "Uncorrected spare error",
+ [0x80] = "Corrected read error",
+ [0xA0] = "Uncorrected read error",
+ [0xC0] = "Uncorrected metadata",
+};
+
+static char *imc_1[] = {
+ [0x00] = "WDB read parity error",
+ [0x08] = "DDR link failure",
+};
+
+static char *imc_2[] = {
+ [0x00] = "DDR5 command / address parity error",
+};
+
+static char *imc_4[] = {
+ [0x00] = "RPQ parity (primary) error",
+};
+
+static char *imc_8[] = {
+ [0x00] = "DDR-T bad request",
+ [0x01] = "DDR Data response to an invalid entry",
+ [0x02] = "DDR data response to an entry not expecting data",
+ [0x03] = "DDR completion to an invalid entry",
+ [0x04] = "DDR-T completion to an invalid entry",
+ [0x05] = "DDR data/completion FIFO overflow",
+ [0x06] = "DDR-T ERID correctable parity error",
+ [0x07] = "DDR-T ERID uncorrectable error",
+ [0x08] = "DDR-T interrupt received while outstanding interrupt was not
ACKed",
+ [0x09] = "ERID FI FO overflow",
+ [0x0A] = "DDR-T error on FNV write credits",
+ [0x0B] = "DDR-T error on FNV read credits",
+ [0x0C] = "DDR-T scheduler error",
+ [0x0D] = "DDR-T FNV error event",
+ [0x0E] = "DDR-T FNV thermal event",
+ [0x0F] = "CMI packet while idle",
+ [0x10] = "DDR_T_RPQ_REQ_PARITY_ERR",
+ [0x11] = "DDR_T_WPQ_REQ_PARITY_ERR",
+ [0x12] = "2LM_NMFILLWR_CAM_ERR",
+ [0x13] = "CMI_CREDIT_OVERSUB_ERR",
+ [0x14] = "CMI_CREDIT_TOTAL_ERR",
+ [0x15] = "CMI_CREDIT_RSVD_POOL_ERR",
+ [0x16] = "DDR_T_RD_ERROR",
+ [0x17] = "WDB_FIFO_ERR",
+ [0x18] = "CMI_REQ_FIFO_OVERFLOW",
+ [0x19] = "CMI_REQ_FIFO_UNDERFLOW",
+ [0x1A] = "CMI_RSP_FIFO_OVERFLOW",
+ [0x1B] = "CMI_RSP_FIFO_UNDERFLOW",
+ [0x1C] = "CMI _MISC_MC_CRDT_ERRORS",
+ [0x1D] = "CMI_MISC_MC_ARB_ERRORS",
+ [0x1E] = "DDR_T_WR_CMPL_FI FO_OVERFLOW",
+ [0x1F] = "DDR_T_WR_CMPL_FI FO_UNDERFLOW",
+ [0x20] = "CMI_RD_CPL_FIFO_OVERFLOW",
+ [0x21] = "CMI_RD_CPL_FIFO_UNDERFLOW",
+ [0x22] = "TME_KEY_PAR_ERR",
+ [0x23] = "TME_CMI_MISC_ERR",
+ [0x24] = "TME_CMI_OVFL_ERR",
+ [0x25] = "TME_CMI_UFL_ERR",
+ [0x26] = "TME_TEM_SECURE_ERR",
+ [0x27] = "TME_UFILL_PAR_ERR",
+ [0x29] = "INTERNAL_ERR",
+ [0x2A] = "TME_INTEGRITY_ERR",
+ [0x2B] = "TME_TDX_ERR",
+ [0x2C] = "TME_UFILL_TEM_SECURE_ERR",
+ [0x2D] = "TME_KEY_POISON_ERR",
+ [0x2E] = "TME_SECURITY_ENGINE_ERR",
+};
+
+static char *imc_10[] = {
+ [0x08] = "CORR_PATSCRUB_MIRR2ND_ERR",
+ [0x10] = "UC_PATSCRUB_MIRR2ND_ERR",
+ [0x20] = "COR_SPARE_MIRR2ND_ERR",
+ [0x40] = "UC_SPARE_MIRR2ND_ERR",
+ [0x80] = "HA_RD_MIRR2ND_ERR",
+ [0xA0] = "HA_UNCORR_RD_MIRR2ND_ERR",
+};
+
+static struct field imc0[] = {
+ FIELD(0, imc_0),
+ {}
+};
+
+static struct field imc1[] = {
+ FIELD(0, imc_1),
+ {}
+};
+
+static struct field imc2[] = {
+ FIELD(0, imc_2),
+ {}
+};
+
+static struct field imc4[] = {
+ FIELD(0, imc_4),
+ {}
+};
+
+static struct field imc8[] = {
+ FIELD(0, imc_8),
+ {}
+};
+
+static struct field imc10[] = {
+ FIELD(0, imc_10),
+ {}
+};
+
+static void sapphire_imc_misc(bool hbm, u64 status, u64 misc)
+{
+ u32 column = EXTRACT(misc, 9, 18) << 2;
+ u32 row = EXTRACT(misc, 19, 39);
+ u32 bank = EXTRACT(misc, 39, 40);
+ u32 bankgroup = EXTRACT(misc, 37, 38) | (EXTRACT(misc, 41, 41) << 2);
+ u32 fdevice = EXTRACT(misc, 43, 48);
+ u32 hbm_fdevice = EXTRACT(misc, 51, 55);
+ u32 subrank = EXTRACT(misc, 52, 55);
+ u32 rank = EXTRACT(misc, 56, 58);
+ u32 eccmode = EXTRACT(misc, 59, 62);
+ u32 transient = EXTRACT(misc, 63, 63);
+
+ Wprintf("bank: 0x%x bankgroup: 0x%x row: 0x%x column: 0x%x\n", bank,
bankgroup, row, column);
+ if (!transient && !EXTRACT(status, 61, 61)) {
+ if (hbm)
+ Wprintf("failed device: 0x%x,0x%x\n", hbm_fdevice,
fdevice);
+ else
+ Wprintf("failed device: 0x%x\n", fdevice);
+ }
+ Wprintf("rank: 0x%x subrank: 0x%x\n", rank, subrank);
+ if (hbm) {
+ switch (eccmode) {
+ case 1:
+ Wprintf("HBM 64B read\n");
+ break;
+ case 9:
+ Wprintf("HBM 32B read\n");
+ break;
+ }
+ } else {
+ Wprintf("ecc mode: ");
+ switch (eccmode) {
+ case 0: Wprintf("SDDC 2LM memory mode\n"); break;
+ case 1: Wprintf("SDDC\n"); break;
+ case 2: Wprintf("SDDC+1 2LM memory mode\n"); break;
+ case 3: Wprintf("SDDC+1\n"); break;
+ case 4: Wprintf("ADDDC 2LM memory mode\n"); break;
+ case 5: Wprintf("ADDDC\n"); break;
+ case 6: Wprintf("ADDDC+1 2LM memory mode\n"); break;
+ case 7: Wprintf("ADDDC+1\n"); break;
+ case 8: Wprintf("DDRT read\n"); break;
+ default: Wprintf("unknown\n"); break;
+ }
+ }
+ if (transient)
+ Wprintf("transient\n");
+}
+
+enum banktype {
+ BT_UNKNOWN,
+ BT_PCU,
+ BT_UPI,
+ BT_M2M,
+ BT_IMC,
+ BT_HBMM2M,
+ BT_HBMIMC,
+};
+
+static enum banktype sapphire[32] = {
+ [4] = BT_PCU,
+ [5] = BT_UPI,
+ [12] = BT_M2M,
+ [13 ... 20] = BT_IMC,
+ [29] = BT_HBMM2M,
+ [30 ... 31] = BT_HBMIMC,
+};
+
+void sapphire_decode_model(int cputype, int bank, u64 status, u64 misc)
+{
+ enum banktype banktype;
+ u64 f;
+
+ switch (cputype) {
+ case CPU_SAPPHIRERAPIDS:
+ case CPU_EMERALDRAPIDS:
+ banktype = sapphire[bank];
+ break;
+ default:
+ return;
+ }
+
+ switch (banktype) {
+ case BT_UNKNOWN:
+ break;
+
+ case BT_PCU:
+ Wprintf("PCU: ");
+ f = EXTRACT(status, 24, 31);
+ if (f)
+ decode_bitfield(f, pcu1);
+ f = EXTRACT(status, 20, 23);
+ if (f)
+ decode_bitfield(f, pcu2);
+ f = EXTRACT(status, 16, 19);
+ if (f) {
+ if (EXTRACT(status, 0, 15) != 0x40C)
+ decode_bitfield(f, pcu3);
+ else
+ decode_bitfield(f, pcu4);
+ }
+ break;
+
+ case BT_UPI:
+ Wprintf("UPI: ");
+ f = EXTRACT(status, 22, 31);
+ if (f)
+ decode_bitfield(status, upi1);
+ f = EXTRACT(status, 16, 21);
+ decode_bitfield(f, upi2);
+ break;
+
+ case BT_HBMM2M:
+ Wprintf("HBM: ");
+ /*fallthrough*/
+
+ case BT_M2M:
+ Wprintf("M2M: ");
+ f = EXTRACT(status, 24, 25);
+ if (f == 1)
+ Wprintf("HBM Error\n");
+ f = EXTRACT(status, 16, 23);
+ decode_bitfield(f, m2m);
+ break;
+
+ case BT_HBMIMC:
+ Wprintf("HBM: ");
+ /*fallthrough*/
+
+ case BT_IMC:
+ Wprintf("MemCtrl: ");
+ f = EXTRACT(status, 16, 23);
+ switch (EXTRACT(status, 24, 31)) {
+ case 0: decode_bitfield(f, imc0); break;
+ case 1: decode_bitfield(f, imc1); break;
+ case 2: decode_bitfield(f, imc2); break;
+ case 4: decode_bitfield(f, imc4); break;
+ case 8: decode_bitfield(f, imc8); break;
+ case 0x10: decode_bitfield(f, imc10); break;
+ }
+ sapphire_imc_misc(bank >= 30, status, misc);
+ break;
+ }
+}
+
+/*
+ * There isn't enough information to identify the DIMM. But
+ * we can derive the channel from the bank number.
+ * There can be four memory controllers with two channels each.
+ */
+void sapphire_memerr_misc(struct mce *m, int *channel, int *dimm)
+{
+ u64 status = m->status;
+ unsigned int chan;
+
+ /* Check this is a memory error */
+ if (!test_prefix(7, status & 0xefff))
+ return;
+
+ chan = EXTRACT(status, 0, 3);
+ if (chan == 0xf)
+ return;
+
+ switch (m->bank) {
+ case 13 ... 20:
+ channel[0] = m->bank - 13;
+ break;
+ case 30 ... 31:
+ channel[0] = 8 + m->bank - 30;
+ break;
+ }
+}
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/mcelog-181/sapphire.h new/mcelog-194/sapphire.h
--- old/mcelog-181/sapphire.h 1970-01-01 01:00:00.000000000 +0100
+++ new/mcelog-194/sapphire.h 2023-06-12 19:48:06.000000000 +0200
@@ -0,0 +1,2 @@
+void sapphire_decode_model(int cputype, int bank, u64 status, u64 misc);
+void sapphire_memerr_misc(struct mce *m, int *channel, int *dimm);
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/mcelog-181/tests/pfa/PFA_test_howto
new/mcelog-194/tests/pfa/PFA_test_howto
--- old/mcelog-181/tests/pfa/PFA_test_howto 2022-04-18 23:13:27.000000000
+0200
+++ new/mcelog-194/tests/pfa/PFA_test_howto 2023-06-12 19:48:06.000000000
+0200
@@ -36,9 +36,9 @@
- Install page-types tool, which is accompanied with Linux kernel source
(2.6.32 or newer).
- # cd $KERNEL_SRC/Documentation/vm/
- # gcc -o page-types page-types.c
- # cp page-types /usr/bin/
+ # cd $KERNEL_SRC/tools/vm/
+ # make
+ # cp page-types /usr/sbin/
++++++ mcelog.obsinfo ++++++
--- /var/tmp/diff_new_pack.0GxPrU/_old 2023-06-17 22:20:09.823484039 +0200
+++ /var/tmp/diff_new_pack.0GxPrU/_new 2023-06-17 22:20:09.827484064 +0200
@@ -1,5 +1,5 @@
name: mcelog
-version: 181
-mtime: 1650316407
-commit: a4edca25ef3bd8780ae1dc54bc203973ec7f1640
+version: 194
+mtime: 1686592086
+commit: 04d51981e8805c4200f5a03b4216c8621bc52ace
++++++ mcelog_invert_prefill_db_warning.patch ++++++
--- /var/tmp/diff_new_pack.0GxPrU/_old 2023-06-17 22:20:09.875484352 +0200
+++ /var/tmp/diff_new_pack.0GxPrU/_new 2023-06-17 22:20:09.879484376 +0200
@@ -2,11 +2,9 @@
memdb.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
-Index: mcelog-181/memdb.c
-===================================================================
---- mcelog-181.orig/memdb.c
-+++ mcelog-181/memdb.c
-@@ -431,11 +431,11 @@ void prefill_memdb(int do_dmi)
+--- a/memdb.c
++++ b/memdb.c
+@@ -431,11 +431,11 @@
md->location = xstrdup(bl);
md->name = xstrdup(dmi_getstring(&d->header,
d->device_locator));
}
