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commit 019936c83511ab99731b92e1c47893a6620b7a0f Author: raiden00pl <[email protected]> AuthorDate: Sat Oct 24 10:44:05 2026 +0200 boards/nucleo-u5a5zj-q: fix LPTIM1 kernel clock frequency LPTIM1 is clocked from MSIK (CCIPR3 LPTIM1SEL reset value), not HCLK, and LPTIM1 cannot select HCLK at all. MSIK runs at 4 MHz on this board. Signed-off-by: raiden00pl <[email protected]> Assisted-by: Claude Code --- boards/arm/stm32u5/nucleo-u5a5zj-q/include/board.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/include/board.h b/boards/arm/stm32u5/nucleo-u5a5zj-q/include/board.h index 762ad05272c..60ba97e1ad4 100644 --- a/boards/arm/stm32u5/nucleo-u5a5zj-q/include/board.h +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/include/board.h @@ -131,7 +131,7 @@ * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define STM32_LPTIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_LPTIM1_CLKIN 4000000 /* MSIK */ #define STM32_LPTIM2_CLKIN STM32_HCLK_FREQUENCY /* DMA Channel/Stream Selections ********************************************/
