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commit 17b70edfc7109b92ef70218a98ef4e2223fceaf6 Author: raiden00pl <[email protected]> AuthorDate: Mon Oct 26 13:22:37 2026 +0100 arch/arm/src/common/stm32: unify LPTIM drivers Use the common LPTIM driver for all STM32 families and remove the STM32L4 copy and its register header. The LPTIM register layout is described by two IP versions taken from the reference SVD files: - STM32_HAVE_IP_LPTIM_V1: IER and CMP, optional OR, CFGR2 and RCR (F4, F7, G0, G4, H7, L0, L4, L5, WB, WL5) - STM32_HAVE_IP_LPTIM_V2: DIER and capture/compare channels (C5, H5, H7RS, N6, U0, U3, U5) The interrupt and the base address of each instance come from the family headers, the RCC bits from stm32_lptim_clk.h. Changes compared to the old drivers: - setclocksource() selects the external or the internal clock only, the kernel clock is selected by the RCC configuration as on STM32F7. The STM32L4 driver also wrote RCC_CCIPR. - setchannel() configures the board GPIO_LPTIMn_CHkOUT pins like the STM32L4 PWM driver, instead of the GPIO_LPTIMn_OUT_k pinmap alternatives. - STM32H5 LPTIM2 builds, STM32_LPTIM2_BASE was missing the _BASE suffix. The STM32F7 LPTIM1 interrupt is renamed to STM32_IRQ_LPTIM1 as on the other families and the STM32U5 APB3RSTR LPTIM reset bits are added. Signed-off-by: raiden00pl <[email protected]> Assisted-by: Claude Code --- .github/CODEOWNERS | 3 - Documentation/guides/chip-specific/stm32_ports.rst | 6 +- LICENSE | 68 -- arch/arm/include/stm32f7/stm32f72xx73xx_irq.h | 2 +- arch/arm/include/stm32f7/stm32f74xx75xx_irq.h | 2 +- arch/arm/include/stm32f7/stm32f76xx77xx_irq.h | 2 +- arch/arm/src/common/stm32/CMakeLists.txt | 3 +- arch/arm/src/common/stm32/Kconfig.periph | 8 +- arch/arm/src/common/stm32/Make.defs | 2 - arch/arm/src/common/stm32/hardware/stm32_lptim.h | 227 +++--- arch/arm/src/stm32c5/Kconfig | 1 + arch/arm/src/stm32f4/Kconfig | 1 + arch/arm/src/stm32f7/Kconfig | 3 +- arch/arm/src/stm32g0/Kconfig | 1 + arch/arm/src/stm32g4/Kconfig | 1 + .../src/stm32h5/hardware/stm32h5xxx_memorymap.h | 2 +- arch/arm/src/stm32l0/Kconfig | 1 + arch/arm/src/stm32l4/CMakeLists.txt | 4 - arch/arm/src/stm32l4/Kconfig | 1 + arch/arm/src/stm32l4/Make.defs | 4 - arch/arm/src/stm32l4/hardware/stm32l4_lptim.h | 137 ---- arch/arm/src/stm32l4/stm32l4_lptim.c | 799 --------------------- arch/arm/src/stm32l4/stm32l4_lptim.h | 216 ------ arch/arm/src/stm32l4/stm32l4_pwm.h | 2 +- arch/arm/src/stm32l5/Kconfig | 1 + arch/arm/src/stm32n6/Kconfig | 1 + arch/arm/src/stm32u0/Kconfig | 1 + arch/arm/src/stm32u3/Kconfig | 1 + arch/arm/src/stm32u5/Kconfig | 1 + arch/arm/src/stm32u5/hardware/stm32_rcc.h | 6 + arch/arm/src/stm32wb/Kconfig | 1 + arch/arm/src/stm32wl5/Kconfig | 1 + 32 files changed, 170 insertions(+), 1339 deletions(-) diff --git a/.github/CODEOWNERS b/.github/CODEOWNERS index ef44e9566ec..f8e021a8ead 100644 --- a/.github/CODEOWNERS +++ b/.github/CODEOWNERS @@ -4304,7 +4304,6 @@ arch/arm/src/stm32l4/hardware/stm32l4_exti.h [email protected] xiaoxiang@xi arch/arm/src/stm32l4/hardware/stm32l4_flash.h [email protected] [email protected] [email protected] [email protected] arch/arm/src/stm32l4/hardware/stm32l4_gpio.h [email protected] [email protected] [email protected] [email protected] arch/arm/src/stm32l4/hardware/stm32l4_i2c.h [email protected] [email protected] -arch/arm/src/stm32l4/hardware/stm32l4_lptim.h [email protected] [email protected] [email protected] [email protected] arch/arm/src/stm32l4/hardware/stm32l4_memorymap.h [email protected] [email protected] [email protected] [email protected] arch/arm/src/stm32l4/hardware/stm32l4_pinmap.h [email protected] [email protected] [email protected] arch/arm/src/stm32l4/hardware/stm32l4_pwr.h [email protected] [email protected] @@ -4384,8 +4383,6 @@ arch/arm/src/stm32l4/stm32l4_irq.c [email protected] [email protected] pau arch/arm/src/stm32l4/stm32l4_iwdg.c [email protected] [email protected] [email protected] arch/arm/src/stm32l4/stm32l4_lowputc.c [email protected] [email protected] [email protected] [email protected] arch/arm/src/stm32l4/stm32l4_lowputc.h [email protected] [email protected] [email protected] -arch/arm/src/stm32l4/stm32l4_lptim.c [email protected] [email protected] [email protected] [email protected] -arch/arm/src/stm32l4/stm32l4_lptim.h [email protected] [email protected] [email protected] arch/arm/src/stm32l4/stm32l4_lse.c [email protected] [email protected] [email protected] [email protected] arch/arm/src/stm32l4/stm32l4_mpuinit.c [email protected] [email protected] [email protected] [email protected] arch/arm/src/stm32l4/stm32l4_mpuinit.h [email protected] [email protected] diff --git a/Documentation/guides/chip-specific/stm32_ports.rst b/Documentation/guides/chip-specific/stm32_ports.rst index 9495305322f..1c07c7475ac 100644 --- a/Documentation/guides/chip-specific/stm32_ports.rst +++ b/Documentation/guides/chip-specific/stm32_ports.rst @@ -508,7 +508,7 @@ FLASH to be done arch/arm/src/stm32l4/stm32l4_flash.c GPIO to be done arch/arm/src/stm32l4/stm32l4_gpio.c I2C to be done arch/arm/src/stm32l4/stm32l4_i2c.c IWDG v1 arch/arm/src/common/stm32/stm32_iwdg.c -LPTIM to be done arch/arm/src/stm32l4/stm32l4_lptim.c +LPTIM v1 arch/arm/src/common/stm32/stm32_lptim.c PWR to be done arch/arm/src/stm32l4/stm32l4_pwr.c QSPI to be done arch/arm/src/stm32l4/stm32l4_qspi.c RCC to be done arch/arm/src/stm32l4/stm32l4_rcc.c @@ -623,7 +623,7 @@ TIM v3 arch/arm/src/common/stm32/stm32_tim.c USART/LPUART v3 arch/arm/src/stm32h5/stm32_serial.c USB FS arch/arm/src/stm32h5/stm32_usbfs.c WWDG v3 arch/arm/src/common/stm32/stm32_wwdg.c -LPTIM n/a arch/arm/src/stm32h5/stm32_lptim.c +LPTIM v2 arch/arm/src/common/stm32/stm32_lptim.c PULSECOUNT n/a arch/arm/src/common/stm32/stm32_pulsecount.c PWM n/a arch/arm/src/stm32h5/stm32_pwm.c RNG n/a arch/arm/src/stm32h5/stm32_rng.c @@ -666,7 +666,7 @@ WWDG v2, H7RS v3 arch/arm/src/common/stm32/stm32_wwdg.c AES/CRYP n/a arch/arm/src/stm32h7/stm32_aes.c BBSRAM n/a arch/arm/src/stm32h7/stm32_bbsram.c CAPTURE n/a arch/arm/src/stm32h7/stm32_capture.c -LPTIM n/a arch/arm/src/stm32h7/stm32_lptim.c +LPTIM v1, H7RS v2 arch/arm/src/common/stm32/stm32_lptim.c PULSECOUNT n/a arch/arm/src/common/stm32/stm32_pulsecount.c PWM n/a arch/arm/src/stm32h7/stm32_pwm.c QENCODER n/a arch/arm/src/common/stm32/stm32_qencoder.c diff --git a/LICENSE b/LICENSE index c028bb3db78..6964f1b7754 100644 --- a/LICENSE +++ b/LICENSE @@ -4642,39 +4642,6 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32l4/hardware/stm32l4_lptim.h -============================================= - - Copyright (C) 2016 Motorola Mobility, LLC. All rights reserved. - Copyright (C) 2009, 2011-2012, 2017 Gregory Nutt. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions -are met: - -1. Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. -2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. -3. Neither the name NuttX nor the names of its contributors may be - used to endorse or promote products derived from this software - without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -POSSIBILITY OF SUCH DAMAGE. - arch/arm/src/stm32l4/stm32l4_comp.c ====================================== Copyright (c) 2017 Gregory Nutt. All rights reserved. @@ -4816,41 +4783,6 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32l4/stm32l4_lptim.c -arch/arm/src/stm32l4/stm32l4_lptim.h -==================================== - - Copyright (C) 2011 Uros Platise. All rights reserved. - Copyright (C) 2016 Motorola Mobility, LLC. All rights reserved. - Copyright (C) 2011-2012, 2017 Gregory Nutt. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions -are met: - -1. Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. -2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. -3. Neither the name NuttX nor the names of its contributors may be - used to endorse or promote products derived from this software - without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -POSSIBILITY OF SUCH DAMAGE. - arch/arm/src/stm32l4/stm32l4_uid.c arch/arm/src/stm32l4/stm32l4_uid.h ================================== diff --git a/arch/arm/include/stm32f7/stm32f72xx73xx_irq.h b/arch/arm/include/stm32f7/stm32f72xx73xx_irq.h index 4c82d5804a2..c8746d55b6c 100644 --- a/arch/arm/include/stm32f7/stm32f72xx73xx_irq.h +++ b/arch/arm/include/stm32f7/stm32f72xx73xx_irq.h @@ -148,7 +148,7 @@ #define STM32_IRQ_SAI2 (STM32_IRQ_FIRST + 91) /* 91: SAI2 global interrupt */ #define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 92) /* 92: QuadSPI global interrupt */ -#define STM32_IRQ_LPTIMER1 (STM32_IRQ_FIRST + 93) /* 93: LP Timer1 global interrupt */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 93) /* 93: LP Timer1 global interrupt */ #define STM32_IRQ_SDMMC2 (STM32_IRQ_FIRST + 103) /* 103: SDMMC2 global interrupt */ diff --git a/arch/arm/include/stm32f7/stm32f74xx75xx_irq.h b/arch/arm/include/stm32f7/stm32f74xx75xx_irq.h index dd6ee2cdfe7..a0cc88552fd 100644 --- a/arch/arm/include/stm32f7/stm32f74xx75xx_irq.h +++ b/arch/arm/include/stm32f7/stm32f74xx75xx_irq.h @@ -150,7 +150,7 @@ #define STM32_IRQ_DMA2D (STM32_IRQ_FIRST + 90) /* 90: DMA2D global interrupt */ #define STM32_IRQ_SAI2 (STM32_IRQ_FIRST + 91) /* 91: SAI2 global interrupt */ #define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 92) /* 92: QuadSPI global interrupt */ -#define STM32_IRQ_LPTIMER1 (STM32_IRQ_FIRST + 93) /* 93: LP Timer1 global interrupt */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 93) /* 93: LP Timer1 global interrupt */ #define STM32_IRQ_HDMICEC (STM32_IRQ_FIRST + 94) /* 94: HDMI-CEC global interrupt */ #define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST + 95) /* 95: I2C4 event interrupt */ #define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST + 96) /* 96: I2C4 Error interrupt */ diff --git a/arch/arm/include/stm32f7/stm32f76xx77xx_irq.h b/arch/arm/include/stm32f7/stm32f76xx77xx_irq.h index cd806f93524..3b40e1821d9 100644 --- a/arch/arm/include/stm32f7/stm32f76xx77xx_irq.h +++ b/arch/arm/include/stm32f7/stm32f76xx77xx_irq.h @@ -150,7 +150,7 @@ #define STM32_IRQ_DMA2D (STM32_IRQ_FIRST + 90) /* 90: DMA2D global interrupt */ #define STM32_IRQ_SAI2 (STM32_IRQ_FIRST + 91) /* 91: SAI2 global interrupt */ #define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 92) /* 92: QuadSPI global interrupt */ -#define STM32_IRQ_LPTIMER1 (STM32_IRQ_FIRST + 93) /* 93: LP Timer1 global interrupt */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 93) /* 93: LP Timer1 global interrupt */ #define STM32_IRQ_HDMICEC (STM32_IRQ_FIRST + 94) /* 94: HDMI-CEC global interrupt */ #define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST + 95) /* 95: I2C4 event interrupt */ #define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST + 96) /* 96: I2C4 Error interrupt */ diff --git a/arch/arm/src/common/stm32/CMakeLists.txt b/arch/arm/src/common/stm32/CMakeLists.txt index a725940137f..caa856c1ac4 100644 --- a/arch/arm/src/common/stm32/CMakeLists.txt +++ b/arch/arm/src/common/stm32/CMakeLists.txt @@ -97,8 +97,7 @@ if(CONFIG_STM32_TIM) list(APPEND SRCS stm32_tim.c) endif() -if(CONFIG_STM32_LPTIM AND (CONFIG_STM32_HAVE_IP_LPTIM_V1 OR - CONFIG_STM32_HAVE_IP_LPTIM_V2)) +if(CONFIG_STM32_LPTIM) list(APPEND SRCS stm32_lptim.c) endif() diff --git a/arch/arm/src/common/stm32/Kconfig.periph b/arch/arm/src/common/stm32/Kconfig.periph index 78e116be183..c23bf08fa95 100644 --- a/arch/arm/src/common/stm32/Kconfig.periph +++ b/arch/arm/src/common/stm32/Kconfig.periph @@ -748,7 +748,7 @@ config STM32_UART8 config STM32_LPTIM1 bool "LPTIM1" depends on STM32_HAVE_LPTIM1 - select STM32_LPTIM if ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB || ARCH_CHIP_STM32H5 + select STM32_LPTIM config STM32_TIM1 bool "TIM1" @@ -838,17 +838,17 @@ config STM32_TIM17 config STM32_LPTIM2 bool "LPTIM2" depends on ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32L4 && STM32_HAVE_LPTIM2 - select STM32_LPTIM if ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB || ARCH_CHIP_STM32H5 + select STM32_LPTIM config STM32_LPTIM3 bool "LPTIM3" depends on STM32_HAVE_LPTIM3 - select STM32_LPTIM if ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32H5 + select STM32_LPTIM config STM32_LPTIM4 bool "LPTIM4" depends on STM32_HAVE_LPTIM4 - select STM32_LPTIM if ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32H5 + select STM32_LPTIM config STM32_LPTIM5 bool "LPTIM5" diff --git a/arch/arm/src/common/stm32/Make.defs b/arch/arm/src/common/stm32/Make.defs index 6c6afc4fc98..e3c1821ddc8 100644 --- a/arch/arm/src/common/stm32/Make.defs +++ b/arch/arm/src/common/stm32/Make.defs @@ -108,10 +108,8 @@ ifeq ($(CONFIG_STM32_TIM),y) CHIP_CSRCS += stm32_tim.c endif ifeq ($(CONFIG_STM32_LPTIM),y) -ifneq ($(CONFIG_STM32_HAVE_IP_LPTIM_V1)$(CONFIG_STM32_HAVE_IP_LPTIM_V2),) CHIP_CSRCS += stm32_lptim.c endif -endif ifeq ($(CONFIG_STM32_FREERUN),y) CHIP_CSRCS += stm32_freerun.c endif diff --git a/arch/arm/src/common/stm32/hardware/stm32_lptim.h b/arch/arm/src/common/stm32/hardware/stm32_lptim.h index d5150364d29..f176b1ec002 100644 --- a/arch/arm/src/common/stm32/hardware/stm32_lptim.h +++ b/arch/arm/src/common/stm32/hardware/stm32_lptim.h @@ -28,65 +28,50 @@ ****************************************************************************/ #include <nuttx/config.h> + #include "chip.h" +#if (defined(CONFIG_STM32_HAVE_IP_LPTIM_V1) + \ + defined(CONFIG_STM32_HAVE_IP_LPTIM_V2)) != 1 +# error Exactly one STM32 LPTIM IP version must be selected +#endif + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ +/* LPTIM IP versions (from the reference SVD files): + * + * V1 - IER and CMP, optional OR, CFGR2 and RCR + * (F4, F7, G0, G4, H7, L0, L4, L5, WB, WL5) + * V2 - DIER, capture/compare channels, CFGR2 and RCR + * (C5, H5, H7RS, N6, U0, U3, U5) + */ + /* Register Offsets *********************************************************/ -#define STM32_LPTIM_ISR_OFFSET 0x0000 /* Interrupt and status register */ -#define STM32_LPTIM_ICR_OFFSET 0x0004 /* Interrupt clear register */ -#define STM32_LPTIM_IER_OFFSET 0x0008 /* Interrupt enable register */ -#define STM32_LPTIM_CFGR_OFFSET 0x000C /* Configuration register */ -#define STM32_LPTIM_CR_OFFSET 0x0010 /* Control register */ -#define STM32_LPTIM_CMP_OFFSET 0x0014 /* Compare register */ -#define STM32_LPTIM_ARR_OFFSET 0x0018 /* Autoreloar register */ -#define STM32_LPTIM_CNT_OFFSET 0x001C /* Counter register */ -#define STM32_LPTIM_CFGR2_OFFSET 0x0024 /* Configuration register 2 */ - -/* Register Addresses *******************************************************/ - -# define STM32_LPTIM1_ISR (STM32_LPTIM1_BASE+STM32_LPTIM_ISR_OFFSET) -# define STM32_LPTIM1_ICR (STM32_LPTIM1_BASE+STM32_LPTIM_ICR_OFFSET) -# define STM32_LPTIM1_IER (STM32_LPTIM1_BASE+STM32_LPTIM_IER_OFFSET) -# define STM32_LPTIM1_CFGR (STM32_LPTIM1_BASE+STM32_LPTIM_CFGR_OFFSET) -# define STM32_LPTIM1_CR (STM32_LPTIM1_BASE+STM32_LPTIM_CR_OFFSET) -# define STM32_LPTIM1_CMP (STM32_LPTIM1_BASE+STM32_LPTIM_CMP_OFFSET) -# define STM32_LPTIM1_ARR (STM32_LPTIM1_BASE+STM32_LPTIM_ARR_OFFSET) -# define STM32_LPTIM1_CNT (STM32_LPTIM1_BASE+STM32_LPTIM_CNT_OFFSET) -# define STM32_LPTIM1_CFGR2 (STM32_LPTIM1_BASE+STM32_LPTIM_CFGR2_OFFSET) - -# define STM32_LPTIM3_ISR (STM32_LPTIM3_BASE+STM32_LPTIM_ISR_OFFSET) -# define STM32_LPTIM3_ICR (STM32_LPTIM3_BASE+STM32_LPTIM_ICR_OFFSET) -# define STM32_LPTIM3_IER (STM32_LPTIM3_BASE+STM32_LPTIM_IER_OFFSET) -# define STM32_LPTIM3_CFGR (STM32_LPTIM3_BASE+STM32_LPTIM_CFGR_OFFSET) -# define STM32_LPTIM3_CR (STM32_LPTIM3_BASE+STM32_LPTIM_CR_OFFSET) -# define STM32_LPTIM3_CMP (STM32_LPTIM3_BASE+STM32_LPTIM_CMP_OFFSET) -# define STM32_LPTIM3_ARR (STM32_LPTIM3_BASE+STM32_LPTIM_ARR_OFFSET) -# define STM32_LPTIM3_CNT (STM32_LPTIM3_BASE+STM32_LPTIM_CNT_OFFSET) -# define STM32_LPTIM3_CFGR2 (STM32_LPTIM3_BASE+STM32_LPTIM_CFGR2_OFFSET) - -# define STM32_LPTIM4_ISR (STM32_LPTIM4_BASE+STM32_LPTIM_ISR_OFFSET) -# define STM32_LPTIM4_ICR (STM32_LPTIM4_BASE+STM32_LPTIM_ICR_OFFSET) -# define STM32_LPTIM4_IER (STM32_LPTIM4_BASE+STM32_LPTIM_IER_OFFSET) -# define STM32_LPTIM4_CFGR (STM32_LPTIM4_BASE+STM32_LPTIM_CFGR_OFFSET) -# define STM32_LPTIM4_CR (STM32_LPTIM4_BASE+STM32_LPTIM_CR_OFFSET) -# define STM32_LPTIM4_CMP (STM32_LPTIM4_BASE+STM32_LPTIM_CMP_OFFSET) -# define STM32_LPTIM4_ARR (STM32_LPTIM4_BASE+STM32_LPTIM_ARR_OFFSET) -# define STM32_LPTIM4_CNT (STM32_LPTIM4_BASE+STM32_LPTIM_CNT_OFFSET) -# define STM32_LPTIM4_CFGR2 (STM32_LPTIM4_BASE+STM32_LPTIM_CFGR2_OFFSET) - -# define STM32_LPTIM5_ISR (STM32_LPTIM5_BASE+STM32_LPTIM_ISR_OFFSET) -# define STM32_LPTIM5_ICR (STM32_LPTIM5_BASE+STM32_LPTIM_ICR_OFFSET) -# define STM32_LPTIM5_IER (STM32_LPTIM5_BASE+STM32_LPTIM_IER_OFFSET) -# define STM32_LPTIM5_CFGR (STM32_LPTIM5_BASE+STM32_LPTIM_CFGR_OFFSET) -# define STM32_LPTIM5_CR (STM32_LPTIM5_BASE+STM32_LPTIM_CR_OFFSET) -# define STM32_LPTIM5_CMP (STM32_LPTIM5_BASE+STM32_LPTIM_CMP_OFFSET) -# define STM32_LPTIM5_ARR (STM32_LPTIM5_BASE+STM32_LPTIM_ARR_OFFSET) -# define STM32_LPTIM5_CNT (STM32_LPTIM5_BASE+STM32_LPTIM_CNT_OFFSET) -# define STM32_LPTIM5_CFGR2 (STM32_LPTIM5_BASE+STM32_LPTIM_CFGR2_OFFSET) +#define STM32_LPTIM_ISR_OFFSET 0x0000 /* Interrupt and status */ +#define STM32_LPTIM_ICR_OFFSET 0x0004 /* Interrupt clear */ +#define STM32_LPTIM_IER_OFFSET 0x0008 /* Interrupt enable */ +#define STM32_LPTIM_CFGR_OFFSET 0x000c /* Configuration */ +#define STM32_LPTIM_CR_OFFSET 0x0010 /* Control */ +#define STM32_LPTIM_CMP_OFFSET 0x0014 /* Compare */ +#define STM32_LPTIM_ARR_OFFSET 0x0018 /* Autoreload */ +#define STM32_LPTIM_CNT_OFFSET 0x001c /* Counter */ +#ifdef CONFIG_STM32_HAVE_IP_LPTIM_V1 +# define STM32_LPTIM_OR_OFFSET 0x0020 /* Option */ +#endif +#define STM32_LPTIM_CFGR2_OFFSET 0x0024 /* Configuration 2 */ +#define STM32_LPTIM_RCR_OFFSET 0x0028 /* Repetition */ +#ifdef CONFIG_STM32_HAVE_IP_LPTIM_V2 +# define STM32_LPTIM_DIER_OFFSET 0x0008 /* Interrupt enable */ +# define STM32_LPTIM_CCR1_OFFSET 0x0014 /* Capture/compare 1 */ +# define STM32_LPTIM_CCMR1_OFFSET 0x002c /* Capture/compare mode 1 */ +# define STM32_LPTIM_CCMR2_OFFSET 0x0030 /* Capture/compare mode 2 */ +# define STM32_LPTIM_CCR2_OFFSET 0x0034 /* Capture/compare 2 */ +# define STM32_LPTIM_CCR3_OFFSET 0x0038 /* Capture/compare 3 */ +# define STM32_LPTIM_CCR4_OFFSET 0x003c /* Capture/compare 4 */ +#endif /* Register Bitfield Definitions ********************************************/ @@ -94,35 +79,45 @@ #define LPTIM_ISR_CMPM (1 << 0) /* Bit 0: Compare match */ #define LPTIM_ISR_ARRM (1 << 1) /* Bit 1: Autoreload match */ -#define LPTIM_ISR_EXTTRIG (1 << 2) /* Bit 2: External trigger edge event */ -#define LPTIM_ISR_CMPOK (1 << 3) /* Bit 3: Compare register update OK */ -#define LPTIM_ISR_ARROK (1 << 4) /* Bit 4: Autoreload register update OK */ -#define LPTIM_ISR_UP (1 << 5) /* Bit 5: Counter direction change down to up */ -#define LPTIM_ISR_DOWN (1 << 6) /* Bit 6: Counter direction change up to down */ +#define LPTIM_ISR_EXTTRIG (1 << 2) /* Bit 2: External trigger */ +#define LPTIM_ISR_CMPOK (1 << 3) /* Bit 3: CMP update OK */ +#define LPTIM_ISR_ARROK (1 << 4) /* Bit 4: ARR update OK */ +#define LPTIM_ISR_UP (1 << 5) /* Bit 5: Down to up change */ +#define LPTIM_ISR_DOWN (1 << 6) /* Bit 6: Up to down change */ +#define LPTIM_ISR_UE (1 << 7) /* Bit 7: Update event */ +#define LPTIM_ISR_REPOK (1 << 8) /* Bit 8: RCR update OK */ +#ifdef CONFIG_STM32_HAVE_IP_LPTIM_V2 +# define LPTIM_ISR_CC2IF (1 << 9) /* Bit 9: Capture/compare 2 */ +# define LPTIM_ISR_CC3IF (1 << 10) /* Bit 10: Capture/compare 3 */ +# define LPTIM_ISR_CC4IF (1 << 11) /* Bit 11: Capture/compare 4 */ +# define LPTIM_ISR_CC1OF (1 << 12) /* Bit 12: CC1 overcapture */ +# define LPTIM_ISR_CC2OF (1 << 13) /* Bit 13: CC2 overcapture */ +# define LPTIM_ISR_CC3OF (1 << 14) /* Bit 14: CC3 overcapture */ +# define LPTIM_ISR_CC4OF (1 << 15) /* Bit 15: CC4 overcapture */ +# define LPTIM_ISR_CMP2OK (1 << 19) /* Bit 19: CCR2 update OK */ +# define LPTIM_ISR_CMP3OK (1 << 20) /* Bit 20: CCR3 update OK */ +# define LPTIM_ISR_CMP4OK (1 << 21) /* Bit 21: CCR4 update OK */ +# define LPTIM_ISR_DIEROK (1 << 24) /* Bit 24: DIER update OK */ + +# define LPTIM_IER_CC1DE (1 << 16) /* Bit 16: CC1 DMA request */ +# define LPTIM_IER_UEDE (1 << 23) /* Bit 23: Update DMA request */ +# define LPTIM_IER_CC2DE (1 << 25) /* Bit 25: CC2 DMA request */ +# define LPTIM_IER_CC3DE (1 << 26) /* Bit 26: CC3 DMA request */ +# define LPTIM_IER_CC4DE (1 << 27) /* Bit 27: CC4 DMA request */ +#endif /* Configuration register */ #define LPTIM_CFGR_CKSEL (1 << 0) /* Bit 0: Clock selector */ #define LPTIM_CFGR_CKPOL_SHIFT (1) /* Bits 1-2: Clock polarity */ #define LPTIM_CFGR_CKPOL_MASK (3 << LPTIM_CFGR_CKPOL_SHIFT) -# define LPTIM_CFGR_CKPOL_RISE (0 << LPTIM_CFGR_CKPOL_SHIFT) /* 00: Rising edge */ -# define LPTIM_CFGR_CKPOL_FALL (1 << LPTIM_CFGR_CKPOL_SHIFT) /* 01: Falling edge */ -# define LPTIM_CFGR_CKPOL_BOTH (2 << LPTIM_CFGR_CKPOL_SHIFT) /* 10: Both edges */ - -#define LPTIM_CFGR_CKFLT_SHIFT (3) /* Bits 3-4: Digital filter for clock*/ +# define LPTIM_CFGR_CKPOL_RISING (0 << LPTIM_CFGR_CKPOL_SHIFT) +# define LPTIM_CFGR_CKPOL_FALLING (1 << LPTIM_CFGR_CKPOL_SHIFT) +# define LPTIM_CFGR_CKPOL_BOTH (2 << LPTIM_CFGR_CKPOL_SHIFT) +#define LPTIM_CFGR_CKFLT_SHIFT (3) /* Bits 3-4: Clock filter */ #define LPTIM_CFGR_CKFLT_MASK (3 << LPTIM_CFGR_CKFLT_SHIFT) -# define LPTIM_CFGR_CKFLT_ANY (0 << LPTIM_CFGR_CKFLT_SHIFT) /* 00: Any */ -# define LPTIM_CFGR_CKFLT_2 (1 << LPTIM_CFGR_CKFLT_SHIFT) /* 01: 2 clocks */ -# define LPTIM_CFGR_CKFLT_4 (2 << LPTIM_CFGR_CKFLT_SHIFT) /* 10: 4 clocks */ -# define LPTIM_CFGR_CKFLT_8 (3 << LPTIM_CFGR_CKFLT_SHIFT) /* 11: 8 clocks */ - -#define LPTIM_CFGR_TRGFLT_SHIFT (6) /* Bits 6-7: digital filter for trigger */ +#define LPTIM_CFGR_TRGFLT_SHIFT (6) /* Bits 6-7: Trigger filter */ #define LPTIM_CFGR_TRGFLT_MASK (3 << LPTIM_CFGR_TRGFLT_SHIFT) -# define LPTIM_CFGR_TRGFLT_ANY (0 << LPTIM_CFGR_TRGFLT_SHIFT) /* 00: Any */ -# define LPTIM_CFGR_TRGFLT_2 (1 << LPTIM_CFGR_TRGFLT_SHIFT) /* 01: 2 clocks */ -# define LPTIM_CFGR_TRGFLT_4 (2 << LPTIM_CFGR_TRGFLT_SHIFT) /* 10: 4 clocks */ -# define LPTIM_CFGR_TRGFLT_8 (3 << LPTIM_CFGR_TRGFLT_SHIFT) /* 11: 8 clocks */ - #define LPTIM_CFGR_PRESC_SHIFT (9) /* Bits 9-11: Clock prescaler */ #define LPTIM_CFGR_PRESC_MASK (7 << LPTIM_CFGR_PRESC_SHIFT) # define LPTIM_CFGR_PRESC_1 (0 << LPTIM_CFGR_PRESC_SHIFT) @@ -133,36 +128,86 @@ # define LPTIM_CFGR_PRESC_32 (5 << LPTIM_CFGR_PRESC_SHIFT) # define LPTIM_CFGR_PRESC_64 (6 << LPTIM_CFGR_PRESC_SHIFT) # define LPTIM_CFGR_PRESC_128 (7 << LPTIM_CFGR_PRESC_SHIFT) - -#define LPTIM_CFGR_TRIGSEL_SHIFT (13) /* Bits 13-15: Trigger selector */ +#define LPTIM_CFGR_TRIGSEL_SHIFT (13) /* Bits 13-15: Trigger select */ #define LPTIM_CFGR_TRIGSEL_MASK (7 << LPTIM_CFGR_TRIGSEL_SHIFT) -#define LPTIM_CFGR_TRIGEN_SHIFT (17) /* Bits 17-18: Trigger enable and polarity */ +#ifdef CONFIG_ARCH_CHIP_STM32G4 +# define LPTIM_CFGR_TRIGSEL_3 (1 << 29) /* Bit 29: TRIGSEL bit 3 */ +#endif +#define LPTIM_CFGR_TRIGEN_SHIFT (17) /* Bits 17-18: Trigger enable */ #define LPTIM_CFGR_TRIGEN_MASK (3 << LPTIM_CFGR_TRIGEN_SHIFT) -# define LPTIM_CFGR_TRIGEN_SW (0 << LPTIM_CFGR_TRIGEN_SHIFT) /* 00: software */ -# define LPTIM_CFGR_TRIGEN_RISE (1 << LPTIM_CFGR_TRIGEN_SHIFT) /* 01: rising edge */ -# define LPTIM_CFGR_TRIGEN_FALL (2 << LPTIM_CFGR_TRIGEN_SHIFT) /* 10: falling edge */ -# define LPTIM_CFGR_TRIGEN_BOTH (3 << LPTIM_CFGR_TRIGEN_SHIFT) /* 11: both edges */ - -#define LPTIM_CFGR_TIMEOUT (1 << 19) /* Bit 19: Timeout enable */ +# define LPTIM_CFGR_TRIGEN_SW (0 << LPTIM_CFGR_TRIGEN_SHIFT) +# define LPTIM_CFGR_TRIGEN_RISING (1 << LPTIM_CFGR_TRIGEN_SHIFT) +# define LPTIM_CFGR_TRIGEN_FALLING (2 << LPTIM_CFGR_TRIGEN_SHIFT) +# define LPTIM_CFGR_TRIGEN_BOTH (3 << LPTIM_CFGR_TRIGEN_SHIFT) +#define LPTIM_CFGR_TIMOUT (1 << 19) /* Bit 19: Timeout enable */ #define LPTIM_CFGR_WAVE (1 << 20) /* Bit 20: Waveform shape */ -#define LPTIM_CFGR_WAVPOL (1 << 21) /* Bit 21: Waveform shape polarity */ -#define LPTIM_CFGR_PRELOAD (1 << 22) /* Bit 22: Registers update mode */ -#define LPTIM_CFGR_COUNTMODE (1 << 23) /* Bit 23: Counter mode enable */ -#define LPTIM_CFGR_ENC (1 << 24) /* Bit 24: Encoder mode enable */ +#define LPTIM_CFGR_WAVPOL (1 << 21) /* Bit 21: Waveform polarity */ +#define LPTIM_CFGR_PRELOAD (1 << 22) /* Bit 22: Preload */ +#define LPTIM_CFGR_COUNTMODE (1 << 23) /* Bit 23: Count mode */ +#define LPTIM_CFGR_ENC (1 << 24) /* Bit 24: Encoder mode */ /* Control register */ -#define LPTIM_CR_ENABLE (1 << 0) /* Bit 0: Enable */ -#define LPTIM_CR_SNGSTRT (1 << 1) /* Bit 1: Start in single mode */ -#define LPTIM_CR_CNTSTRT (1 << 2) /* Bit 2: Start in continuous mode */ +#define LPTIM_CR_ENABLE (1 << 0) /* Bit 0: LPTIM enable */ +#define LPTIM_CR_SNGSTRT (1 << 1) /* Bit 1: Single start */ +#define LPTIM_CR_CNTSTRT (1 << 2) /* Bit 2: Continuous start */ #define LPTIM_CR_COUNTRST (1 << 3) /* Bit 3: Counter reset */ -#define LPTIM_CR_RSTARE (1 << 4) /* Reset after read enable */ +#define LPTIM_CR_RSTARE (1 << 4) /* Bit 4: Reset after read */ /* Configuration register 2 */ -#define LPTIM_CFGR2_IN1SEL_SHIFT (0) /* Input 1 selection */ +#define LPTIM_CFGR2_IN1SEL_SHIFT (0) /* Bits 0-1: Input 1 select */ #define LPTIM_CFGR2_IN1SEL_MASK (3 << LPTIM_CFGR2_IN1SEL_SHIFT) -#define LPTIM_CFGR2_IN2SEL_SHIFT (4) /* Input 2 selection */ +#define LPTIM_CFGR2_IN2SEL_SHIFT (4) /* Bits 4-5: Input 2 select */ #define LPTIM_CFGR2_IN2SEL_MASK (3 << LPTIM_CFGR2_IN2SEL_SHIFT) +#ifdef CONFIG_STM32_HAVE_IP_LPTIM_V2 +# define LPTIM_CFGR2_IC1SEL_SHIFT (16) /* Bits 16-17: IC1 selection */ +# define LPTIM_CFGR2_IC1SEL_MASK (3 << LPTIM_CFGR2_IC1SEL_SHIFT) +# define LPTIM_CFGR2_IC2SEL_SHIFT (20) /* Bits 20-21: IC2 selection */ +# define LPTIM_CFGR2_IC2SEL_MASK (3 << LPTIM_CFGR2_IC2SEL_SHIFT) +#endif + +/* Repetition register */ + +#define LPTIM_RCR_REP_SHIFT (0) /* Bits 0-7: Repetition value */ +#define LPTIM_RCR_REP_MASK (0xff << LPTIM_RCR_REP_SHIFT) + +#ifdef CONFIG_STM32_HAVE_IP_LPTIM_V2 +/* Capture/compare mode registers 1 and 2 (channel n: 1/3 low, 2/4 high) */ + +# define LPTIM_CCMR1_CC1SEL (1 << 0) /* Bit 0: CC1 selection */ +# define LPTIM_CCMR1_CC1E (1 << 1) /* Bit 1: CC1 output enable */ +# define LPTIM_CCMR1_CC1P_SHIFT (2) /* Bits 2-3: CC1 polarity */ +# define LPTIM_CCMR1_CC1P_MASK (3 << LPTIM_CCMR1_CC1P_SHIFT) +# define LPTIM_CCMR1_IC1PSC_SHIFT (8) /* Bits 8-9: IC1 prescaler */ +# define LPTIM_CCMR1_IC1PSC_MASK (3 << LPTIM_CCMR1_IC1PSC_SHIFT) +# define LPTIM_CCMR1_IC1F_SHIFT (12) /* Bits 12-13: IC1 filter */ +# define LPTIM_CCMR1_IC1F_MASK (3 << LPTIM_CCMR1_IC1F_SHIFT) +# define LPTIM_CCMR1_CC2SEL (1 << 16) /* Bit 16: CC2 selection */ +# define LPTIM_CCMR1_CC2E (1 << 17) /* Bit 17: CC2 output enable */ +# define LPTIM_CCMR1_CC2P_SHIFT (18) /* Bits 18-19: CC2 polarity */ +# define LPTIM_CCMR1_CC2P_MASK (3 << LPTIM_CCMR1_CC2P_SHIFT) +# define LPTIM_CCMR1_IC2PSC_SHIFT (24) /* Bits 24-25: IC2 prescaler */ +# define LPTIM_CCMR1_IC2PSC_MASK (3 << LPTIM_CCMR1_IC2PSC_SHIFT) +# define LPTIM_CCMR1_IC2F_SHIFT (28) /* Bits 28-29: IC2 filter */ +# define LPTIM_CCMR1_IC2F_MASK (3 << LPTIM_CCMR1_IC2F_SHIFT) + +# define LPTIM_CCMR2_CC3SEL (1 << 0) /* Bit 0: CC3 selection */ +# define LPTIM_CCMR2_CC3E (1 << 1) /* Bit 1: CC3 output enable */ +# define LPTIM_CCMR2_CC3P_SHIFT (2) /* Bits 2-3: CC3 polarity */ +# define LPTIM_CCMR2_CC3P_MASK (3 << LPTIM_CCMR2_CC3P_SHIFT) +# define LPTIM_CCMR2_IC3PSC_SHIFT (8) /* Bits 8-9: IC3 prescaler */ +# define LPTIM_CCMR2_IC3PSC_MASK (3 << LPTIM_CCMR2_IC3PSC_SHIFT) +# define LPTIM_CCMR2_IC3F_SHIFT (12) /* Bits 12-13: IC3 filter */ +# define LPTIM_CCMR2_IC3F_MASK (3 << LPTIM_CCMR2_IC3F_SHIFT) +# define LPTIM_CCMR2_CC4SEL (1 << 16) /* Bit 16: CC4 selection */ +# define LPTIM_CCMR2_CC4E (1 << 17) /* Bit 17: CC4 output enable */ +# define LPTIM_CCMR2_CC4P_SHIFT (18) /* Bits 18-19: CC4 polarity */ +# define LPTIM_CCMR2_CC4P_MASK (3 << LPTIM_CCMR2_CC4P_SHIFT) +# define LPTIM_CCMR2_IC4PSC_SHIFT (24) /* Bits 24-25: IC4 prescaler */ +# define LPTIM_CCMR2_IC4PSC_MASK (3 << LPTIM_CCMR2_IC4PSC_SHIFT) +# define LPTIM_CCMR2_IC4F_SHIFT (28) /* Bits 28-29: IC4 filter */ +# define LPTIM_CCMR2_IC4F_MASK (3 << LPTIM_CCMR2_IC4F_SHIFT) +#endif #endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_LPTIM_H */ diff --git a/arch/arm/src/stm32c5/Kconfig b/arch/arm/src/stm32c5/Kconfig index b25f3eb3b83..8695ba37ca2 100644 --- a/arch/arm/src/stm32c5/Kconfig +++ b/arch/arm/src/stm32c5/Kconfig @@ -18,6 +18,7 @@ config STM32_C5_PERIPHERALS select STM32_HAVE_IP_GPIO_M33_V1 select STM32_HAVE_IP_TIMERS_V3 select STM32_HAVE_IP_DBGMCU_V5 + select STM32_HAVE_IP_LPTIM_V2 select STM32_HAVE_IP_WDG_V3 select STM32_HAVE_IP_USART_M33_V3 select STM32_HAVE_LPUART1 diff --git a/arch/arm/src/stm32f4/Kconfig b/arch/arm/src/stm32f4/Kconfig index 7c13a47b036..4b06a3123c8 100644 --- a/arch/arm/src/stm32f4/Kconfig +++ b/arch/arm/src/stm32f4/Kconfig @@ -260,6 +260,7 @@ config STM32_STM32F4XXX select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM select STM32_HAVE_IP_CRYPTO_M3M4_V1 select STM32_HAVE_IP_DBGMCU_V2 + select STM32_HAVE_IP_LPTIM_V1 select STM32_HAVE_IP_ADC_M3M4_V1 select STM32_HAVE_COMMON_FOC select STM32_HAVE_IP_DCMI_V1 diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig index 9f41738f660..ce1ab6b225b 100644 --- a/arch/arm/src/stm32f7/Kconfig +++ b/arch/arm/src/stm32f7/Kconfig @@ -49,8 +49,9 @@ config STM32_F7_PERIPHERALS select STM32_HAVE_USART6 select STM32_HAVE_FLASH_ART_ACCELERATOR select STM32_HAVE_IP_TIMERS_V2 - select STM32_HAVE_IP_WDG_V1 select STM32_HAVE_IP_DBGMCU_V2 + select STM32_HAVE_IP_LPTIM_V1 + select STM32_HAVE_IP_WDG_V1 choice prompt "STM32 F7 Chip Selection" diff --git a/arch/arm/src/stm32g0/Kconfig b/arch/arm/src/stm32g0/Kconfig index a28f238153d..e2cb2645946 100644 --- a/arch/arm/src/stm32g0/Kconfig +++ b/arch/arm/src/stm32g0/Kconfig @@ -225,6 +225,7 @@ config STM32_STM32G0 select STM32_HAVE_IP_COMP_M0_V1 if STM32_HAVE_COMP select STM32_HAVE_IP_DAC_M0_V1 if STM32_HAVE_DAC1 select STM32_HAVE_IP_DBGMCU_V3 + select STM32_HAVE_IP_LPTIM_V1 select STM32_HAVE_IP_DMA_V1 select STM32_HAVE_IP_DMA_V1_7CH_DMAMUX select STM32_HAVE_IP_EXTI_V2 diff --git a/arch/arm/src/stm32g4/Kconfig b/arch/arm/src/stm32g4/Kconfig index cc5db2dd027..c44a8bd331b 100644 --- a/arch/arm/src/stm32g4/Kconfig +++ b/arch/arm/src/stm32g4/Kconfig @@ -98,6 +98,7 @@ config STM32_STM32G4XXX select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM select STM32_HAVE_IP_CRYPTO_M3M4_V1 select STM32_HAVE_IP_DBGMCU_V4 + select STM32_HAVE_IP_LPTIM_V1 select STM32_HAVE_IP_ADC_M3M4_V2 select STM32_FOC_HAVE_ADC_CHAN0_WORKAROUND select STM32_HAVE_COMMON_FOC diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_memorymap.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_memorymap.h index 38a8ba2ef2f..e0c7878f790 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_memorymap.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5xxx_memorymap.h @@ -84,7 +84,7 @@ #define STM32_FDCAN_SRAM_BASE 0x4000ac00 #define STM32_FDCAN2_BASE 0x4000a800 #define STM32_FDCAN1_BASE 0x4000a400 -#define STM32_LPTIM2 0x40009400 +#define STM32_LPTIM2_BASE 0x40009400 #define STM32_DTS_BASE 0x40008c00 #define STM32_UART12_BASE 0x40008400 #define STM32_UART9_BASE 0x40008000 diff --git a/arch/arm/src/stm32l0/Kconfig b/arch/arm/src/stm32l0/Kconfig index fa5a5a71686..b15708f6064 100644 --- a/arch/arm/src/stm32l0/Kconfig +++ b/arch/arm/src/stm32l0/Kconfig @@ -219,6 +219,7 @@ config STM32_STM32L0 select STM32_HAVE_IP_COMP_M0_V1 if STM32_HAVE_COMP select STM32_HAVE_IP_DAC_M0_V1 if STM32_HAVE_DAC1 select STM32_HAVE_IP_DBGMCU_V3 + select STM32_HAVE_IP_LPTIM_V1 select STM32_HAVE_IP_DMA_V1 select STM32_HAVE_IP_DMA_V1_7CH select STM32_HAVE_IP_EXTI_V1 diff --git a/arch/arm/src/stm32l4/CMakeLists.txt b/arch/arm/src/stm32l4/CMakeLists.txt index 819a8d8f48d..cf52b56be03 100644 --- a/arch/arm/src/stm32l4/CMakeLists.txt +++ b/arch/arm/src/stm32l4/CMakeLists.txt @@ -134,10 +134,6 @@ if(CONFIG_STM32_SAI) list(APPEND SRCS stm32l4_sai.c) endif() -if(CONFIG_STM32_LPTIM) - list(APPEND SRCS stm32l4_lptim.c) -endif() - if(CONFIG_STM32_PWM) list(APPEND SRCS stm32l4_pwm.c) endif() diff --git a/arch/arm/src/stm32l4/Kconfig b/arch/arm/src/stm32l4/Kconfig index c9bba70b782..b74762ab538 100644 --- a/arch/arm/src/stm32l4/Kconfig +++ b/arch/arm/src/stm32l4/Kconfig @@ -13,6 +13,7 @@ config STM32_L4_PERIPHERALS select STM32_HAVE_IP_DBGMCU_V4 select STM32_HAVE_FLASH_ICACHE select STM32_HAVE_FLASH_DCACHE + select STM32_HAVE_IP_LPTIM_V1 select STM32_HAVE_DAC1 select STM32_HAVE_DMA1 select STM32_HAVE_DMA2 diff --git a/arch/arm/src/stm32l4/Make.defs b/arch/arm/src/stm32l4/Make.defs index 8dd3a34c2e1..b5fe54cc18e 100644 --- a/arch/arm/src/stm32l4/Make.defs +++ b/arch/arm/src/stm32l4/Make.defs @@ -132,10 +132,6 @@ ifeq ($(CONFIG_STM32_SAI),y) CHIP_CSRCS += stm32l4_sai.c endif -ifeq ($(CONFIG_STM32_LPTIM),y) -CHIP_CSRCS += stm32l4_lptim.c -endif - ifeq ($(CONFIG_STM32_PWM),y) CHIP_CSRCS += stm32l4_pwm.c endif diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_lptim.h b/arch/arm/src/stm32l4/hardware/stm32l4_lptim.h deleted file mode 100644 index 0a9c98ab0ba..00000000000 --- a/arch/arm/src/stm32l4/hardware/stm32l4_lptim.h +++ /dev/null @@ -1,137 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/hardware/stm32l4_lptim.h - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2017 Gregory Nutt. All rights reserved. - * SPDX-FileCopyrightText: 2016 Motorola Mobility LLC. All rights reserved. - * SPDX-FileCopyrightText: 2009, 2011-2012 Gregory Nutt. All rights reserved. - * SPDX-FileContributor: Gregory Nutt <[email protected]> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_LPTIM_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_LPTIM_H - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -/* Basic Timers - TIM6 and TIM7 */ - -#define STM32_LPTIM_ISR_OFFSET 0x0000 /* Interrupt and Status Register */ -#define STM32_LPTIM_ICR_OFFSET 0x0004 /* Interrupt Clear Register */ -#define STM32_LPTIM_IER_OFFSET 0x0008 /* Interrupt Enable Register */ -#define STM32_LPTIM_CFGR_OFFSET 0x000c /* Configuration Register */ -#define STM32_LPTIM_CR_OFFSET 0x0010 /* Control Register */ -#define STM32_LPTIM_CMP_OFFSET 0x0014 /* Compare Register */ -#define STM32_LPTIM_ARR_OFFSET 0x0018 /* Autoreload Register */ -#define STM32_LPTIM_CNT_OFFSET 0x001c /* Counter Register */ - -/* Register Addresses *******************************************************/ - -/* Low-Power Timers - LPTIM1 and LPTIM2 */ - -#define STM32_LPTIM1_ISR (STM32_LPTIM1_BASE+STM32_LPTIM_ISR_OFFSET) -#define STM32_LPTIM1_ICR (STM32_LPTIM1_BASE+STM32_LPTIM_ICR_OFFSET) -#define STM32_LPTIM1_IER (STM32_LPTIM1_BASE+STM32_LPTIM_IER_OFFSET) -#define STM32_LPTIM1_CFGR (STM32_LPTIM1_BASE+STM32_LPTIM_CFGR_OFFSET) -#define STM32_LPTIM1_CR (STM32_LPTIM1_BASE+STM32_LPTIM_CR_OFFSET) -#define STM32_LPTIM1_CMP (STM32_LPTIM1_BASE+STM32_LPTIM_CMP_OFFSET) -#define STM32_LPTIM1_ARR (STM32_LPTIM1_BASE+STM32_LPTIM_ARR_OFFSET) -#define STM32_LPTIM1_CNT (STM32_LPTIM1_BASE+STM32_LPTIM_CNT_OFFSET) - -#define STM32_LPTIM2_ISR (STM32_LPTIM2_BASE+STM32_LPTIM_ISR_OFFSET) -#define STM32_LPTIM2_ICR (STM32_LPTIM2_BASE+STM32_LPTIM_ICR_OFFSET) -#define STM32_LPTIM2_IER (STM32_LPTIM2_BASE+STM32_LPTIM_IER_OFFSET) -#define STM32_LPTIM2_CFGR (STM32_LPTIM2_BASE+STM32_LPTIM_CFGR_OFFSET) -#define STM32_LPTIM2_CR (STM32_LPTIM2_BASE+STM32_LPTIM_CR_OFFSET) -#define STM32_LPTIM2_CMP (STM32_LPTIM2_BASE+STM32_LPTIM_CMP_OFFSET) -#define STM32_LPTIM2_ARR (STM32_LPTIM2_BASE+STM32_LPTIM_ARR_OFFSET) -#define STM32_LPTIM2_CNT (STM32_LPTIM2_BASE+STM32_LPTIM_CNT_OFFSET) - -/* Register Bitfield Definitions ********************************************/ - -#define LPTIM_CFGR_CKSEL (1 << 0) /* Bit 0: Clock selector */ -#define LPTIM_CFGR_CKSEL_SHIFT (0) -#define LPTIM_CFGR_CKSEL_MASK (1) -# define LPTIM_CFGR_CKSEL_INTCLK (0) /* 0: Internal clock */ -# define LPTIM_CFGR_CKSEL_EXTCLK (1) /* 1: External clock */ - -#define LPTIM_CFGR_CKPOL_SHIFT (1) /* Bits 2-1: Clock Polarity */ -#define LPTIM_CFGR_CKPOL_MASK (3 << LPTIM_CFGR_CKPOL_SHIFT) -# define LPTIM_CFGR_CKPOL_RISING (0 << LPTIM_CFGR_CKPOL_SHIFT) /* 00: Rising Edge */ -# define LPTIM_CFGR_CKPOL_FALLING (1 << LPTIM_CFGR_CKPOL_SHIFT) /* 01: Falling Edge */ -# define LPTIM_CFGR_CKPOL_BOTH (2 << LPTIM_CFGR_CKPOL_SHIFT) /* 00: Both Edges */ - -#define LPTIM_CFGR_CKFLT_SHIFT (3) /* Bits 4-3: Digital filter for external clock */ -#define LPTIM_CFGR_CKFLTN_MASK (3 << LPTIM_CFGR_CKFLT_SHIFT) - /* Bit 5: reserved */ -#define LPTIM_CFGR_TRGFLT_SHIFT (6) /* Bits 7-6: Digital filter for trigger */ -#define LPTIM_CFGR_TRGFLT_MASK (3 << LPTIM_CFGR_TRGFLT_SHIFT) - /* Bit 8: reserved */ -#define LPTIM_CFGR_PRESC_SHIFT (9) /* Bits 11-9: clock pre-scaler */ -#define LPTIM_CFGR_PRESC_MASK (7 << LPTIM_CFGR_PRESC_SHIFT) -# define LPTIM_CFGR_PRESCd1 (0 << LPTIM_CFGR_PRESC_SHIFT) /* 000: divide by 1 */ -# define LPTIM_CFGR_PRESCd2 (1 << LPTIM_CFGR_PRESC_SHIFT) /* 001: divide by 2 */ -# define LPTIM_CFGR_PRESCd4 (2 << LPTIM_CFGR_PRESC_SHIFT) /* 010: divide by 4 */ -# define LPTIM_CFGR_PRESCd8 (3 << LPTIM_CFGR_PRESC_SHIFT) /* 011: divide by 8 */ -# define LPTIM_CFGR_PRESCd16 (4 << LPTIM_CFGR_PRESC_SHIFT) /* 100: divide by 16 */ -# define LPTIM_CFGR_PRESCd32 (5 << LPTIM_CFGR_PRESC_SHIFT) /* 101: divide by 32 */ -# define LPTIM_CFGR_PRESCd64 (6 << LPTIM_CFGR_PRESC_SHIFT) /* 110: divide by 64 */ -# define LPTIM_CFGR_PRESCd128 (7 << LPTIM_CFGR_PRESC_SHIFT) /* 111: divide by 128 */ - - /* Bit 12: reserved */ -#define LPTIM_CFGR_TRIGSEL_SHIFT (13) /* Bits 15-13: Trigger selector */ -#define LPTIM_CFGR_TRIGSEL_MASK (7 << LPTIM_CFGR_TRIGSEL_SHIFT) - /* Bit 16: reserved */ -#define LPTIM_CFGR_TRIGEN_SHIFT (17) /* Bits 18-17: Trigger enable and polarity */ -#define LPTIM_CFGR_TRIGEN_MASK (3 << LPTIM_CFGR_TRIGEN_SHIFT) -#define LPTIM_CFGR_TIMOUT (1 << 19) /* Bit 19: Timeout enable */ -#define LPTIM_CFGR_WAVE (1 << 20) /* Bit 20: Waveform shape */ -#define LPTIM_CFGR_WAVPOL (1 << 21) /* Bit 21: Waveform polarity */ -#define LPTIM_CFGR_PRELOAD (1 << 22) /* Bit 22: Update mode enable */ -#define LPTIM_CFGR_COUNTMODE (1 << 23) /* Bit 23: Count mode enable */ -#define LPTIM_CFGR_ENC (1 << 24) /* Bit 24: Encoder mode enable (LPTIM1 only) */ - -#define LPTIM_CR_ENABLE (1 << 0) /* Bit 0: Enable */ -#define LPTIM_CR_SNGSTRT (1 << 1) /* Bit 1: Single Mode */ -#define LPTIM_CR_CNTSTRT (1 << 2) /* Bit 2: Continuous Mode */ - -#define LPTIM_ISR_CMPM (1 << 0) /* Bit 0: Compare match */ -#define LPTIM_ISR_ARRM (1 << 1) /* Bit 1: Autoreload match */ -#define LPTIM_ISR_EXTTRIG (1 << 2) /* Bit 2: External trigger edge event */ -#define LPTIM_ISR_CMPOK (1 << 3) /* Bit 3: Compare register update OK */ -#define LPTIM_ISR_ARROK (1 << 4) /* Bit 4: Autoreload register update OK */ -#define LPTIM_ISR_UP (1 << 5) /* Bit 5: Counter direction change down to up */ -#define LPTIM_ISR_DOWN (1 << 6) /* Bit 6: Counter direction change up to down */ - -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_LPTIM_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_lptim.c b/arch/arm/src/stm32l4/stm32l4_lptim.c deleted file mode 100644 index 217ae4e2d79..00000000000 --- a/arch/arm/src/stm32l4/stm32l4_lptim.c +++ /dev/null @@ -1,799 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_lptim.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2016 Motorola Mobility LLC. All rights reserved. - * SPDX-FileCopyrightText: 2011-2012, 2017 Gregory Nutt. All rights reserved. - * SPDX-FileCopyrightText: 2011 Uros Platise. All rights reserved. - * SPDX-FileContributor: Gregory Nutt <[email protected]> - * SPDX-FileContributor: Uros Platise <[email protected]> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Copyright (c) 2015 Google, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its - * may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include <nuttx/config.h> - -#include <assert.h> -#include <errno.h> - -#include <arch/board/board.h> - -#include "stm32.h" -#include "stm32l4_gpio.h" -#include "stm32l4_lptim.h" -#include "stm32l4_rcc.h" - -#if defined(CONFIG_STM32_LPTIM1) || defined(CONFIG_STM32_LPTIM2) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* TIM Device Structure */ - -struct stm32_lptim_priv_s -{ - const struct stm32_lptim_ops_s *ops; - stm32_lptim_mode_t mode; - uint32_t base; /* LPTIMn base address */ - uint32_t freq; /* Clocking for the LPTIM module */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static struct stm32_lptim_dev_s *stm32_lptim_getstruct(int timer); -static inline void stm32_modifyreg32(struct stm32_lptim_dev_s *dev, - uint8_t offset, uint32_t clearbits, - uint32_t setbits); -static int stm32_lptim_enable(struct stm32_lptim_dev_s *dev); -static int stm32_lptim_disable(struct stm32_lptim_dev_s *dev); -static int stm32_lptim_reset(struct stm32_lptim_dev_s *dev); -static int stm32_lptim_get_gpioconfig(struct stm32_lptim_dev_s *dev, - stm32_lptim_channel_t channel, - uint32_t *cfg); -static int stm32_lptim_setmode(struct stm32_lptim_dev_s *dev, - stm32_lptim_mode_t mode); -static int stm32_lptim_setclock(struct stm32_lptim_dev_s *dev, - uint32_t freq); -static int stm32_lptim_setchannel(struct stm32_lptim_dev_s *dev, - stm32_lptim_channel_t channel, - int enable); -static int stm32_lptim_setclocksource(struct stm32_lptim_dev_s *dev, - stm32_lptim_clksrc_t clksrc); -static int stm32_lptim_setpolarity(struct stm32_lptim_dev_s *dev, - stm32_lptim_clkpol_t polarity); -static -uint32_t stm32_lptim_getcounter(struct stm32_lptim_dev_s *dev); -static int stm32_lptim_setcountmode(struct stm32_lptim_dev_s *dev, - stm32_lptim_cntmode_t cntmode); -static void stm32_lptim_setperiod(struct stm32_lptim_dev_s *dev, - uint32_t period); -static uint32_t stm32_lptim_getperiod(struct stm32_lptim_dev_s *dev); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct stm32_lptim_ops_s stm32_lptim_ops = -{ - .setmode = &stm32_lptim_setmode, - .setclock = &stm32_lptim_setclock, - .setchannel = &stm32_lptim_setchannel, - .setclocksource = &stm32_lptim_setclocksource, - .setpolarity = &stm32_lptim_setpolarity, - .getcounter = &stm32_lptim_getcounter, - .setcountmode = &stm32_lptim_setcountmode, - .setperiod = &stm32_lptim_setperiod, - .getperiod = &stm32_lptim_getperiod -}; - -#if defined(CONFIG_STM32_LPTIM1) -static struct stm32_lptim_priv_s stm32_lptim1_priv = -{ - .ops = &stm32_lptim_ops, - .mode = STM32_LPTIM_MODE_UNUSED, - .base = STM32_LPTIM1_BASE, - .freq = STM32_LPTIM1_CLKIN, /* Must be defined in board.h */ -}; -#endif - -#if defined(CONFIG_STM32_LPTIM2) -static struct stm32_lptim_priv_s stm32_lptim2_priv = -{ - .ops = &stm32_lptim_ops, - .mode = STM32_LPTIM_MODE_UNUSED, - .base = STM32_LPTIM2_BASE, - .freq = STM32_LPTIM2_CLKIN, /* Must be defined in board.h */ -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_lptim_getstruct - ****************************************************************************/ - -static struct stm32_lptim_dev_s *stm32_lptim_getstruct(int timer) -{ - switch (timer) - { -#if defined(CONFIG_STM32_LPTIM1) - case 1: - return (struct stm32_lptim_dev_s *)&stm32_lptim1_priv; -#endif -#if defined(CONFIG_STM32_LPTIM2) - case 2: - return (struct stm32_lptim_dev_s *)&stm32_lptim2_priv; -#endif - default: - return NULL; - } -} - -/**************************************************************************** - * Name: stm32_modifyreg32 - ****************************************************************************/ - -static inline void stm32_modifyreg32(struct stm32_lptim_dev_s *dev, - uint8_t offset, uint32_t clearbits, - uint32_t setbits) -{ - modifyreg32(((struct stm32_lptim_priv_s *)dev)->base + offset, - clearbits, setbits); -} - -/**************************************************************************** - * Name: stm32_lptim_enable - ****************************************************************************/ - -static int stm32_lptim_enable(struct stm32_lptim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - - switch (((struct stm32_lptim_priv_s *)dev)->base) - { -#if defined(CONFIG_STM32_LPTIM1) - case STM32_LPTIM1_BASE: - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_LPTIM1EN); - break; -#endif -#if defined(CONFIG_STM32_LPTIM2) - case STM32_LPTIM2_BASE: - modifyreg32(STM32_RCC_APB1ENR2, 0, RCC_APB1ENR2_LPTIM2EN); - break; -#endif - - default: - return ERROR; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_lptim_disable - ****************************************************************************/ - -static int stm32_lptim_disable(struct stm32_lptim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - - switch (((struct stm32_lptim_priv_s *)dev)->base) - { -#if defined(CONFIG_STM32_LPTIM1) - case STM32_LPTIM1_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_LPTIM1EN, 0); - break; -#endif -#if defined(CONFIG_STM32_LPTIM2) - case STM32_LPTIM2_BASE: - modifyreg32(STM32_RCC_APB1ENR2, RCC_APB1ENR2_LPTIM2EN, 0); - break; -#endif - - default: - return ERROR; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_lptim_reset - ****************************************************************************/ - -static int stm32_lptim_reset(struct stm32_lptim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - - switch (((struct stm32_lptim_priv_s *)dev)->base) - { -#if defined(CONFIG_STM32_LPTIM1) - case STM32_LPTIM1_BASE: - modifyreg32(STM32_RCC_APB1RSTR1, 0, RCC_APB1RSTR1_LPTIM1RST); - modifyreg32(STM32_RCC_APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST, 0); - break; -#endif -#if defined(CONFIG_STM32_LPTIM2) - case STM32_LPTIM2_BASE: - modifyreg32(STM32_RCC_APB1RSTR2, 0, RCC_APB1RSTR2_LPTIM2RST); - modifyreg32(STM32_RCC_APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST, 0); - break; -#endif - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_lptim_get_gpioconfig - ****************************************************************************/ - -static int stm32_lptim_get_gpioconfig(struct stm32_lptim_dev_s *dev, - stm32_lptim_channel_t channel, - uint32_t *cfg) -{ - DEBUGASSERT(dev != NULL && cfg != NULL); - - channel &= STM32_LPTIM_CH_MASK; - - switch (((struct stm32_lptim_priv_s *)dev)->base) - { -#if defined(CONFIG_STM32_LPTIM1) - case STM32_LPTIM1_BASE: - switch (channel) - { -# if defined(GPIO_LPTIM1_OUT_1) - case 1: - *cfg = GPIO_LPTIM1_OUT_1; - break; -# endif -# if defined(GPIO_LPTIM1_OUT_2) - case 2: - *cfg = GPIO_LPTIM1_OUT_2; - break; -# endif -# if defined(GPIO_LPTIM1_OUT_3) - case 3: - *cfg = GPIO_LPTIM1_OUT_3; - break; -# endif - default: - return ERROR; - } - break; -#endif /* CONFIG_STM32_LPTIM1 */ - -#if defined(CONFIG_STM32_LPTIM2) - case STM32_LPTIM2_BASE: - switch (channel) - { -# if defined(GPIO_LPTIM2_OUT_1) - case 1: - *cfg = GPIO_LPTIM2_OUT_1; - break; -# endif -# if defined(GPIO_LPTIM2_OUT_2) - case 2: - *cfg = GPIO_LPTIM2_OUT_2; - break; -# endif -# if defined(GPIO_LPTIM2_OUT_3) - case 3: - *cfg = GPIO_LPTIM2_OUT_3; - break; -# endif - default: - return ERROR; - } - break; -#endif /* CONFIG_STM32_LPTIM2 */ - - default: - return ERROR; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_lptim_setmode - ****************************************************************************/ - -static int stm32_lptim_setmode(struct stm32_lptim_dev_s *dev, - stm32_lptim_mode_t mode) -{ - const uint32_t addr = ((struct stm32_lptim_priv_s *)dev)->base + - STM32_LPTIM_CR_OFFSET; - - DEBUGASSERT(dev != NULL); - - /* Mode */ - - switch (mode & STM32_LPTIM_MODE_MASK) - { - case STM32_LPTIM_MODE_DISABLED: - modifyreg32(addr, LPTIM_CR_ENABLE, 0); - break; - - case STM32_LPTIM_MODE_SINGLE: - modifyreg32(addr, 0, LPTIM_CR_ENABLE); - modifyreg32(addr, 0, LPTIM_CR_SNGSTRT); - break; - - case STM32_LPTIM_MODE_CONTINUOUS: - modifyreg32(addr, 0, LPTIM_CR_ENABLE); - modifyreg32(addr, 0, LPTIM_CR_CNTSTRT); - break; - - default: - return ERROR; - } - - /* Save mode */ - - ((struct stm32_lptim_priv_s *)dev)->mode = mode; - - return OK; -} - -/**************************************************************************** - * Name: stm32_lptim_setclock - ****************************************************************************/ - -static int stm32_lptim_setclock(struct stm32_lptim_dev_s *dev, - uint32_t freq) -{ - struct stm32_lptim_priv_s *priv = - (struct stm32_lptim_priv_s *)dev; - uint32_t setbits; - uint32_t actual; - - DEBUGASSERT(dev != NULL); - - /* Disable Timer? */ - - if (freq == 0) - { - stm32_lptim_disable(dev); - return 0; - } - - if (freq >= priv->freq >> 0) - { - /* More than clock source. This is as fast as we can go */ - - setbits = LPTIM_CFGR_PRESCd1; - actual = priv->freq >> 0; - } - else if (freq >= priv->freq >> 1) - { - setbits = LPTIM_CFGR_PRESCd2; - actual = priv->freq >> 1; - } - else if (freq >= priv->freq >> 2) - { - setbits = LPTIM_CFGR_PRESCd4; - actual = priv->freq >> 2; - } - else if (freq >= priv->freq >> 3) - { - setbits = LPTIM_CFGR_PRESCd8; - actual = priv->freq >> 3; - } - else if (freq >= priv->freq >> 4) - { - setbits = LPTIM_CFGR_PRESCd16; - actual = priv->freq >> 4; - } - else if (freq >= priv->freq >> 5) - { - setbits = LPTIM_CFGR_PRESCd32; - actual = priv->freq >> 5; - } - else if (freq >= priv->freq >> 6) - { - setbits = LPTIM_CFGR_PRESCd64; - actual = priv->freq >> 6; - } - else - { - /* This is as slow as we can go */ - - setbits = LPTIM_CFGR_PRESCd128; - actual = priv->freq >> 7; - } - - stm32_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_PRESC_MASK, - setbits); - stm32_lptim_enable(dev); - - return actual; -} - -/**************************************************************************** - * Name: stm32_lptim_setchannel - ****************************************************************************/ - -static int stm32_lptim_setchannel(struct stm32_lptim_dev_s *dev, - stm32_lptim_channel_t channel, - int enable) -{ - int ret = OK; - uint32_t cfg = 0; - - DEBUGASSERT(dev); - - /* Configure GPIOs */ - - ret = stm32_lptim_get_gpioconfig(dev, channel, &cfg); - if (!ret) - { - if (enable) - { - stm32_configgpio(cfg); - } - else - { - stm32_unconfiggpio(cfg); - } - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_lptim_setclocksource - ****************************************************************************/ - -static int stm32_lptim_setclocksource(struct stm32_lptim_dev_s *dev, - stm32_lptim_clksrc_t clksrc) -{ - struct stm32_lptim_priv_s *priv = - (struct stm32_lptim_priv_s *)dev; - - DEBUGASSERT(dev != NULL); - - if (clksrc == STM32_LPTIM_CLK_EXT) - { - stm32_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, - LPTIM_CFGR_CKSEL_MASK, - LPTIM_CFGR_CKSEL_EXTCLK); - } - else - { - uint32_t ccr_mask = 0; - - switch (priv->base) - { -#ifdef CONFIG_STM32_LPTIM1 - case STM32_LPTIM1_BASE: - ccr_mask = RCC_CCIPR_LPTIM1SEL_MASK; - break; -#endif -#ifdef CONFIG_STM32_LPTIM2 - case STM32_LPTIM2_BASE: - ccr_mask = RCC_CCIPR_LPTIM2SEL_MASK; - break; -#endif - } - - uint32_t ccr_bits = 0; - - switch (clksrc) - { - case STM32_LPTIM_CLK_PCLK: - switch (priv->base) - { -#ifdef CONFIG_STM32_LPTIM1 - case STM32_LPTIM1_BASE: - ccr_bits = RCC_CCIPR_LPTIM1SEL_PCLK; - break; -#endif -#ifdef CONFIG_STM32_LPTIM2 - case STM32_LPTIM2_BASE: - ccr_bits = RCC_CCIPR_LPTIM2SEL_PCLK; - break; -#endif - } - break; - case STM32_LPTIM_CLK_HSI: - switch (priv->base) - { -#ifdef CONFIG_STM32_LPTIM1 - case STM32_LPTIM1_BASE: - ccr_bits = RCC_CCIPR_LPTIM1SEL_HSI; - break; -#endif -#ifdef CONFIG_STM32_LPTIM2 - case STM32_LPTIM2_BASE: - ccr_bits = RCC_CCIPR_LPTIM2SEL_HSI; - break; -#endif - } - break; - case STM32_LPTIM_CLK_LSI: - switch (priv->base) - { -#ifdef CONFIG_STM32_LPTIM1 - case STM32_LPTIM1_BASE: - ccr_bits = RCC_CCIPR_LPTIM1SEL_LSI; - break; -#endif -#ifdef CONFIG_STM32_LPTIM2 - case STM32_LPTIM2_BASE: - ccr_bits = RCC_CCIPR_LPTIM2SEL_LSI; - break; -#endif - } - break; - case STM32_LPTIM_CLK_LSE: - switch (priv->base) - { -#ifdef CONFIG_STM32_LPTIM1 - case STM32_LPTIM1_BASE: - ccr_bits = RCC_CCIPR_LPTIM1SEL_LSE; - break; -#endif -#ifdef CONFIG_STM32_LPTIM2 - case STM32_LPTIM2_BASE: - ccr_bits = RCC_CCIPR_LPTIM2SEL_LSE; - break; -#endif - } - break; - default: - break; - } - - modifyreg32(STM32_RCC_CCIPR, ccr_mask, ccr_bits); - - stm32_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, - LPTIM_CFGR_CKSEL_MASK, - LPTIM_CFGR_CKSEL_INTCLK); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_lptim_setperiod - ****************************************************************************/ - -static void stm32_lptim_setperiod(struct stm32_lptim_dev_s *dev, - uint32_t period) -{ - struct stm32_lptim_priv_s *priv = - (struct stm32_lptim_priv_s *)dev; - - DEBUGASSERT(dev != NULL); - putreg32(period, (uintptr_t)(priv->base + STM32_LPTIM_ARR_OFFSET)); -} - -/**************************************************************************** - * Name: stm32_tim_getperiod - ****************************************************************************/ - -static uint32_t stm32_lptim_getperiod(struct stm32_lptim_dev_s *dev) -{ - struct stm32_lptim_priv_s *priv = - (struct stm32_lptim_priv_s *)dev; - - DEBUGASSERT(dev != NULL); - return getreg32((uintptr_t)(priv->base + STM32_LPTIM_ARR_OFFSET)); -} - -/**************************************************************************** - * Name: stm32_lptim_setcountmode - ****************************************************************************/ - -static int stm32_lptim_setcountmode(struct stm32_lptim_dev_s *dev, - stm32_lptim_cntmode_t cntmode) -{ - DEBUGASSERT(dev != NULL); - - if (cntmode == STM32_LPTIM_COUNT_CLOCK) - { - stm32_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, - LPTIM_CFGR_COUNTMODE, 0); - } - else if (cntmode == STM32_LPTIM_COUNT_EXTTRIG) - { - stm32_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, - 0, LPTIM_CFGR_COUNTMODE); - } - else - { - return ERROR; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_lptim_setpolarity - ****************************************************************************/ - -static int stm32_lptim_setpolarity(struct stm32_lptim_dev_s *dev, - stm32_lptim_clkpol_t polarity) -{ - DEBUGASSERT(dev != NULL); - - switch (polarity) - { - case STM32_LPTIM_CLKPOL_RISING: - stm32_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, - LPTIM_CFGR_CKPOL_MASK, - LPTIM_CFGR_CKPOL_RISING); - break; - - case STM32_LPTIM_CLKPOL_FALLING: - stm32_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, - LPTIM_CFGR_CKPOL_MASK, - LPTIM_CFGR_CKPOL_FALLING); - break; - - case STM32_LPTIM_CLKPOL_BOTH: - stm32_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, - LPTIM_CFGR_CKPOL_MASK, - LPTIM_CFGR_CKPOL_BOTH); - break; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_lptim_setpolarity - ****************************************************************************/ - -static uint32_t stm32_lptim_getcounter(struct stm32_lptim_dev_s *dev) -{ - struct stm32_lptim_priv_s *priv = - (struct stm32_lptim_priv_s *)dev; - - DEBUGASSERT(dev != NULL); - - uint32_t counter1; - uint32_t counter2; - - do - { - counter1 = getreg32((uintptr_t)(priv->base + - STM32_LPTIM_CNT_OFFSET)); - counter2 = getreg32((uintptr_t)(priv->base + - STM32_LPTIM_CNT_OFFSET)); - } - while (counter1 != counter2); - - return counter1; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_lptim_init - ****************************************************************************/ - -struct stm32_lptim_dev_s *stm32_lptim_init(int timer) -{ - struct stm32_lptim_dev_s *dev = NULL; - - /* Get structure and enable power */ - - dev = stm32_lptim_getstruct(timer); - if (!dev) - { - return NULL; - } - - /* Is device already allocated */ - - if (((struct stm32_lptim_priv_s *)dev)->mode != - STM32_LPTIM_MODE_UNUSED) - { - return NULL; - } - - /* Enable power */ - - stm32_lptim_enable(dev); - - /* Reset timer */ - - stm32_lptim_reset(dev); - - /* Mark it as used */ - - ((struct stm32_lptim_priv_s *)dev)->mode = STM32_LPTIM_MODE_DISABLED; - - return dev; -} - -/**************************************************************************** - * Name: stm32_lptim_deinit - ****************************************************************************/ - -int stm32_lptim_deinit(struct stm32_lptim_dev_s * dev) -{ - DEBUGASSERT(dev); - - /* Disable power */ - - stm32_lptim_disable(dev); - - /* Mark it as free */ - - ((struct stm32_lptim_priv_s *)dev)->mode = STM32_LPTIM_MODE_UNUSED; - - return OK; -} - -#endif /* CONFIG_STM32_LPTIM1 || CONFIG_STM32_LPTIM2 */ diff --git a/arch/arm/src/stm32l4/stm32l4_lptim.h b/arch/arm/src/stm32l4/stm32l4_lptim.h deleted file mode 100644 index 5cba0f903b2..00000000000 --- a/arch/arm/src/stm32l4/stm32l4_lptim.h +++ /dev/null @@ -1,216 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_lptim.h - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2016 Motorola Mobility LLC. All rights reserved. - * SPDX-FileCopyrightText: 2011-2012, 2017 Gregory Nutt. All rights reserved. - * SPDX-FileCopyrightText: 2011 Uros Platise. All rights reserved. - * SPDX-FileContributor: Gregory Nutt <[email protected]> - * SPDX-FileContributor: Uros Platise <[email protected]> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Copyright (c) 2015 Google, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its - * may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A - * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_LPTIM_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_LPTIM_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include <nuttx/config.h> - -#include "chip.h" -#include "hardware/stm32l4_lptim.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Helpers ******************************************************************/ - -#define STM32_LPTIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32_LPTIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32_LPTIM_SETCHANNEL(d,ch,en) ((d)->ops->setchannel(d,ch,en)) -#define STM32_LPTIM_SETCLOCKSOURCE(d,s) ((d)->ops->setclocksource(d,s)) -#define STM32_LPTIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32_LPTIM_SETCOUNTMODE(d,m) ((d)->ops->setcountmode(d,m)) -#define STM32_LPTIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32_LPTIM_GETPERIOD(d) ((d)->ops->getperiod(d)) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#if defined(__cplusplus) -extern "C" -{ -#endif - -/* LPTIM Device Structure */ - -struct stm32_lptim_dev_s -{ - struct stm32_lptim_ops_s *ops; -}; - -/* LPTIM Modes of Operation */ - -typedef enum -{ - STM32_LPTIM_MODE_UNUSED = -1, - - /* MODES */ - - STM32_LPTIM_MODE_DISABLED = 0x0000, - STM32_LPTIM_MODE_SINGLE = 0x0001, - STM32_LPTIM_MODE_CONTINUOUS = 0x0002, - STM32_LPTIM_MODE_MASK = 0x000f, -} stm32_lptim_mode_t; - -/* LPTIM Clock Source */ - -typedef enum -{ - /* Clock Sources */ - - STM32_LPTIM_CLK_PCLK = 0x0000, - STM32_LPTIM_CLK_LSI = 0x0001, - STM32_LPTIM_CLK_HSI = 0x0002, - STM32_LPTIM_CLK_LSE = 0x0003, - STM32_LPTIM_CLK_EXT = 0x0004, -} stm32_lptim_clksrc_t; - -/* LPTIM Counter Modes */ - -typedef enum -{ - /* Modes */ - - STM32_LPTIM_COUNT_CLOCK = 0x0000, - STM32_LPTIM_COUNT_EXTTRIG = 0x0001, -} stm32_lptim_cntmode_t; - -/* LPTIM Clock Polarity */ - -typedef enum -{ - /* MODES */ - - STM32_LPTIM_CLKPOL_RISING = 0x0000, - STM32_LPTIM_CLKPOL_FALLING = 0x0001, - STM32_LPTIM_CLKPOL_BOTH = 0x0002, -} stm32_lptim_clkpol_t; - -/* LPTIM Channel Modes */ - -typedef enum -{ - STM32_LPTIM_CH_DISABLED = 0x0000, - - /* CHANNELS */ - - STM32_LPTIM_CH_CHINVALID = 0x0000, - STM32_LPTIM_CH_CH1 = 0x0001, - STM32_LPTIM_CH_CH2 = 0x0002, - STM32_LPTIM_CH_CH3 = 0x0003, - STM32_LPTIM_CH_MASK = 0x000f, -} stm32_lptim_channel_t; - -/* LPTIM Operations */ - -struct stm32_lptim_ops_s -{ - int (*setmode)(struct stm32_lptim_dev_s *dev, - stm32_lptim_mode_t mode); - int (*setclock)(struct stm32_lptim_dev_s *dev, uint32_t freq); - int (*setchannel)(struct stm32_lptim_dev_s *dev, - stm32_lptim_channel_t channel, int enable); - int (*setclocksource)(struct stm32_lptim_dev_s *dev, - stm32_lptim_clksrc_t clksrc); - int (*setpolarity)(struct stm32_lptim_dev_s *dev, - stm32_lptim_clkpol_t polarity); - uint32_t (*getcounter)(struct stm32_lptim_dev_s *dev); - int (*setcountmode)(struct stm32_lptim_dev_s *dev, - stm32_lptim_cntmode_t cntmode); - void (*setperiod)(struct stm32_lptim_dev_s *dev, uint32_t period); - uint32_t (*getperiod)(struct stm32_lptim_dev_s *dev); -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Get timer structure, power-up, reset, and mark it as used */ - -struct stm32_lptim_dev_s *stm32_lptim_init(int timer); - -/* Power-down timer, mark it as unused */ - -int stm32_lptim_deinit(struct stm32_lptim_dev_s *dev); - -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_LPTIM_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.h b/arch/arm/src/stm32l4/stm32l4_pwm.h index da520c3e826..31c20f0de69 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwm.h +++ b/arch/arm/src/stm32l4/stm32l4_pwm.h @@ -40,7 +40,7 @@ #include "chip.h" #include "hardware/stm32_tim.h" -#include "hardware/stm32l4_lptim.h" +#include "hardware/stm32_lptim.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32l5/Kconfig b/arch/arm/src/stm32l5/Kconfig index 6195b789841..aaddb0aa458 100644 --- a/arch/arm/src/stm32l5/Kconfig +++ b/arch/arm/src/stm32l5/Kconfig @@ -14,6 +14,7 @@ config STM32_L5_PERIPHERALS select STM32_HAVE_IP_GPIO_M33_V1 select STM32_HAVE_IP_TIMERS_V2 select STM32_HAVE_IP_DBGMCU_V4 + select STM32_HAVE_IP_LPTIM_V1 select STM32_HAVE_IP_WDG_V2 select STM32_HAVE_IP_USART_M33_V3 select STM32_HAVE_RTC_SUBSECONDS diff --git a/arch/arm/src/stm32n6/Kconfig b/arch/arm/src/stm32n6/Kconfig index 7a2ef876b36..a40d82f5de8 100644 --- a/arch/arm/src/stm32n6/Kconfig +++ b/arch/arm/src/stm32n6/Kconfig @@ -12,6 +12,7 @@ config STM32_N6_PERIPHERALS default y select STM32_HAVE_IP_TIMERS_V3 select STM32_HAVE_IP_DBGMCU_V8 + select STM32_HAVE_IP_LPTIM_V2 select STM32_HAVE_IP_WDG_V3 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 diff --git a/arch/arm/src/stm32u0/Kconfig b/arch/arm/src/stm32u0/Kconfig index a830d42bcd1..ead64576f98 100644 --- a/arch/arm/src/stm32u0/Kconfig +++ b/arch/arm/src/stm32u0/Kconfig @@ -147,6 +147,7 @@ config STM32_STM32U0 select STM32_HAVE_IP_COMP_M0_V1 if STM32_HAVE_COMP select STM32_HAVE_IP_DAC_M0_V1 if STM32_HAVE_DAC1 select STM32_HAVE_IP_DBGMCU_V3 + select STM32_HAVE_IP_LPTIM_V2 select STM32_HAVE_IP_DMA_V1 select STM32_HAVE_IP_DMA_V1_7CH_DMAMUX select STM32_HAVE_IP_EXTI_V2 diff --git a/arch/arm/src/stm32u3/Kconfig b/arch/arm/src/stm32u3/Kconfig index f23453d817c..363a4ba27e8 100644 --- a/arch/arm/src/stm32u3/Kconfig +++ b/arch/arm/src/stm32u3/Kconfig @@ -16,6 +16,7 @@ config STM32_U3_PERIPHERALS select STM32_HAVE_IP_GPIO_M33_V1 select STM32_HAVE_IP_TIMERS_V3 select STM32_HAVE_IP_DBGMCU_V5 + select STM32_HAVE_IP_LPTIM_V2 select STM32_HAVE_IP_WDG_V3 select STM32_HAVE_IP_USART_M33_V3 select STM32_HAVE_SYSCFG diff --git a/arch/arm/src/stm32u5/Kconfig b/arch/arm/src/stm32u5/Kconfig index ece2d908f8d..2246104e95b 100644 --- a/arch/arm/src/stm32u5/Kconfig +++ b/arch/arm/src/stm32u5/Kconfig @@ -16,6 +16,7 @@ config STM32_U5_PERIPHERALS select STM32_HAVE_IP_GPIO_M33_V1 select STM32_HAVE_IP_TIMERS_V3 select STM32_HAVE_IP_DBGMCU_V5 + select STM32_HAVE_IP_LPTIM_V2 select STM32_HAVE_IP_USART_M33_V3 select STM32_HAVE_COMP select STM32_HAVE_CRS diff --git a/arch/arm/src/stm32u5/hardware/stm32_rcc.h b/arch/arm/src/stm32u5/hardware/stm32_rcc.h index aaebbddb012..78b4fa6c61e 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_rcc.h +++ b/arch/arm/src/stm32u5/hardware/stm32_rcc.h @@ -390,6 +390,12 @@ #define RCC_APB2RSTR_SAI1RST (1 << 21) /* Bit 21: SAI1 reset */ #define RCC_APB2RSTR_SAI2RST (1 << 22) /* Bit 22: SAI2 reset */ +/* APB3 peripheral reset register */ + +#define RCC_APB3RSTR_LPTIM1RST (1 << 11) /* Bit 11: LPTIM1 reset */ +#define RCC_APB3RSTR_LPTIM3RST (1 << 12) /* Bit 12: LPTIM3 reset */ +#define RCC_APB3RSTR_LPTIM4RST (1 << 13) /* Bit 13: LPTIM4 reset */ + /* AHB1 Peripheral Clock enable register */ #define RCC_AHB1ENR_GPDMA1EN (1 << 0) /* Bit 0: GPDMA1 clock enable */ diff --git a/arch/arm/src/stm32wb/Kconfig b/arch/arm/src/stm32wb/Kconfig index 37a8836fd0e..64b42934130 100644 --- a/arch/arm/src/stm32wb/Kconfig +++ b/arch/arm/src/stm32wb/Kconfig @@ -28,6 +28,7 @@ config STM32_WB_PERIPHERALS select STM32_HAVE_SYSCFG select STM32_HAVE_USART1 select STM32_HAVE_IP_DBGMCU_V6 + select STM32_HAVE_IP_LPTIM_V1 select STM32_HAVE_IP_WDG_V2 choice diff --git a/arch/arm/src/stm32wl5/Kconfig b/arch/arm/src/stm32wl5/Kconfig index acfe717f13c..baacf43cdf2 100644 --- a/arch/arm/src/stm32wl5/Kconfig +++ b/arch/arm/src/stm32wl5/Kconfig @@ -42,6 +42,7 @@ config STM32_STM32WL5XXX bool select STM32_HAVE_IP_TIMERS_V2 select STM32_HAVE_IP_DBGMCU_V6 + select STM32_HAVE_IP_LPTIM_V1 select STM32_HAVE_IP_WDG_V2 config STM32_STM32WL5XXX_CPU1
