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commit 89eeb7685b1633acaff65da6de896caa36957cc0 Author: zhangyuan29 <[email protected]> AuthorDate: Thu Aug 14 22:09:12 2025 +0800 arch/tricore: fixed tc3xx tos issue tc3xx core2~core5 tos is 2~5, change to get the right tos value. Signed-off-by: zhangyuan29 <[email protected]> --- arch/tricore/src/common/tricore_irq.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/tricore/src/common/tricore_irq.c b/arch/tricore/src/common/tricore_irq.c index 41e966da053..b0213a31c79 100644 --- a/arch/tricore/src/common/tricore_irq.c +++ b/arch/tricore/src/common/tricore_irq.c @@ -92,18 +92,22 @@ static int g_irqmap_count = 1; static void tricore_gpsrinitialize(void) { - volatile Ifx_SRC_SRCR *src = &SRC_GPSR00 + up_cpu_index(); + volatile Ifx_SRC_SRCR *src; + int cpu_idx; int i; + cpu_idx = up_cpu_index(); + src = &SRC_GPSR00 + cpu_idx; + /* Cpux gpsr init */ for (i = 0; i < 6; i++) { #ifdef CONFIG_ARCH_CHIP_TC3XX - IfxSrc_init(src, IfxSrc_Tos_cpu0 + up_cpu_index(), + IfxSrc_init(src, (cpu_idx == 0 ? IfxSrc_Tos_cpu0 : cpu_idx + 1), IRQ_TO_NDX(TRICORE_SRC2IRQ(src))); #else - IfxSrc_init(src, IfxSrc_Tos_cpu0 + up_cpu_index(), + IfxSrc_init(src, IfxSrc_Tos_cpu0 + cpu_idx, IRQ_TO_NDX(TRICORE_SRC2IRQ(src)), IfxSrc_VmId_none); #endif @@ -114,8 +118,8 @@ static void tricore_gpsrinitialize(void) /* Cpucs gpsr init */ #ifndef CONFIG_ARCH_CHIP_TC3XX - src = &SRC_GPSR6_SR0 + up_cpu_index(); - IfxSrc_init(src, IfxSrc_Tos_cpu0 + up_cpu_index(), + src = &SRC_GPSR6_SR0 + cpu_idx; + IfxSrc_init(src, IfxSrc_Tos_cpu0 + cpu_idx, IRQ_TO_NDX(TRICORE_SRC2IRQ(src)), IfxSrc_VmId_none); #endif
