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commit 51cec7607b183e716f1c297fc586ac021917f784 Author: wanggang26 <[email protected]> AuthorDate: Tue Dec 17 10:55:39 2024 +0800 arch/tricore: adaptive multi cores for irq Route the irq to the cpu that enables it instead of always cpu0, use per-cpu GPSR for irq trigger, and support up_affinity_irq. Signed-off-by: wanggang26 <[email protected]> Signed-off-by: zhangyuan29 <[email protected]> --- arch/tricore/src/common/tricore_irq.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/tricore/src/common/tricore_irq.c b/arch/tricore/src/common/tricore_irq.c index f8e4c6078ec..41e966da053 100644 --- a/arch/tricore/src/common/tricore_irq.c +++ b/arch/tricore/src/common/tricore_irq.c @@ -189,9 +189,10 @@ void up_enable_irq(int irq) volatile Ifx_SRC_SRCR *src = &SRC_CPU_CPU0_SB + irq; #ifdef CONFIG_ARCH_CHIP_TC3XX - IfxSrc_init(src, IfxSrc_Tos_cpu0, IRQ_TO_NDX(irq)); + IfxSrc_init(src, IfxSrc_Tos_cpu0 + up_cpu_index(), IRQ_TO_NDX(irq)); #else - IfxSrc_init(src, IfxSrc_Tos_cpu0, IRQ_TO_NDX(irq), IfxSrc_VmId_none); + IfxSrc_init(src, IfxSrc_Tos_cpu0 + up_cpu_index(), IRQ_TO_NDX(irq), + IfxSrc_VmId_none); #endif IfxSrc_enable(src);
