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commit 74239e55e5ec0a9715537fd308959311ea02da28 Author: raiden00pl <[email protected]> AuthorDate: Wed Nov 4 13:17:06 2026 +0100 arch/arm/src/stm32h7: Remove the PLL1 R output on STM32H7R/S. PLL1 of STM32H7R/S has no R output: RCC_PLLCFGR bit 7 and RCC_PLL1DIVR1 bits 30:24 are reserved. Drop PLL1REN and the PLL1 R divider from the header and the boards, and keep the PLL1DIVR1 reserved bits at reset. Assisted-by: Claude Code:claude-opus-5-5 Signed-off-by: raiden00pl <[email protected]> --- arch/arm/src/stm32h7/hardware/stm32h7rsxx_rcc.h | 5 +++-- arch/arm/src/stm32h7/stm32h7rsxx_rcc.c | 8 +++++--- boards/arm/stm32h7/nucleo-h7s3l8/include/board.h | 9 ++------- boards/arm/stm32h7/stm32h7s8-dk/include/board.h | 9 ++------- 4 files changed, 12 insertions(+), 19 deletions(-) diff --git a/arch/arm/src/stm32h7/hardware/stm32h7rsxx_rcc.h b/arch/arm/src/stm32h7/hardware/stm32h7rsxx_rcc.h index 29340b878b7..6c81071feba 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7rsxx_rcc.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7rsxx_rcc.h @@ -323,7 +323,6 @@ # define RCC_PLLCFGR_PLL1RGE_8_16 (3 << RCC_PLLCFGR_PLL1RGE_SHIFT) #define RCC_PLLCFGR_PLL1PEN (1 << 5) /* PLL1 P output enable */ #define RCC_PLLCFGR_PLL1QEN (1 << 6) /* PLL1 Q output enable */ -#define RCC_PLLCFGR_PLL1REN (1 << 7) /* PLL1 R output enable */ #define RCC_PLLCFGR_PLL1SEN (1 << 8) /* PLL1 S output enable */ #define RCC_PLLCFGR_PLL2FRACEN (1 << 11) /* PLL2 fractional enable */ #define RCC_PLLCFGR_PLL2VCOSEL (1 << 12) /* PLL2 VCO selection */ @@ -346,8 +345,11 @@ #define RCC_PLLCFGR_PLL3SEN (1 << 30) /* PLL3 S output enable */ #define RCC_PLLDIVR_DIVN_SHIFT (0) /* PLL N multiplier */ +#define RCC_PLLDIVR_DIVN_MASK (0x1ff << RCC_PLLDIVR_DIVN_SHIFT) #define RCC_PLLDIVR_DIVP_SHIFT (9) /* PLL P divider */ +#define RCC_PLLDIVR_DIVP_MASK (0x7f << RCC_PLLDIVR_DIVP_SHIFT) #define RCC_PLLDIVR_DIVQ_SHIFT (16) /* PLL Q divider */ +#define RCC_PLLDIVR_DIVQ_MASK (0x7f << RCC_PLLDIVR_DIVQ_SHIFT) #define RCC_PLLDIVR_DIVR_SHIFT (24) /* PLL R divider */ # define RCC_PLLDIVR_DIVN(n) (((n) - 1) << RCC_PLLDIVR_DIVN_SHIFT) # define RCC_PLLDIVR_DIVP(n) (((n) - 1) << RCC_PLLDIVR_DIVP_SHIFT) @@ -356,7 +358,6 @@ #define RCC_PLL1DIVR1_N(n) RCC_PLLDIVR_DIVN(n) #define RCC_PLL1DIVR1_P(n) RCC_PLLDIVR_DIVP(n) #define RCC_PLL1DIVR1_Q(n) RCC_PLLDIVR_DIVQ(n) -#define RCC_PLL1DIVR1_R(n) RCC_PLLDIVR_DIVR(n) #define RCC_PLL2DIVR1_N(n) RCC_PLLDIVR_DIVN(n) #define RCC_PLL2DIVR1_P(n) RCC_PLLDIVR_DIVP(n) #define RCC_PLL2DIVR1_Q(n) RCC_PLLDIVR_DIVQ(n) diff --git a/arch/arm/src/stm32h7/stm32h7rsxx_rcc.c b/arch/arm/src/stm32h7/stm32h7rsxx_rcc.c index bdecbaa25f6..f572361b27c 100644 --- a/arch/arm/src/stm32h7/stm32h7rsxx_rcc.c +++ b/arch/arm/src/stm32h7/stm32h7rsxx_rcc.c @@ -562,9 +562,11 @@ void stm32_stdclockconfig(void) putreg32(STM32_PLLCFG_PLLSRC | STM32_PLLCFG_PLL1M, STM32_RCC_PLLCKSELR); putreg32(STM32_PLLCFG_PLL1CFG, STM32_RCC_PLLCFGR); - putreg32(STM32_PLLCFG_PLL1N | STM32_PLLCFG_PLL1P | - STM32_PLLCFG_PLL1Q | STM32_PLLCFG_PLL1R, - STM32_RCC_PLL1DIVR1); + regval = getreg32(STM32_RCC_PLL1DIVR1); + regval &= ~(RCC_PLLDIVR_DIVN_MASK | RCC_PLLDIVR_DIVP_MASK | + RCC_PLLDIVR_DIVQ_MASK); + regval |= STM32_PLLCFG_PLL1N | STM32_PLLCFG_PLL1P | STM32_PLLCFG_PLL1Q; + putreg32(regval, STM32_RCC_PLL1DIVR1); modifyreg32(STM32_RCC_CR, 0, RCC_CR_PLL1ON); while ((getreg32(STM32_RCC_CR) & RCC_CR_PLL1RDY) == 0) diff --git a/boards/arm/stm32h7/nucleo-h7s3l8/include/board.h b/boards/arm/stm32h7/nucleo-h7s3l8/include/board.h index f186564899f..d924ff9873a 100644 --- a/boards/arm/stm32h7/nucleo-h7s3l8/include/board.h +++ b/boards/arm/stm32h7/nucleo-h7s3l8/include/board.h @@ -67,7 +67,6 @@ * * PLL1P = 600 MHz * PLL1Q = 300 MHz - * PLL1R = 300 MHz */ #ifdef CONFIG_NUCLEO_H7S3L8_USE_HSE @@ -78,8 +77,7 @@ # define STM32_PLLCFG_PLL1N RCC_PLL1DIVR1_N(50) # define STM32_PLLCFG_PLL1CFG (RCC_PLLCFGR_PLL1RGE_8_16 | \ RCC_PLLCFGR_PLL1PEN | \ - RCC_PLLCFGR_PLL1QEN | \ - RCC_PLLCFGR_PLL1REN) + RCC_PLLCFGR_PLL1QEN) #else # define STM32_BOARD_USEHSI # define STM32_PLLCFG_PLLSRC RCC_PLLCKSELR_PLLSRC_HSI @@ -87,18 +85,15 @@ # define STM32_PLLCFG_PLL1N RCC_PLL1DIVR1_N(300) # define STM32_PLLCFG_PLL1CFG (RCC_PLLCFGR_PLL1RGE_2_4 | \ RCC_PLLCFGR_PLL1PEN | \ - RCC_PLLCFGR_PLL1QEN | \ - RCC_PLLCFGR_PLL1REN) + RCC_PLLCFGR_PLL1QEN) #endif #define STM32_PLLCFG_PLL1P RCC_PLL1DIVR1_P(1) #define STM32_PLLCFG_PLL1Q RCC_PLL1DIVR1_Q(2) -#define STM32_PLLCFG_PLL1R RCC_PLL1DIVR1_R(2) #define STM32_VCO1_FREQUENCY 600000000ul #define STM32_PLL1P_FREQUENCY STM32_VCO1_FREQUENCY #define STM32_PLL1Q_FREQUENCY (STM32_VCO1_FREQUENCY / 2) -#define STM32_PLL1R_FREQUENCY (STM32_VCO1_FREQUENCY / 2) /* SYSCLK = PLL1P = 600 MHz * CPUCLK = SYSCLK diff --git a/boards/arm/stm32h7/stm32h7s8-dk/include/board.h b/boards/arm/stm32h7/stm32h7s8-dk/include/board.h index d5dac67356e..a126adacac1 100644 --- a/boards/arm/stm32h7/stm32h7s8-dk/include/board.h +++ b/boards/arm/stm32h7/stm32h7s8-dk/include/board.h @@ -67,7 +67,6 @@ * * PLL1P = 600 MHz * PLL1Q = 300 MHz - * PLL1R = 300 MHz */ #ifdef CONFIG_STM32H7S8_DK_USE_HSE @@ -78,8 +77,7 @@ # define STM32_PLLCFG_PLL1N RCC_PLL1DIVR1_N(50) # define STM32_PLLCFG_PLL1CFG (RCC_PLLCFGR_PLL1RGE_8_16 | \ RCC_PLLCFGR_PLL1PEN | \ - RCC_PLLCFGR_PLL1QEN | \ - RCC_PLLCFGR_PLL1REN) + RCC_PLLCFGR_PLL1QEN) #else # define STM32_BOARD_USEHSI # define STM32_PLLCFG_PLLSRC RCC_PLLCKSELR_PLLSRC_HSI @@ -87,18 +85,15 @@ # define STM32_PLLCFG_PLL1N RCC_PLL1DIVR1_N(300) # define STM32_PLLCFG_PLL1CFG (RCC_PLLCFGR_PLL1RGE_2_4 | \ RCC_PLLCFGR_PLL1PEN | \ - RCC_PLLCFGR_PLL1QEN | \ - RCC_PLLCFGR_PLL1REN) + RCC_PLLCFGR_PLL1QEN) #endif #define STM32_PLLCFG_PLL1P RCC_PLL1DIVR1_P(1) #define STM32_PLLCFG_PLL1Q RCC_PLL1DIVR1_Q(2) -#define STM32_PLLCFG_PLL1R RCC_PLL1DIVR1_R(2) #define STM32_VCO1_FREQUENCY 600000000ul #define STM32_PLL1P_FREQUENCY STM32_VCO1_FREQUENCY #define STM32_PLL1Q_FREQUENCY (STM32_VCO1_FREQUENCY / 2) -#define STM32_PLL1R_FREQUENCY (STM32_VCO1_FREQUENCY / 2) /* SYSCLK = PLL1P = 600 MHz * CPUCLK = SYSCLK
