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commit e362957f765a0a5b7ee47ec38d15c1f309bc302f Author: Marco Casaroli <[email protected]> AuthorDate: Tue Nov 3 21:46:41 2026 +0100 arch/arm64/imx9: Start the perf counter with ARCH_PERF_EVENTS. The i.MX9 never calls up_perf_init(), so the PMU cycle counter does not run and its rate stays ULONG_MAX. With ARCH_PERF_EVENTS (the default with SCHED_CRITMONITOR) all perf times are then 0. Call up_perf_init() at the end of arm64_chip_boot(), as the other arm64 chips do, with the clock of the A55 cores: the ARM PLL or the A55 clock root, as the shared CCM GPR selects. With IMX9_CLK_OVER_SCMI the clocks belong to the system manager, which is not ready at this point, so that case does not change. Assisted-by: Claude Code:claude-opus-5-5 Signed-off-by: Marco Casaroli <[email protected]> --- arch/arm64/src/imx9/imx9_boot.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/src/imx9/imx9_boot.c b/arch/arm64/src/imx9/imx9_boot.c index 977b5b21f35..88eca0f3bc5 100644 --- a/arch/arm64/src/imx9/imx9_boot.c +++ b/arch/arm64/src/imx9/imx9_boot.c @@ -48,6 +48,7 @@ #include "imx9_gpio.h" #include "imx9_lowputc.h" #include "imx9_system_ctl.h" +#include "hardware/imx9_ccm.h" #ifdef CONFIG_IMX9_DDR_TRAINING #include "ddr/imx9_ddr_training.h" #endif @@ -96,6 +97,37 @@ const struct arm_mmu_config g_mmu_config = .mmu_regions = g_mmu_regions, }; +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_a55_frequency + * + * Description: + * Return the clock of the A55 cores: the ARM PLL or the A55 clock root. + * + ****************************************************************************/ + +#if defined(CONFIG_ARCH_PERF_EVENTS) && !defined(CONFIG_IMX9_CLK_OVER_SCMI) +static uint32_t imx9_a55_frequency(void) +{ + uint32_t freq = 0; + + if ((getreg32(IMX9_CCM_GPR_SH(CCM_SHARED_A55_CLK)) & + CCM_GPR_A55_CLK_SEL_MASK) == CCM_GPR_A55_CLK_SEL_PLL) + { + imx9_get_clock(ARM_PLL, &freq); + } + else + { + imx9_get_rootclock(CCM_ARM_A55_CLK_ROOT, &freq); + } + + return freq; +} +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -229,4 +261,8 @@ void arm64_chip_boot(void) */ imx9_board_initialize(); + +#if defined(CONFIG_ARCH_PERF_EVENTS) && !defined(CONFIG_IMX9_CLK_OVER_SCMI) + up_perf_init((void *)(uintptr_t)imx9_a55_frequency()); +#endif }
