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commit b6e148fca6af443a7b7261f78dea93932a603f4f Author: Marco Casaroli <[email protected]> AuthorDate: Tue Nov 3 21:46:41 2026 +0100 arch/arm64/zynq-mpsoc: Give up_perf_init() the real CPU clock. zynq_boot.c calls up_perf_init() with CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, but no zynq-mpsoc header defines it, so a build with ARCH_PERF_EVENTS (the default with SCHED_CRITMONITOR) fails. The PMU cycle counter counts the cycles of the Cortex-A53. Read its clock (acpu) from the PLL registers with mpsoc_clk_rate_get(), as zynq_serial.c does for the UART clock. Assisted-by: Claude Code:claude-opus-5-5 Signed-off-by: Marco Casaroli <[email protected]> --- arch/arm64/src/zynq-mpsoc/zynq_boot.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/src/zynq-mpsoc/zynq_boot.c b/arch/arm64/src/zynq-mpsoc/zynq_boot.c index 3e002b1466e..abf10121af0 100644 --- a/arch/arm64/src/zynq-mpsoc/zynq_boot.c +++ b/arch/arm64/src/zynq-mpsoc/zynq_boot.c @@ -47,6 +47,7 @@ #include "arm64_mmu.h" #include "zynq_boot.h" #include "zynq_serial.h" +#include "hardware/zynq_pll.h" /**************************************************************************** * Private Data @@ -200,6 +201,6 @@ void arm64_chip_boot(void) #endif #ifdef CONFIG_ARCH_PERF_EVENTS - up_perf_init((void *)CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC); + up_perf_init((void *)mpsoc_clk_rate_get(acpu)); #endif }
