zhangyu-duck commented on code in PR #21546: URL: https://github.com/apache/nuttx/pull/21546#discussion_r4510127736
########## arch/tricore/src/aurix/Make.defs: ########## @@ -0,0 +1,23 @@ +############################################################################ +# arch/tricore/src/aurix/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 Review Comment: why add arc/aurix path, seems no need ########## arch/tricore/src/common/gnu/tricore_head.S: ########## @@ -0,0 +1,119 @@ +/**************************************************************************** + * arch/tricore/src/common/gnu/tricore_head.S + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Reset entry. _START only sets the stack and jumps on, as the linker + * script keeps .start to 0x20 bytes ahead of the interface constants. + * tricore_head then sets the small data base registers and the PSW and + * jumps to tricore_start, which links the CSAs before it calls anything. + * + * TC4xx first disables the virtualization with a call to a function that + * returns with rfh, using a boot stack and a single boot CSA in the PSPR, + * as the iLLD startup code does. + * + * tasking/tricore_head.asm is the same code in the TASKING syntax. + ****************************************************************************/ + +#include <nuttx/config.h> +#include <arch/csfr.h> + +#define TRICORE_PSW_RESET 0x980 /* Supervisor, call depth counting on */ + +#ifdef CONFIG_ARCH_CHIP_TC4XX +# define TC4XX_BOOT_SP 0x7010eb00 +# define TC4XX_PSW_VIRT 0xb00 /* PSW for disabling the virtualization */ +#endif + + .section .start, "ax", %progbits + .global _START + .type _START, %function +_START: +#ifdef CONFIG_ARCH_CHIP_TC4XX + movh.a %sp, hi:TC4XX_BOOT_SP + lea %sp, [%sp]lo:TC4XX_BOOT_SP +#else + movh.a %sp, hi:__USTACK0 + lea %sp, [%sp]lo:__USTACK0 +#endif Review Comment: why not Unified ########## arch/tricore/src/common/tasking/tricore_head.asm: ########## @@ -0,0 +1,109 @@ +;**************************************************************************** +; arch/tricore/src/common/tasking/tricore_head.asm +; +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed to the Apache Software Foundation (ASF) under one or more +; contributor license agreements. See the NOTICE file distributed with +; this work for additional information regarding copyright ownership. The +; ASF licenses this file to you under the Apache License, Version 2.0 (the +; "License"); you may not use this file except in compliance with the +; License. You may obtain a copy of the License at +; +; http://www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +; License for the specific language governing permissions and limitations +; under the License. +; +;**************************************************************************** +; +; TASKING (astc) version of gnu/tricore_head.S, same code; see there for the +; description. astc does not run the C preprocessor, so the CSFR offsets +; (arch/csfr.h) are written out, and TRICORE_TC4XX is set by the build. +; +;**************************************************************************** + + .extern tricore_start + .extern __USTACK0 + .extern __A0_MEM + .extern __A1_MEM + .extern __A8_MEM + .extern __A9_MEM + .extern __TRAPTAB_CPU0 + + .sdecl ".text.start",code,protect + .sect ".text.start" + .global _START +_START: + .if @DEF('TRICORE_TC4XX') + movh.a a10, #@HIS(0x7010eb00) + lea a10, [a10]@LOS(0x7010eb00) Review Comment: why fix address ########## arch/tricore/src/common/gnu/tricore_head.S: ########## @@ -0,0 +1,119 @@ +/**************************************************************************** + * arch/tricore/src/common/gnu/tricore_head.S + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Reset entry. _START only sets the stack and jumps on, as the linker + * script keeps .start to 0x20 bytes ahead of the interface constants. + * tricore_head then sets the small data base registers and the PSW and + * jumps to tricore_start, which links the CSAs before it calls anything. + * + * TC4xx first disables the virtualization with a call to a function that + * returns with rfh, using a boot stack and a single boot CSA in the PSPR, + * as the iLLD startup code does. + * + * tasking/tricore_head.asm is the same code in the TASKING syntax. + ****************************************************************************/ + +#include <nuttx/config.h> +#include <arch/csfr.h> + +#define TRICORE_PSW_RESET 0x980 /* Supervisor, call depth counting on */ + +#ifdef CONFIG_ARCH_CHIP_TC4XX +# define TC4XX_BOOT_SP 0x7010eb00 +# define TC4XX_PSW_VIRT 0xb00 /* PSW for disabling the virtualization */ +#endif + + .section .start, "ax", %progbits + .global _START + .type _START, %function +_START: +#ifdef CONFIG_ARCH_CHIP_TC4XX + movh.a %sp, hi:TC4XX_BOOT_SP + lea %sp, [%sp]lo:TC4XX_BOOT_SP +#else + movh.a %sp, hi:__USTACK0 + lea %sp, [%sp]lo:__USTACK0 +#endif + dsync + movh.a %a15, hi:tricore_head + lea %a15, [%a15]lo:tricore_head + ji %a15 + + .text + .type tricore_head, %function +tricore_head: Review Comment: /**************************************************************************** * Private Functions ****************************************************************************/ ########## arch/tricore/src/common/gnu/tricore_head.S: ########## @@ -0,0 +1,119 @@ +/**************************************************************************** + * arch/tricore/src/common/gnu/tricore_head.S + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Reset entry. _START only sets the stack and jumps on, as the linker + * script keeps .start to 0x20 bytes ahead of the interface constants. + * tricore_head then sets the small data base registers and the PSW and + * jumps to tricore_start, which links the CSAs before it calls anything. + * + * TC4xx first disables the virtualization with a call to a function that + * returns with rfh, using a boot stack and a single boot CSA in the PSPR, + * as the iLLD startup code does. + * + * tasking/tricore_head.asm is the same code in the TASKING syntax. + ****************************************************************************/ + +#include <nuttx/config.h> +#include <arch/csfr.h> + +#define TRICORE_PSW_RESET 0x980 /* Supervisor, call depth counting on */ + +#ifdef CONFIG_ARCH_CHIP_TC4XX +# define TC4XX_BOOT_SP 0x7010eb00 +# define TC4XX_PSW_VIRT 0xb00 /* PSW for disabling the virtualization */ +#endif + + .section .start, "ax", %progbits + .global _START Review Comment: __start ########## arch/tricore/src/common/tasking/tricore_head.asm: ########## @@ -0,0 +1,109 @@ +;**************************************************************************** +; arch/tricore/src/common/tasking/tricore_head.asm +; +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed to the Apache Software Foundation (ASF) under one or more +; contributor license agreements. See the NOTICE file distributed with +; this work for additional information regarding copyright ownership. The +; ASF licenses this file to you under the Apache License, Version 2.0 (the +; "License"); you may not use this file except in compliance with the +; License. You may obtain a copy of the License at +; +; http://www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +; License for the specific language governing permissions and limitations +; under the License. +; +;**************************************************************************** +; +; TASKING (astc) version of gnu/tricore_head.S, same code; see there for the +; description. astc does not run the C preprocessor, so the CSFR offsets +; (arch/csfr.h) are written out, and TRICORE_TC4XX is set by the build. +; +;**************************************************************************** + + .extern tricore_start + .extern __USTACK0 + .extern __A0_MEM + .extern __A1_MEM + .extern __A8_MEM + .extern __A9_MEM + .extern __TRAPTAB_CPU0 + + .sdecl ".text.start",code,protect + .sect ".text.start" + .global _START +_START: + .if @DEF('TRICORE_TC4XX') + movh.a a10, #@HIS(0x7010eb00) + lea a10, [a10]@LOS(0x7010eb00) + .else + movh.a a10, #@HIS(__USTACK0) Review Comment: what about other core? ########## arch/tricore/src/common/tasking/tricore_head.asm: ########## @@ -0,0 +1,109 @@ +;**************************************************************************** +; arch/tricore/src/common/tasking/tricore_head.asm +; +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed to the Apache Software Foundation (ASF) under one or more +; contributor license agreements. See the NOTICE file distributed with +; this work for additional information regarding copyright ownership. The +; ASF licenses this file to you under the Apache License, Version 2.0 (the +; "License"); you may not use this file except in compliance with the +; License. You may obtain a copy of the License at +; +; http://www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +; License for the specific language governing permissions and limitations +; under the License. +; +;**************************************************************************** +; +; TASKING (astc) version of gnu/tricore_head.S, same code; see there for the +; description. astc does not run the C preprocessor, so the CSFR offsets +; (arch/csfr.h) are written out, and TRICORE_TC4XX is set by the build. +; +;**************************************************************************** + + .extern tricore_start + .extern __USTACK0 + .extern __A0_MEM + .extern __A1_MEM + .extern __A8_MEM + .extern __A9_MEM + .extern __TRAPTAB_CPU0 + + .sdecl ".text.start",code,protect + .sect ".text.start" + .global _START +_START: + .if @DEF('TRICORE_TC4XX') Review Comment: keep way like gcc, not tasking way ########## arch/tricore/src/common/tricore_main.c: ########## @@ -24,25 +24,89 @@ * Included Files ****************************************************************************/ -#include <tricore_internal.h> +#include <nuttx/config.h> + +#include <stdint.h> + #include <nuttx/init.h> -#include "Ifx_Types.h" -#include "IfxCpu.h" +#include <arch/arch.h> + +#include "tricore_internal.h" +#include "tricore_stm.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Startup core synchronization: core ID bits to wait for and the timeout + * in STM ticks (0: no timeout) + */ + +#ifdef CONFIG_ARCH_CHIP_TC3XX +# define TRICORE_CORE_SYNC_MASK 0x5f Review Comment: tc3xx, chip.h, not here ########## arch/tricore/src/tc3xx/tc3xx_start.c: ########## @@ -0,0 +1,277 @@ +/**************************************************************************** + * arch/tricore/src/tc3xx/tc3xx_start.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdbool.h> +#include <stdint.h> + +#include <arch/arch.h> + +#include "tricore_internal.h" +#include "hardware/tc3xx_cpu.h" +#include "hardware/tc3xx_scu.h" +#include "tc3xx_wdt.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The BIV of the single interrupt vector at INTTAB + 0x1fe0 */ + +#define TC3XX_BIV_VECTOR 0x1fe0 + +/**************************************************************************** + * External Function Prototypes + ****************************************************************************/ + +void core0_main(void); + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Provided by the linker script */ + +extern uintptr_t __CSA0[]; +extern uintptr_t __CSA0_END[]; +extern uintptr_t __TRAPTAB_CPU0[]; +extern uintptr_t __INTTAB_CPU0[]; +extern uintptr_t __ISTACK0[]; +extern uintptr_t __START1[]; + +#ifndef CONFIG_TRICORE_TOOLCHAIN_TASKING +extern const uintptr_t __clear_table[]; +extern const uintptr_t __copy_table[]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tc3xx_csa_init + * + * Description: + * Link the CSAs from start to end into the free context list, with LCX + * at the third last. It runs before any function call is possible, so + * it must not call. + * + ****************************************************************************/ + +static inline_function void tc3xx_csa_init(uintptr_t *start, uintptr_t *end) +{ + uint32_t num = ((uintptr_t)end - (uintptr_t)start) / TC_CONTEXT_SIZE; + uintptr_t *prev = NULL; + uintptr_t *csa = start; + uint32_t link; + uint32_t k; + + for (k = 0; k < num; k++) + { + link = tricore_addr2csa(csa); + if (k == 0) + { + tricore_mtcr(TRICORE_CPU_FCX, link); + } + else + { + *prev = link; + } + + if (k == num - 3) + { + tricore_mtcr(TRICORE_CPU_LCX, link); + } + + prev = csa; + csa += TC_CONTEXT_REGS; + } + + *prev = 0; + UP_DSB(); +} + +/**************************************************************************** + * Name: tc3xx_application_reset + ****************************************************************************/ + +static bool tc3xx_application_reset(void) +{ + uint32_t rststat = getreg32(TC3XX_SCU_RSTSTAT); + uint32_t bit; + + if ((rststat & TC3XX_RSTSTAT_POWERON) != 0) + { + return false; + } + + if ((rststat & TC3XX_RSTSTAT_RESET) != 0) + { + rststat &= TC3XX_RSTSTAT_RESET; + for (bit = 31; (rststat & (1u << bit)) == 0; bit--); + + return ((getreg32(TC3XX_SCU_RSTCON) >> (bit << 1)) & 3) == + TC3XX_RSTCON_APPLICATION; + } + + if ((rststat & TC3XX_RSTSTAT_CB3) != 0) + { + return true; + } + + return (getreg32(TC3XX_CPU0_KRST0) & TC3XX_KRST0_RSTSTAT_MASK) != 0; +} + +/**************************************************************************** + * Name: tc3xx_c_init + * + * Description: + * Clear .bss and copy .data, from the tables of the linker script on + * GCC, with the TASKING runtime otherwise. + * + ****************************************************************************/ + +static void tc3xx_c_init(void) +{ +#ifdef CONFIG_TRICORE_TOOLCHAIN_TASKING + extern void _c_init(void); + + _c_init(); +#else + const uintptr_t *table; + uint8_t *src; + uint8_t *dst; + uint32_t len; + + for (table = __clear_table; ; table += 2) + { + dst = (uint8_t *)table[0]; + len = table[1]; + if (len == 0xffffffff) + { + break; + } + + while (len >= 8) + { + *(uint64_t *)dst = 0; + dst += 8; + len -= 8; + } + + while (len-- > 0) + { + *dst++ = 0; + } + } + + for (table = __copy_table; ; table += 3) + { + src = (uint8_t *)table[0]; + dst = (uint8_t *)table[1]; + len = table[2]; + if (len == 0xffffffff) + { + break; + } + + while (len >= 8) + { + *(uint64_t *)dst = *(uint64_t *)src; + dst += 8; + src += 8; + len -= 8; + } + + while (len-- > 0) + { + *dst++ = *src++; + } + } +#endif +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tricore_start + * + * Description: + * C entry of the startup, jumped to from _START in tricore_head with the + * stack and the small data pointers set. It does what the iLLD startup + * code did for CPU0: link the CSAs, set up the clocks after a power-on + * reset, initialize the C runtime with the watchdogs disabled, start + * CPU1, enable the caches, set BTV, BIV and ISP and enter core0_main. + * + ****************************************************************************/ + +void tricore_start(void) +{ + tc3xx_csa_init(__CSA0, __CSA0_END); + UP_ISB(); + + if (!tc3xx_application_reset()) + { + tc3xx_wdt_service(); + if (tricore_clockconfig() != 0) + { + __asm__ volatile ("debug"); + } + } + + tc3xx_wdt_set_disabled(true); + tc3xx_c_init(); + tc3xx_wdt_set_disabled(false); + +#ifndef CONFIG_TRICORE_BL + putreg32((getreg32(TC3XX_CPU1_PC) & 1) | ((uintptr_t)__START1 & ~1), + TC3XX_CPU1_PC); + if ((getreg32(TC3XX_CPU1_SYSCON) & TC3XX_SYSCON_BHALT) != 0) + { + putreg32(getreg32(TC3XX_CPU1_SYSCON) & ~TC3XX_SYSCON_BHALT, + TC3XX_CPU1_SYSCON); + } +#endif + + /* Caches on, trap and interrupt vectors, interrupt stack */ + + tc3xx_wdt_cpu_endinit(false); + tricore_mtcr(TRICORE_CPU_PCON0, 0); + UP_ISB(); + tricore_mtcr(TRICORE_CPU_DCON0, 0); + UP_ISB(); + tricore_mtcr(TRICORE_CPU_BTV, (uintptr_t)__TRAPTAB_CPU0); Review Comment: should in asm,.S ########## arch/tricore/src/tc4xx/tc4xx_start.c: ########## @@ -0,0 +1,472 @@ +/**************************************************************************** + * arch/tricore/src/tc4xx/tc4xx_start.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdbool.h> +#include <stdint.h> + +#include <arch/arch.h> + +#include "tricore_internal.h" +#include "hardware/tc4xx_clock.h" +#include "hardware/tc4xx_cpu.h" +#include "hardware/tc4xx_pms.h" +#include "hardware/tc4xx_smm.h" +#include "hardware/tc4xx_vmt.h" +#include "tc4xx_wdt.h" +#include "tricore_stm.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Watchdog reload values of the startup and of the application */ + +#define TC4XX_WDT_RELOAD_STARTUP 0xffc2 +#define TC4XX_WDT_RELOAD_APP 0xfffc + +/* Loop count before the crystal power-up gives up */ + +#define TC4XX_CCU_LCK_TIMEOUT 0x1000 + +/* STM of CPU0 */ + +#define TC4XX_STM0_ABS (TRICORE_STM0_BASE + TRICORE_STM_ABS_OFFSET) + +/* The BIV of the single interrupt vector at INTTAB + 0x1fe0 */ + +#define TC4XX_BIV_VECTOR 0x1fe0 + +/**************************************************************************** + * External Function Prototypes + ****************************************************************************/ + +void core0_main(void); + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Provided by the linker script */ + +extern uintptr_t __CSA0[]; +extern uintptr_t __CSA0_END[]; +extern uintptr_t __INTTAB_CPU0[]; +extern uintptr_t __ISTACK0[]; +extern uintptr_t __START1[]; +extern uintptr_t __START2[]; +extern uintptr_t __START3[]; +extern uintptr_t __START4[]; +extern uintptr_t __START5[]; + +#ifndef CONFIG_TRICORE_TOOLCHAIN_TASKING +extern const uintptr_t __clear_table[]; +extern const uintptr_t __copy_table[]; +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* MBIST selectors of the LMU and MCAN RAMs that are cleared */ + +static const uint8_t g_tc4xx_sram[] = +{ + 0x17, 0x18, 0x20, 0x21, 0x19, 0x1a, 0x1b, 0x22, 0x23, 0x24, /* LMU0-9 */ + 0xa2, 0xa3, 0xa4, 0xa5, 0xa6 /* MCAN0-4 */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tc4xx_csa_init + * + * Description: + * Link the CSAs from start to end into the free context list, with LCX + * at the third last. It runs before any function call is possible, so + * it must not call. + * + ****************************************************************************/ + +static inline_function void tc4xx_csa_init(uintptr_t *start, uintptr_t *end) +{ + uint32_t num = ((uintptr_t)end - (uintptr_t)start) / TC_CONTEXT_SIZE; + uintptr_t *prev = NULL; + uintptr_t *csa = start; + uint32_t link; + uint32_t k; + + for (k = 0; k < num; k++) + { + link = tricore_addr2csa(csa); + if (k == 0) + { + tricore_mtcr(TRICORE_CPU_FCX, link); + } + else + { + *prev = link; + } + + if (k == num - 3) + { + tricore_mtcr(TRICORE_CPU_LCX, link); + } + + prev = csa; + csa += TC_CONTEXT_REGS; + } + + *prev = 0; + UP_DSB(); +} + +/**************************************************************************** + * Name: tc4xx_c_init + * + * Description: + * Clear .bss and copy .data, from the tables of the linker script on + * GCC, with the TASKING runtime otherwise. + * + ****************************************************************************/ + +static void tc4xx_c_init(void) Review Comment: common code ########## arch/tricore/src/tc3xx/tc3xx_start.c: ########## @@ -0,0 +1,277 @@ +/**************************************************************************** + * arch/tricore/src/tc3xx/tc3xx_start.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdbool.h> +#include <stdint.h> + +#include <arch/arch.h> + +#include "tricore_internal.h" +#include "hardware/tc3xx_cpu.h" +#include "hardware/tc3xx_scu.h" +#include "tc3xx_wdt.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The BIV of the single interrupt vector at INTTAB + 0x1fe0 */ + +#define TC3XX_BIV_VECTOR 0x1fe0 + +/**************************************************************************** + * External Function Prototypes + ****************************************************************************/ + +void core0_main(void); + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Provided by the linker script */ + +extern uintptr_t __CSA0[]; +extern uintptr_t __CSA0_END[]; +extern uintptr_t __TRAPTAB_CPU0[]; +extern uintptr_t __INTTAB_CPU0[]; +extern uintptr_t __ISTACK0[]; +extern uintptr_t __START1[]; + +#ifndef CONFIG_TRICORE_TOOLCHAIN_TASKING +extern const uintptr_t __clear_table[]; +extern const uintptr_t __copy_table[]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tc3xx_csa_init + * + * Description: + * Link the CSAs from start to end into the free context list, with LCX + * at the third last. It runs before any function call is possible, so + * it must not call. + * + ****************************************************************************/ + +static inline_function void tc3xx_csa_init(uintptr_t *start, uintptr_t *end) +{ + uint32_t num = ((uintptr_t)end - (uintptr_t)start) / TC_CONTEXT_SIZE; + uintptr_t *prev = NULL; + uintptr_t *csa = start; + uint32_t link; + uint32_t k; + + for (k = 0; k < num; k++) + { + link = tricore_addr2csa(csa); + if (k == 0) + { + tricore_mtcr(TRICORE_CPU_FCX, link); + } + else + { + *prev = link; + } + + if (k == num - 3) + { + tricore_mtcr(TRICORE_CPU_LCX, link); + } + + prev = csa; + csa += TC_CONTEXT_REGS; + } + + *prev = 0; + UP_DSB(); +} + +/**************************************************************************** + * Name: tc3xx_application_reset + ****************************************************************************/ + +static bool tc3xx_application_reset(void) +{ + uint32_t rststat = getreg32(TC3XX_SCU_RSTSTAT); + uint32_t bit; + + if ((rststat & TC3XX_RSTSTAT_POWERON) != 0) + { + return false; + } + + if ((rststat & TC3XX_RSTSTAT_RESET) != 0) + { + rststat &= TC3XX_RSTSTAT_RESET; + for (bit = 31; (rststat & (1u << bit)) == 0; bit--); + + return ((getreg32(TC3XX_SCU_RSTCON) >> (bit << 1)) & 3) == + TC3XX_RSTCON_APPLICATION; + } + + if ((rststat & TC3XX_RSTSTAT_CB3) != 0) + { + return true; + } + + return (getreg32(TC3XX_CPU0_KRST0) & TC3XX_KRST0_RSTSTAT_MASK) != 0; +} + +/**************************************************************************** + * Name: tc3xx_c_init + * + * Description: + * Clear .bss and copy .data, from the tables of the linker script on + * GCC, with the TASKING runtime otherwise. + * + ****************************************************************************/ + +static void tc3xx_c_init(void) +{ +#ifdef CONFIG_TRICORE_TOOLCHAIN_TASKING + extern void _c_init(void); + + _c_init(); +#else + const uintptr_t *table; + uint8_t *src; + uint8_t *dst; + uint32_t len; + + for (table = __clear_table; ; table += 2) + { + dst = (uint8_t *)table[0]; + len = table[1]; + if (len == 0xffffffff) + { + break; + } + + while (len >= 8) + { + *(uint64_t *)dst = 0; + dst += 8; + len -= 8; + } + + while (len-- > 0) + { + *dst++ = 0; + } + } + + for (table = __copy_table; ; table += 3) + { + src = (uint8_t *)table[0]; + dst = (uint8_t *)table[1]; + len = table[2]; + if (len == 0xffffffff) + { + break; + } + + while (len >= 8) + { + *(uint64_t *)dst = *(uint64_t *)src; + dst += 8; + src += 8; + len -= 8; + } + + while (len-- > 0) + { + *dst++ = *src++; + } + } +#endif +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tricore_start + * + * Description: + * C entry of the startup, jumped to from _START in tricore_head with the + * stack and the small data pointers set. It does what the iLLD startup + * code did for CPU0: link the CSAs, set up the clocks after a power-on + * reset, initialize the C runtime with the watchdogs disabled, start + * CPU1, enable the caches, set BTV, BIV and ISP and enter core0_main. + * + ****************************************************************************/ + +void tricore_start(void) +{ + tc3xx_csa_init(__CSA0, __CSA0_END); + UP_ISB(); + + if (!tc3xx_application_reset()) + { + tc3xx_wdt_service(); + if (tricore_clockconfig() != 0) + { + __asm__ volatile ("debug"); + } + } + + tc3xx_wdt_set_disabled(true); + tc3xx_c_init(); + tc3xx_wdt_set_disabled(false); + +#ifndef CONFIG_TRICORE_BL Review Comment: CONFIG_TRICORE_BL not used in startup ########## arch/tricore/src/tc3xx/tc3xx_start.c: ########## @@ -0,0 +1,277 @@ +/**************************************************************************** + * arch/tricore/src/tc3xx/tc3xx_start.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdbool.h> +#include <stdint.h> + +#include <arch/arch.h> + +#include "tricore_internal.h" +#include "hardware/tc3xx_cpu.h" +#include "hardware/tc3xx_scu.h" +#include "tc3xx_wdt.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The BIV of the single interrupt vector at INTTAB + 0x1fe0 */ + +#define TC3XX_BIV_VECTOR 0x1fe0 + +/**************************************************************************** + * External Function Prototypes + ****************************************************************************/ + +void core0_main(void); + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Provided by the linker script */ + +extern uintptr_t __CSA0[]; +extern uintptr_t __CSA0_END[]; +extern uintptr_t __TRAPTAB_CPU0[]; +extern uintptr_t __INTTAB_CPU0[]; +extern uintptr_t __ISTACK0[]; +extern uintptr_t __START1[]; + +#ifndef CONFIG_TRICORE_TOOLCHAIN_TASKING +extern const uintptr_t __clear_table[]; +extern const uintptr_t __copy_table[]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tc3xx_csa_init + * + * Description: + * Link the CSAs from start to end into the free context list, with LCX + * at the third last. It runs before any function call is possible, so + * it must not call. + * + ****************************************************************************/ + +static inline_function void tc3xx_csa_init(uintptr_t *start, uintptr_t *end) +{ Review Comment: common code ########## arch/tricore/src/common/gnu/tricore_head.S: ########## @@ -0,0 +1,119 @@ +/**************************************************************************** + * arch/tricore/src/common/gnu/tricore_head.S + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Reset entry. _START only sets the stack and jumps on, as the linker + * script keeps .start to 0x20 bytes ahead of the interface constants. + * tricore_head then sets the small data base registers and the PSW and + * jumps to tricore_start, which links the CSAs before it calls anything. + * + * TC4xx first disables the virtualization with a call to a function that + * returns with rfh, using a boot stack and a single boot CSA in the PSPR, + * as the iLLD startup code does. + * + * tasking/tricore_head.asm is the same code in the TASKING syntax. + ****************************************************************************/ + +#include <nuttx/config.h> +#include <arch/csfr.h> + +#define TRICORE_PSW_RESET 0x980 /* Supervisor, call depth counting on */ + +#ifdef CONFIG_ARCH_CHIP_TC4XX +# define TC4XX_BOOT_SP 0x7010eb00 +# define TC4XX_PSW_VIRT 0xb00 /* PSW for disabling the virtualization */ +#endif + + .section .start, "ax", %progbits + .global _START + .type _START, %function +_START: +#ifdef CONFIG_ARCH_CHIP_TC4XX + movh.a %sp, hi:TC4XX_BOOT_SP + lea %sp, [%sp]lo:TC4XX_BOOT_SP +#else + movh.a %sp, hi:__USTACK0 + lea %sp, [%sp]lo:__USTACK0 +#endif + dsync + movh.a %a15, hi:tricore_head + lea %a15, [%a15]lo:tricore_head + ji %a15 + + .text + .type tricore_head, %function +tricore_head: Review Comment: where mbist ? ########## arch/tricore/src/tc4xx/tc4xx_start.c: ########## @@ -0,0 +1,472 @@ +/**************************************************************************** + * arch/tricore/src/tc4xx/tc4xx_start.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdbool.h> +#include <stdint.h> + +#include <arch/arch.h> + +#include "tricore_internal.h" +#include "hardware/tc4xx_clock.h" +#include "hardware/tc4xx_cpu.h" +#include "hardware/tc4xx_pms.h" +#include "hardware/tc4xx_smm.h" +#include "hardware/tc4xx_vmt.h" +#include "tc4xx_wdt.h" +#include "tricore_stm.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Watchdog reload values of the startup and of the application */ + +#define TC4XX_WDT_RELOAD_STARTUP 0xffc2 +#define TC4XX_WDT_RELOAD_APP 0xfffc + +/* Loop count before the crystal power-up gives up */ + +#define TC4XX_CCU_LCK_TIMEOUT 0x1000 + +/* STM of CPU0 */ + +#define TC4XX_STM0_ABS (TRICORE_STM0_BASE + TRICORE_STM_ABS_OFFSET) + +/* The BIV of the single interrupt vector at INTTAB + 0x1fe0 */ + +#define TC4XX_BIV_VECTOR 0x1fe0 + +/**************************************************************************** + * External Function Prototypes + ****************************************************************************/ + +void core0_main(void); + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Provided by the linker script */ + +extern uintptr_t __CSA0[]; +extern uintptr_t __CSA0_END[]; +extern uintptr_t __INTTAB_CPU0[]; +extern uintptr_t __ISTACK0[]; +extern uintptr_t __START1[]; +extern uintptr_t __START2[]; +extern uintptr_t __START3[]; +extern uintptr_t __START4[]; +extern uintptr_t __START5[]; + +#ifndef CONFIG_TRICORE_TOOLCHAIN_TASKING +extern const uintptr_t __clear_table[]; +extern const uintptr_t __copy_table[]; +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* MBIST selectors of the LMU and MCAN RAMs that are cleared */ + +static const uint8_t g_tc4xx_sram[] = +{ + 0x17, 0x18, 0x20, 0x21, 0x19, 0x1a, 0x1b, 0x22, 0x23, 0x24, /* LMU0-9 */ + 0xa2, 0xa3, 0xa4, 0xa5, 0xa6 /* MCAN0-4 */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tc4xx_csa_init + * + * Description: + * Link the CSAs from start to end into the free context list, with LCX + * at the third last. It runs before any function call is possible, so + * it must not call. + * + ****************************************************************************/ + +static inline_function void tc4xx_csa_init(uintptr_t *start, uintptr_t *end) +{ + uint32_t num = ((uintptr_t)end - (uintptr_t)start) / TC_CONTEXT_SIZE; + uintptr_t *prev = NULL; + uintptr_t *csa = start; + uint32_t link; + uint32_t k; + + for (k = 0; k < num; k++) + { + link = tricore_addr2csa(csa); + if (k == 0) + { + tricore_mtcr(TRICORE_CPU_FCX, link); + } + else + { + *prev = link; + } + + if (k == num - 3) + { + tricore_mtcr(TRICORE_CPU_LCX, link); + } + + prev = csa; + csa += TC_CONTEXT_REGS; + } + + *prev = 0; + UP_DSB(); +} + +/**************************************************************************** + * Name: tc4xx_c_init + * + * Description: + * Clear .bss and copy .data, from the tables of the linker script on + * GCC, with the TASKING runtime otherwise. + * + ****************************************************************************/ + +static void tc4xx_c_init(void) +{ +#ifdef CONFIG_TRICORE_TOOLCHAIN_TASKING + extern void _c_init(void); + + _c_init(); +#else + const uintptr_t *table; + uint8_t *src; + uint8_t *dst; + uint32_t len; + + for (table = __clear_table; ; table += 2) + { + dst = (uint8_t *)table[0]; + len = table[1]; + if (len == 0xffffffff) + { + break; + } + + while (len >= 8) + { + *(uint64_t *)dst = 0; + dst += 8; + len -= 8; + } + + while (len-- > 0) + { + *dst++ = 0; + } + } + + for (table = __copy_table; ; table += 3) + { + src = (uint8_t *)table[0]; + dst = (uint8_t *)table[1]; + len = table[2]; + if (len == 0xffffffff) + { + break; + } + + while (len >= 8) + { + *(uint64_t *)dst = *(uint64_t *)src; + dst += 8; + src += 8; + len -= 8; + } + + while (len-- > 0) + { + *dst++ = *src++; + } + } +#endif +} + +/**************************************************************************** + * Name: tc4xx_sram_clear + * + * Description: + * Clear an SRAM with its MBIST controller, as IfxVmt_clearSram does. + * + ****************************************************************************/ + +static void tc4xx_sram_clear(uint32_t sel) +{ + uintptr_t vmt = TC4XX_VMT_BASE + (sel >> 5) * TC4XX_VMT_SIZE; + uintptr_t mc = vmt + TC4XX_VMT_MC(sel % 32); + uint32_t mask = 1 << (sel % 32); + + if ((getreg32(vmt + TC4XX_VMT_CLC) & TC4XX_VMT_CLC_DISS) != 0) + { + putreg32(0, vmt + TC4XX_VMT_CLC); + } + + /* Enable the MBIST shell and start the clear */ + + putreg32(getreg32(mc + TC4XX_VMT_MC_ALMSRCS) & ~TC4XX_ALMSRCS_ALARMS, + mc + TC4XX_VMT_MC_ALMSRCS); + putreg32(getreg32(vmt + TC4XX_VMT_MEMTEST) | mask, + vmt + TC4XX_VMT_MEMTEST); + while ((getreg32(vmt + TC4XX_VMT_MEMSTAT) & mask) != 0); + + putreg32((1 << 15) | (1 << 0), mc + TC4XX_VMT_MC_MCONTROL); + putreg32(getreg32(mc + TC4XX_VMT_MC_MCONTROL) & ~(1 << 0), + mc + TC4XX_VMT_MC_MCONTROL); + while ((getreg32(vmt + TC4XX_VMT_MEMDONE) & mask) == 0); + + /* Read address 0 once, then disable the MBIST shell again */ + + putreg32(1 << 3, mc + TC4XX_VMT_MC_MCONTROL); + putreg32((1 << 12) | (1 << 0), mc + TC4XX_VMT_MC_CONFIG0); + putreg32(0, mc + TC4XX_VMT_MC_CONFIG1); + putreg32(0, mc + TC4XX_VMT_MC_RANGE); + putreg32((1 << 3) | (1 << 0), mc + TC4XX_VMT_MC_MCONTROL); + putreg32(1 << 3, mc + TC4XX_VMT_MC_MCONTROL); + while ((getreg32(vmt + TC4XX_VMT_MEMDONE) & mask) == 0); + + putreg32(getreg32(vmt + TC4XX_VMT_MEMTEST) & ~mask, + vmt + TC4XX_VMT_MEMTEST); + while ((getreg32(vmt + TC4XX_VMT_MEMSTAT) & mask) != 0); + putreg32(getreg32(mc + TC4XX_VMT_MC_ALMSRCS) | TC4XX_ALMSRCS_ALARMS, + mc + TC4XX_VMT_MC_ALMSRCS); +} + +/**************************************************************************** + * Name: tc4xx_osc_power_on + * + * Description: + * Power up the crystal oscillator in external crystal mode. + * + ****************************************************************************/ + +static void tc4xx_osc_power_on(void) +{ + uint32_t regval = getreg32(TC4XX_CLOCK_OSCCON) & ~TC4XX_OSCCON_MODE_MASK; + uint32_t count = TC4XX_CCU_LCK_TIMEOUT; + + while ((getreg32(TC4XX_CLOCK_CCUSTAT) & TC4XX_CCUSTAT_LCK) != 0) + { + if (--count == 0) + { + putreg32(regval, TC4XX_CLOCK_OSCCON); + __asm__ volatile ("debug"); + return; + } + } + + putreg32(regval, TC4XX_CLOCK_OSCCON); +} + +/**************************************************************************** + * Name: tc4xx_stm_frequency + * + * Description: + * STM frequency as the iLLD startup code computes it for its delays. + * + ****************************************************************************/ + +static uint32_t tc4xx_stm_frequency(void) +{ + uint32_t insel = (getreg32(TC4XX_CLOCK_OSCCON) & + TC4XX_OSCCON_INSEL_MASK) >> TC4XX_OSCCON_INSEL_SHIFT; + uint32_t clksels = getreg32(TC4XX_CLOCK_CCUSTAT) & TC4XX_CCU_CLKSELS_MASK; + uint32_t con0 = getreg32(TC4XX_CLOCK_SYSPLLCON0); + uint32_t stat = getreg32(TC4XX_CLOCK_RAMPSTAT); + uint32_t fstat = (stat & TC4XX_RAMPSTAT_FSTAT_MASK) >> + TC4XX_RAMPSTAT_FSTAT_SHIFT; + uint32_t osc; + uint32_t freq; + + osc = insel == 2 ? 20000000 : insel == 1 ? 25000000 : 100000000; + if (clksels == TC4XX_CCU_CLKSELS_PLL) + { + uint32_t ndiv = (con0 & TC4XX_PLLCON0_NDIV_MASK) >> + TC4XX_PLLCON0_NDIV_SHIFT; + uint32_t pdiv = (con0 & TC4XX_PLLCON0_PDIV_MASK) >> + TC4XX_PLLCON0_PDIV_SHIFT; + uint32_t k2div = getreg32(TC4XX_CLOCK_SYSPLLCON1) & + TC4XX_PLLCON1_K2DIV_MASK; + + freq = (uint32_t)((float)osc * (ndiv + 1) / + ((pdiv + 1) * (k2div + 1)) + 0.5f); + } + else if (clksels == TC4XX_CCU_CLKSELS_RAMP) + { + freq = 0; + if ((stat & TC4XX_RAMPSTAT_SSTAT_MASK) == 0) + { + if (fstat == 2) + { + freq = (getreg32(TC4XX_CLOCK_RAMPCON0) & + TC4XX_RAMPCON0_UFL_MASK) * 1000000; + } + else if (fstat == 1) + { + freq = 100000000; + } + } + } + else + { + freq = 100000000; + } + + return freq / ((getreg32(TC4XX_CLOCK_SYSCCUCON0) & + TC4XX_SYSCCUCON0_STMDIV_MASK) >> + TC4XX_SYSCCUCON0_STMDIV_SHIFT); +} + +/**************************************************************************** + * Name: tc4xx_delay + * + * Description: + * Wait 100 us on the STM between the starts of the cores. + * + ****************************************************************************/ + +static void tc4xx_delay(void) +{ + uint32_t ticks = tc4xx_stm_frequency() / 10000; + uint32_t start = getreg32(TC4XX_STM0_ABS); + + while (getreg32(TC4XX_STM0_ABS) - start < ticks); +} + +/**************************************************************************** + * Name: tc4xx_start_core + ****************************************************************************/ + +static void tc4xx_start_core(int cpu, uintptr_t pc) +{ + putreg32((getreg32(TC4XX_CPU_HRA_PC(cpu)) & 1) | (pc & ~1), + TC4XX_CPU_HRA_PC(cpu)); + if ((getreg32(TC4XX_CPU_HRA_BOOTCON(cpu)) & TC4XX_BOOTCON_BHALT) != 0) + { + putreg32(getreg32(TC4XX_CPU_HRA_BOOTCON(cpu)) & ~TC4XX_BOOTCON_BHALT, + TC4XX_CPU_HRA_BOOTCON(cpu)); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tricore_start + * + * Description: + * C entry of the startup, jumped to from _START in tricore_head after it + * has disabled the virtualization and set the stack and the small data + * pointers. It does what the iLLD startup code did for CPU0: link the + * CSAs, and after a power-on reset clear the LMU and MCAN RAMs and set + * up the crystal and the clocks; initialize the C runtime, start the + * other cores unless TRICORE_BL is set, enable the caches, set BIV and + * ISP and enter core0_main. An application reset with the key-off + * marker set stops, as the iLLD key-off path does without its tests. + * + ****************************************************************************/ + +void tricore_start(void) +{ + int i; + + tc4xx_csa_init(__CSA0, __CSA0_END); + UP_ISB(); + + tc4xx_wdt_service(); + + if ((getreg32(TC4XX_SMM_RSTSTATH) & TC4XX_RSTSTATH_APPRST) == 0) + { + tc4xx_wdt_service(); + tc4xx_wdt_reload(TC4XX_WDT_RELOAD_STARTUP); + + for (i = 0; i < sizeof(g_tc4xx_sram); i++) + { + tc4xx_sram_clear(g_tc4xx_sram[i]); + } + + tc4xx_c_init(); + + tc4xx_wdt_service(); + tc4xx_osc_power_on(); + if (tricore_clockconfig() != 0) + { + __asm__ volatile ("debug"); + } + } + else if ((getreg32(TC4XX_PMS_CLDPORSTUSRINFO) & 0xff) != 0) + { + tc4xx_wdt_reload(TC4XX_WDT_RELOAD_STARTUP); + putreg32(0, TC4XX_PMS_CLDPORSTUSRINFO); + for (; ; ); + } + else + { + tc4xx_c_init(); + } + + tc4xx_wdt_service(); + +#ifndef CONFIG_TRICORE_BL + tc4xx_start_core(1, (uintptr_t)__START1); + tc4xx_delay(); + tc4xx_start_core(2, (uintptr_t)__START2); + tc4xx_delay(); + tc4xx_start_core(3, (uintptr_t)__START3); + tc4xx_delay(); + tc4xx_start_core(4, (uintptr_t)__START4); + tc4xx_delay(); + tc4xx_start_core(5, (uintptr_t)__START5); +#endif + + /* Caches on, interrupt vector, interrupt stack */ + + tricore_mtcr(TRICORE_CPU_PCON0, 0); Review Comment: in asm ########## arch/tricore/src/common/tricore_irq.c: ########## @@ -225,23 +221,16 @@ void up_enable_irq(int irq) void up_affinity_irq(int irq, cpu_set_t cpuset) { - volatile Ifx_SRC_SRCR *src = &SRC_CPU_CPU0_SB + irq; - int irq_prio = src->B.SRPN; + volatile uint32_t *src = TRICORE_SRC(irq); - IfxSrc_disable(src); + *src &= ~TRICORE_SRC_SRE; /* Only support interrupt routing mode 0, * so routing to the first cpu in cpuset. */ -#ifdef CONFIG_ARCH_CHIP_TC3XX - IfxSrc_init(src, g_tricore_tos[ffs(cpuset) - 1], irq_prio); -#else - IfxSrc_init(src, g_tricore_tos[ffs(cpuset) - 1], irq_prio, - IfxSrc_VmId_none); -#endif - - IfxSrc_enable(src); + tricore_src_init(src, ffs(cpuset) - 1, *src & TRICORE_SRC_SRPN_MASK); Review Comment: https://github.com/apache/nuttx/pull/21511, Can we reach a consensus: you submit the interrupt/trap-related code, while I provide the boot-related code? For instance, you could take my interrupt/trap PR and make any necessary modifications; likewise, you are welcome to offer your feedback on our boot implementation. what we do is based on amp/bmp/smp mode and multcore ########## arch/tricore/src/tc4xx/tc4xx_start.c: ########## @@ -0,0 +1,472 @@ +/**************************************************************************** + * arch/tricore/src/tc4xx/tc4xx_start.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdbool.h> +#include <stdint.h> + +#include <arch/arch.h> + +#include "tricore_internal.h" +#include "hardware/tc4xx_clock.h" +#include "hardware/tc4xx_cpu.h" +#include "hardware/tc4xx_pms.h" +#include "hardware/tc4xx_smm.h" +#include "hardware/tc4xx_vmt.h" +#include "tc4xx_wdt.h" +#include "tricore_stm.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Watchdog reload values of the startup and of the application */ + +#define TC4XX_WDT_RELOAD_STARTUP 0xffc2 +#define TC4XX_WDT_RELOAD_APP 0xfffc + +/* Loop count before the crystal power-up gives up */ + +#define TC4XX_CCU_LCK_TIMEOUT 0x1000 + +/* STM of CPU0 */ + +#define TC4XX_STM0_ABS (TRICORE_STM0_BASE + TRICORE_STM_ABS_OFFSET) + +/* The BIV of the single interrupt vector at INTTAB + 0x1fe0 */ + +#define TC4XX_BIV_VECTOR 0x1fe0 + +/**************************************************************************** + * External Function Prototypes + ****************************************************************************/ + +void core0_main(void); + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Provided by the linker script */ + +extern uintptr_t __CSA0[]; +extern uintptr_t __CSA0_END[]; +extern uintptr_t __INTTAB_CPU0[]; +extern uintptr_t __ISTACK0[]; +extern uintptr_t __START1[]; +extern uintptr_t __START2[]; +extern uintptr_t __START3[]; +extern uintptr_t __START4[]; +extern uintptr_t __START5[]; + +#ifndef CONFIG_TRICORE_TOOLCHAIN_TASKING +extern const uintptr_t __clear_table[]; +extern const uintptr_t __copy_table[]; +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* MBIST selectors of the LMU and MCAN RAMs that are cleared */ + +static const uint8_t g_tc4xx_sram[] = +{ + 0x17, 0x18, 0x20, 0x21, 0x19, 0x1a, 0x1b, 0x22, 0x23, 0x24, /* LMU0-9 */ + 0xa2, 0xa3, 0xa4, 0xa5, 0xa6 /* MCAN0-4 */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tc4xx_csa_init + * + * Description: + * Link the CSAs from start to end into the free context list, with LCX + * at the third last. It runs before any function call is possible, so + * it must not call. + * + ****************************************************************************/ + +static inline_function void tc4xx_csa_init(uintptr_t *start, uintptr_t *end) +{ + uint32_t num = ((uintptr_t)end - (uintptr_t)start) / TC_CONTEXT_SIZE; + uintptr_t *prev = NULL; + uintptr_t *csa = start; + uint32_t link; + uint32_t k; + + for (k = 0; k < num; k++) + { + link = tricore_addr2csa(csa); + if (k == 0) + { + tricore_mtcr(TRICORE_CPU_FCX, link); + } + else + { + *prev = link; + } + + if (k == num - 3) + { + tricore_mtcr(TRICORE_CPU_LCX, link); + } + + prev = csa; + csa += TC_CONTEXT_REGS; + } + + *prev = 0; + UP_DSB(); +} + +/**************************************************************************** + * Name: tc4xx_c_init + * + * Description: + * Clear .bss and copy .data, from the tables of the linker script on + * GCC, with the TASKING runtime otherwise. + * + ****************************************************************************/ + +static void tc4xx_c_init(void) +{ +#ifdef CONFIG_TRICORE_TOOLCHAIN_TASKING + extern void _c_init(void); + + _c_init(); +#else + const uintptr_t *table; + uint8_t *src; + uint8_t *dst; + uint32_t len; + + for (table = __clear_table; ; table += 2) + { + dst = (uint8_t *)table[0]; + len = table[1]; + if (len == 0xffffffff) + { + break; + } + + while (len >= 8) + { + *(uint64_t *)dst = 0; + dst += 8; + len -= 8; + } + + while (len-- > 0) + { + *dst++ = 0; + } + } + + for (table = __copy_table; ; table += 3) + { + src = (uint8_t *)table[0]; + dst = (uint8_t *)table[1]; + len = table[2]; + if (len == 0xffffffff) + { + break; + } + + while (len >= 8) + { + *(uint64_t *)dst = *(uint64_t *)src; + dst += 8; + src += 8; + len -= 8; + } + + while (len-- > 0) + { + *dst++ = *src++; + } + } +#endif +} + +/**************************************************************************** + * Name: tc4xx_sram_clear + * + * Description: + * Clear an SRAM with its MBIST controller, as IfxVmt_clearSram does. + * + ****************************************************************************/ + +static void tc4xx_sram_clear(uint32_t sel) +{ + uintptr_t vmt = TC4XX_VMT_BASE + (sel >> 5) * TC4XX_VMT_SIZE; + uintptr_t mc = vmt + TC4XX_VMT_MC(sel % 32); + uint32_t mask = 1 << (sel % 32); + + if ((getreg32(vmt + TC4XX_VMT_CLC) & TC4XX_VMT_CLC_DISS) != 0) + { + putreg32(0, vmt + TC4XX_VMT_CLC); + } + + /* Enable the MBIST shell and start the clear */ + + putreg32(getreg32(mc + TC4XX_VMT_MC_ALMSRCS) & ~TC4XX_ALMSRCS_ALARMS, + mc + TC4XX_VMT_MC_ALMSRCS); + putreg32(getreg32(vmt + TC4XX_VMT_MEMTEST) | mask, + vmt + TC4XX_VMT_MEMTEST); + while ((getreg32(vmt + TC4XX_VMT_MEMSTAT) & mask) != 0); + + putreg32((1 << 15) | (1 << 0), mc + TC4XX_VMT_MC_MCONTROL); + putreg32(getreg32(mc + TC4XX_VMT_MC_MCONTROL) & ~(1 << 0), + mc + TC4XX_VMT_MC_MCONTROL); + while ((getreg32(vmt + TC4XX_VMT_MEMDONE) & mask) == 0); + + /* Read address 0 once, then disable the MBIST shell again */ + + putreg32(1 << 3, mc + TC4XX_VMT_MC_MCONTROL); + putreg32((1 << 12) | (1 << 0), mc + TC4XX_VMT_MC_CONFIG0); + putreg32(0, mc + TC4XX_VMT_MC_CONFIG1); + putreg32(0, mc + TC4XX_VMT_MC_RANGE); + putreg32((1 << 3) | (1 << 0), mc + TC4XX_VMT_MC_MCONTROL); + putreg32(1 << 3, mc + TC4XX_VMT_MC_MCONTROL); + while ((getreg32(vmt + TC4XX_VMT_MEMDONE) & mask) == 0); + + putreg32(getreg32(vmt + TC4XX_VMT_MEMTEST) & ~mask, + vmt + TC4XX_VMT_MEMTEST); + while ((getreg32(vmt + TC4XX_VMT_MEMSTAT) & mask) != 0); + putreg32(getreg32(mc + TC4XX_VMT_MC_ALMSRCS) | TC4XX_ALMSRCS_ALARMS, + mc + TC4XX_VMT_MC_ALMSRCS); +} + +/**************************************************************************** + * Name: tc4xx_osc_power_on + * + * Description: + * Power up the crystal oscillator in external crystal mode. + * + ****************************************************************************/ + +static void tc4xx_osc_power_on(void) +{ + uint32_t regval = getreg32(TC4XX_CLOCK_OSCCON) & ~TC4XX_OSCCON_MODE_MASK; + uint32_t count = TC4XX_CCU_LCK_TIMEOUT; + + while ((getreg32(TC4XX_CLOCK_CCUSTAT) & TC4XX_CCUSTAT_LCK) != 0) + { + if (--count == 0) + { + putreg32(regval, TC4XX_CLOCK_OSCCON); + __asm__ volatile ("debug"); + return; + } + } + + putreg32(regval, TC4XX_CLOCK_OSCCON); +} + +/**************************************************************************** + * Name: tc4xx_stm_frequency + * + * Description: + * STM frequency as the iLLD startup code computes it for its delays. + * + ****************************************************************************/ + +static uint32_t tc4xx_stm_frequency(void) Review Comment: startup code should only start code ########## arch/tricore/src/common/tasking/tricore_head.asm: ########## @@ -0,0 +1,109 @@ +;**************************************************************************** +; arch/tricore/src/common/tasking/tricore_head.asm +; +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed to the Apache Software Foundation (ASF) under one or more +; contributor license agreements. See the NOTICE file distributed with +; this work for additional information regarding copyright ownership. The +; ASF licenses this file to you under the Apache License, Version 2.0 (the +; "License"); you may not use this file except in compliance with the +; License. You may obtain a copy of the License at +; +; http://www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +; License for the specific language governing permissions and limitations +; under the License. +; +;**************************************************************************** +; +; TASKING (astc) version of gnu/tricore_head.S, same code; see there for the +; description. astc does not run the C preprocessor, so the CSFR offsets +; (arch/csfr.h) are written out, and TRICORE_TC4XX is set by the build. +; +;**************************************************************************** + + .extern tricore_start + .extern __USTACK0 + .extern __A0_MEM + .extern __A1_MEM + .extern __A8_MEM + .extern __A9_MEM + .extern __TRAPTAB_CPU0 + + .sdecl ".text.start",code,protect + .sect ".text.start" + .global _START +_START: Review Comment: public function ,follow nuttx style ########## arch/tricore/src/tc4xx/tc4xx_start.c: ########## @@ -0,0 +1,472 @@ +/**************************************************************************** + * arch/tricore/src/tc4xx/tc4xx_start.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdbool.h> +#include <stdint.h> + +#include <arch/arch.h> + +#include "tricore_internal.h" +#include "hardware/tc4xx_clock.h" +#include "hardware/tc4xx_cpu.h" +#include "hardware/tc4xx_pms.h" +#include "hardware/tc4xx_smm.h" +#include "hardware/tc4xx_vmt.h" +#include "tc4xx_wdt.h" +#include "tricore_stm.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Watchdog reload values of the startup and of the application */ + +#define TC4XX_WDT_RELOAD_STARTUP 0xffc2 +#define TC4XX_WDT_RELOAD_APP 0xfffc + +/* Loop count before the crystal power-up gives up */ + +#define TC4XX_CCU_LCK_TIMEOUT 0x1000 + +/* STM of CPU0 */ + +#define TC4XX_STM0_ABS (TRICORE_STM0_BASE + TRICORE_STM_ABS_OFFSET) + +/* The BIV of the single interrupt vector at INTTAB + 0x1fe0 */ + +#define TC4XX_BIV_VECTOR 0x1fe0 + +/**************************************************************************** + * External Function Prototypes + ****************************************************************************/ + +void core0_main(void); + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Provided by the linker script */ + +extern uintptr_t __CSA0[]; +extern uintptr_t __CSA0_END[]; +extern uintptr_t __INTTAB_CPU0[]; +extern uintptr_t __ISTACK0[]; +extern uintptr_t __START1[]; +extern uintptr_t __START2[]; +extern uintptr_t __START3[]; +extern uintptr_t __START4[]; +extern uintptr_t __START5[]; + +#ifndef CONFIG_TRICORE_TOOLCHAIN_TASKING +extern const uintptr_t __clear_table[]; +extern const uintptr_t __copy_table[]; +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* MBIST selectors of the LMU and MCAN RAMs that are cleared */ + +static const uint8_t g_tc4xx_sram[] = +{ + 0x17, 0x18, 0x20, 0x21, 0x19, 0x1a, 0x1b, 0x22, 0x23, 0x24, /* LMU0-9 */ + 0xa2, 0xa3, 0xa4, 0xa5, 0xa6 /* MCAN0-4 */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tc4xx_csa_init + * + * Description: + * Link the CSAs from start to end into the free context list, with LCX + * at the third last. It runs before any function call is possible, so + * it must not call. + * + ****************************************************************************/ + +static inline_function void tc4xx_csa_init(uintptr_t *start, uintptr_t *end) +{ + uint32_t num = ((uintptr_t)end - (uintptr_t)start) / TC_CONTEXT_SIZE; + uintptr_t *prev = NULL; + uintptr_t *csa = start; + uint32_t link; + uint32_t k; + + for (k = 0; k < num; k++) + { + link = tricore_addr2csa(csa); + if (k == 0) + { + tricore_mtcr(TRICORE_CPU_FCX, link); + } + else + { + *prev = link; + } + + if (k == num - 3) + { + tricore_mtcr(TRICORE_CPU_LCX, link); + } + + prev = csa; + csa += TC_CONTEXT_REGS; + } + + *prev = 0; + UP_DSB(); +} + +/**************************************************************************** + * Name: tc4xx_c_init + * + * Description: + * Clear .bss and copy .data, from the tables of the linker script on + * GCC, with the TASKING runtime otherwise. + * + ****************************************************************************/ + +static void tc4xx_c_init(void) +{ +#ifdef CONFIG_TRICORE_TOOLCHAIN_TASKING + extern void _c_init(void); + + _c_init(); +#else + const uintptr_t *table; + uint8_t *src; + uint8_t *dst; + uint32_t len; + + for (table = __clear_table; ; table += 2) + { + dst = (uint8_t *)table[0]; + len = table[1]; + if (len == 0xffffffff) + { + break; + } + + while (len >= 8) + { + *(uint64_t *)dst = 0; + dst += 8; + len -= 8; + } + + while (len-- > 0) + { + *dst++ = 0; + } + } + + for (table = __copy_table; ; table += 3) + { + src = (uint8_t *)table[0]; + dst = (uint8_t *)table[1]; + len = table[2]; + if (len == 0xffffffff) + { + break; + } + + while (len >= 8) + { + *(uint64_t *)dst = *(uint64_t *)src; + dst += 8; + src += 8; + len -= 8; + } + + while (len-- > 0) + { + *dst++ = *src++; + } + } +#endif +} + +/**************************************************************************** + * Name: tc4xx_sram_clear + * + * Description: + * Clear an SRAM with its MBIST controller, as IfxVmt_clearSram does. + * + ****************************************************************************/ + +static void tc4xx_sram_clear(uint32_t sel) +{ + uintptr_t vmt = TC4XX_VMT_BASE + (sel >> 5) * TC4XX_VMT_SIZE; + uintptr_t mc = vmt + TC4XX_VMT_MC(sel % 32); + uint32_t mask = 1 << (sel % 32); + + if ((getreg32(vmt + TC4XX_VMT_CLC) & TC4XX_VMT_CLC_DISS) != 0) + { + putreg32(0, vmt + TC4XX_VMT_CLC); + } + + /* Enable the MBIST shell and start the clear */ + + putreg32(getreg32(mc + TC4XX_VMT_MC_ALMSRCS) & ~TC4XX_ALMSRCS_ALARMS, + mc + TC4XX_VMT_MC_ALMSRCS); + putreg32(getreg32(vmt + TC4XX_VMT_MEMTEST) | mask, + vmt + TC4XX_VMT_MEMTEST); + while ((getreg32(vmt + TC4XX_VMT_MEMSTAT) & mask) != 0); + + putreg32((1 << 15) | (1 << 0), mc + TC4XX_VMT_MC_MCONTROL); + putreg32(getreg32(mc + TC4XX_VMT_MC_MCONTROL) & ~(1 << 0), + mc + TC4XX_VMT_MC_MCONTROL); + while ((getreg32(vmt + TC4XX_VMT_MEMDONE) & mask) == 0); + + /* Read address 0 once, then disable the MBIST shell again */ + + putreg32(1 << 3, mc + TC4XX_VMT_MC_MCONTROL); + putreg32((1 << 12) | (1 << 0), mc + TC4XX_VMT_MC_CONFIG0); + putreg32(0, mc + TC4XX_VMT_MC_CONFIG1); + putreg32(0, mc + TC4XX_VMT_MC_RANGE); + putreg32((1 << 3) | (1 << 0), mc + TC4XX_VMT_MC_MCONTROL); + putreg32(1 << 3, mc + TC4XX_VMT_MC_MCONTROL); + while ((getreg32(vmt + TC4XX_VMT_MEMDONE) & mask) == 0); + + putreg32(getreg32(vmt + TC4XX_VMT_MEMTEST) & ~mask, + vmt + TC4XX_VMT_MEMTEST); + while ((getreg32(vmt + TC4XX_VMT_MEMSTAT) & mask) != 0); + putreg32(getreg32(mc + TC4XX_VMT_MC_ALMSRCS) | TC4XX_ALMSRCS_ALARMS, + mc + TC4XX_VMT_MC_ALMSRCS); +} + +/**************************************************************************** + * Name: tc4xx_osc_power_on + * + * Description: + * Power up the crystal oscillator in external crystal mode. + * + ****************************************************************************/ + +static void tc4xx_osc_power_on(void) +{ + uint32_t regval = getreg32(TC4XX_CLOCK_OSCCON) & ~TC4XX_OSCCON_MODE_MASK; + uint32_t count = TC4XX_CCU_LCK_TIMEOUT; + + while ((getreg32(TC4XX_CLOCK_CCUSTAT) & TC4XX_CCUSTAT_LCK) != 0) + { + if (--count == 0) + { + putreg32(regval, TC4XX_CLOCK_OSCCON); + __asm__ volatile ("debug"); + return; + } + } + + putreg32(regval, TC4XX_CLOCK_OSCCON); +} + +/**************************************************************************** + * Name: tc4xx_stm_frequency + * + * Description: + * STM frequency as the iLLD startup code computes it for its delays. + * + ****************************************************************************/ + +static uint32_t tc4xx_stm_frequency(void) +{ + uint32_t insel = (getreg32(TC4XX_CLOCK_OSCCON) & + TC4XX_OSCCON_INSEL_MASK) >> TC4XX_OSCCON_INSEL_SHIFT; + uint32_t clksels = getreg32(TC4XX_CLOCK_CCUSTAT) & TC4XX_CCU_CLKSELS_MASK; + uint32_t con0 = getreg32(TC4XX_CLOCK_SYSPLLCON0); + uint32_t stat = getreg32(TC4XX_CLOCK_RAMPSTAT); + uint32_t fstat = (stat & TC4XX_RAMPSTAT_FSTAT_MASK) >> + TC4XX_RAMPSTAT_FSTAT_SHIFT; + uint32_t osc; + uint32_t freq; + + osc = insel == 2 ? 20000000 : insel == 1 ? 25000000 : 100000000; + if (clksels == TC4XX_CCU_CLKSELS_PLL) + { + uint32_t ndiv = (con0 & TC4XX_PLLCON0_NDIV_MASK) >> + TC4XX_PLLCON0_NDIV_SHIFT; + uint32_t pdiv = (con0 & TC4XX_PLLCON0_PDIV_MASK) >> + TC4XX_PLLCON0_PDIV_SHIFT; + uint32_t k2div = getreg32(TC4XX_CLOCK_SYSPLLCON1) & + TC4XX_PLLCON1_K2DIV_MASK; + + freq = (uint32_t)((float)osc * (ndiv + 1) / + ((pdiv + 1) * (k2div + 1)) + 0.5f); + } + else if (clksels == TC4XX_CCU_CLKSELS_RAMP) + { + freq = 0; + if ((stat & TC4XX_RAMPSTAT_SSTAT_MASK) == 0) + { + if (fstat == 2) + { + freq = (getreg32(TC4XX_CLOCK_RAMPCON0) & + TC4XX_RAMPCON0_UFL_MASK) * 1000000; + } + else if (fstat == 1) + { + freq = 100000000; + } + } + } + else + { + freq = 100000000; + } + + return freq / ((getreg32(TC4XX_CLOCK_SYSCCUCON0) & + TC4XX_SYSCCUCON0_STMDIV_MASK) >> + TC4XX_SYSCCUCON0_STMDIV_SHIFT); +} + +/**************************************************************************** + * Name: tc4xx_delay + * + * Description: + * Wait 100 us on the STM between the starts of the cores. + * + ****************************************************************************/ + +static void tc4xx_delay(void) +{ + uint32_t ticks = tc4xx_stm_frequency() / 10000; + uint32_t start = getreg32(TC4XX_STM0_ABS); + + while (getreg32(TC4XX_STM0_ABS) - start < ticks); +} + +/**************************************************************************** + * Name: tc4xx_start_core + ****************************************************************************/ + +static void tc4xx_start_core(int cpu, uintptr_t pc) +{ + putreg32((getreg32(TC4XX_CPU_HRA_PC(cpu)) & 1) | (pc & ~1), + TC4XX_CPU_HRA_PC(cpu)); + if ((getreg32(TC4XX_CPU_HRA_BOOTCON(cpu)) & TC4XX_BOOTCON_BHALT) != 0) + { + putreg32(getreg32(TC4XX_CPU_HRA_BOOTCON(cpu)) & ~TC4XX_BOOTCON_BHALT, + TC4XX_CPU_HRA_BOOTCON(cpu)); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tricore_start + * + * Description: + * C entry of the startup, jumped to from _START in tricore_head after it + * has disabled the virtualization and set the stack and the small data + * pointers. It does what the iLLD startup code did for CPU0: link the + * CSAs, and after a power-on reset clear the LMU and MCAN RAMs and set + * up the crystal and the clocks; initialize the C runtime, start the + * other cores unless TRICORE_BL is set, enable the caches, set BIV and + * ISP and enter core0_main. An application reset with the key-off + * marker set stops, as the iLLD key-off path does without its tests. + * + ****************************************************************************/ + +void tricore_start(void) +{ + int i; + + tc4xx_csa_init(__CSA0, __CSA0_END); + UP_ISB(); + + tc4xx_wdt_service(); + + if ((getreg32(TC4XX_SMM_RSTSTATH) & TC4XX_RSTSTATH_APPRST) == 0) + { + tc4xx_wdt_service(); + tc4xx_wdt_reload(TC4XX_WDT_RELOAD_STARTUP); + + for (i = 0; i < sizeof(g_tc4xx_sram); i++) + { + tc4xx_sram_clear(g_tc4xx_sram[i]); + } + + tc4xx_c_init(); + + tc4xx_wdt_service(); + tc4xx_osc_power_on(); + if (tricore_clockconfig() != 0) + { + __asm__ volatile ("debug"); + } + } + else if ((getreg32(TC4XX_PMS_CLDPORSTUSRINFO) & 0xff) != 0) + { + tc4xx_wdt_reload(TC4XX_WDT_RELOAD_STARTUP); + putreg32(0, TC4XX_PMS_CLDPORSTUSRINFO); + for (; ; ); + } + else + { + tc4xx_c_init(); + } + + tc4xx_wdt_service(); + +#ifndef CONFIG_TRICORE_BL + tc4xx_start_core(1, (uintptr_t)__START1); Review Comment: __start , one name ########## arch/tricore/src/tc4xx/tc4xx_start.c: ########## @@ -0,0 +1,472 @@ +/**************************************************************************** + * arch/tricore/src/tc4xx/tc4xx_start.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdbool.h> +#include <stdint.h> + +#include <arch/arch.h> + +#include "tricore_internal.h" +#include "hardware/tc4xx_clock.h" +#include "hardware/tc4xx_cpu.h" +#include "hardware/tc4xx_pms.h" +#include "hardware/tc4xx_smm.h" +#include "hardware/tc4xx_vmt.h" +#include "tc4xx_wdt.h" +#include "tricore_stm.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Watchdog reload values of the startup and of the application */ + +#define TC4XX_WDT_RELOAD_STARTUP 0xffc2 +#define TC4XX_WDT_RELOAD_APP 0xfffc + +/* Loop count before the crystal power-up gives up */ + +#define TC4XX_CCU_LCK_TIMEOUT 0x1000 + +/* STM of CPU0 */ + +#define TC4XX_STM0_ABS (TRICORE_STM0_BASE + TRICORE_STM_ABS_OFFSET) + +/* The BIV of the single interrupt vector at INTTAB + 0x1fe0 */ + +#define TC4XX_BIV_VECTOR 0x1fe0 Review Comment: common code ########## arch/tricore/src/common/tricore_irq.c: ########## @@ -225,23 +221,16 @@ void up_enable_irq(int irq) void up_affinity_irq(int irq, cpu_set_t cpuset) { - volatile Ifx_SRC_SRCR *src = &SRC_CPU_CPU0_SB + irq; - int irq_prio = src->B.SRPN; + volatile uint32_t *src = TRICORE_SRC(irq); - IfxSrc_disable(src); + *src &= ~TRICORE_SRC_SRE; /* Only support interrupt routing mode 0, * so routing to the first cpu in cpuset. */ -#ifdef CONFIG_ARCH_CHIP_TC3XX - IfxSrc_init(src, g_tricore_tos[ffs(cpuset) - 1], irq_prio); -#else - IfxSrc_init(src, g_tricore_tos[ffs(cpuset) - 1], irq_prio, - IfxSrc_VmId_none); -#endif - - IfxSrc_enable(src); + tricore_src_init(src, ffs(cpuset) - 1, *src & TRICORE_SRC_SRPN_MASK); Review Comment: wrong ########## arch/tricore/src/common/tricore_main.c: ########## @@ -24,25 +24,89 @@ * Included Files ****************************************************************************/ -#include <tricore_internal.h> +#include <nuttx/config.h> + +#include <stdint.h> + #include <nuttx/init.h> -#include "Ifx_Types.h" -#include "IfxCpu.h" +#include <arch/arch.h> + +#include "tricore_internal.h" +#include "tricore_stm.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Startup core synchronization: core ID bits to wait for and the timeout + * in STM ticks (0: no timeout) + */ + +#ifdef CONFIG_ARCH_CHIP_TC3XX +# define TRICORE_CORE_SYNC_MASK 0x5f +# define TRICORE_CORE_SYNC_TIMEOUT 100000 +#else +# define TRICORE_CORE_SYNC_MASK 0x01 +# define TRICORE_CORE_SYNC_TIMEOUT 0 +#endif -#ifdef CONFIG_ARCH_CHIP_TC4XX -# include "IfxWtu.h" +/* Core index from CORE_ID; CPU5 has the core ID 6 on TC39x */ + +#ifdef CONFIG_ARCH_CHIP_TC3XX +# define tricore_core_id() tricore_mfcr(TRICORE_CPU_CORE_ID) Review Comment: up_cpu_index ########## arch/tricore/src/tc4xx/tc4xx_start.c: ########## @@ -0,0 +1,472 @@ +/**************************************************************************** + * arch/tricore/src/tc4xx/tc4xx_start.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdbool.h> +#include <stdint.h> + +#include <arch/arch.h> + +#include "tricore_internal.h" +#include "hardware/tc4xx_clock.h" +#include "hardware/tc4xx_cpu.h" +#include "hardware/tc4xx_pms.h" +#include "hardware/tc4xx_smm.h" +#include "hardware/tc4xx_vmt.h" +#include "tc4xx_wdt.h" +#include "tricore_stm.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Watchdog reload values of the startup and of the application */ + +#define TC4XX_WDT_RELOAD_STARTUP 0xffc2 +#define TC4XX_WDT_RELOAD_APP 0xfffc + +/* Loop count before the crystal power-up gives up */ + +#define TC4XX_CCU_LCK_TIMEOUT 0x1000 + +/* STM of CPU0 */ + +#define TC4XX_STM0_ABS (TRICORE_STM0_BASE + TRICORE_STM_ABS_OFFSET) + +/* The BIV of the single interrupt vector at INTTAB + 0x1fe0 */ + +#define TC4XX_BIV_VECTOR 0x1fe0 + +/**************************************************************************** + * External Function Prototypes + ****************************************************************************/ + +void core0_main(void); + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Provided by the linker script */ + +extern uintptr_t __CSA0[]; +extern uintptr_t __CSA0_END[]; +extern uintptr_t __INTTAB_CPU0[]; +extern uintptr_t __ISTACK0[]; +extern uintptr_t __START1[]; +extern uintptr_t __START2[]; +extern uintptr_t __START3[]; +extern uintptr_t __START4[]; +extern uintptr_t __START5[]; + +#ifndef CONFIG_TRICORE_TOOLCHAIN_TASKING +extern const uintptr_t __clear_table[]; +extern const uintptr_t __copy_table[]; +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* MBIST selectors of the LMU and MCAN RAMs that are cleared */ + +static const uint8_t g_tc4xx_sram[] = +{ + 0x17, 0x18, 0x20, 0x21, 0x19, 0x1a, 0x1b, 0x22, 0x23, 0x24, /* LMU0-9 */ + 0xa2, 0xa3, 0xa4, 0xa5, 0xa6 /* MCAN0-4 */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tc4xx_csa_init + * + * Description: + * Link the CSAs from start to end into the free context list, with LCX + * at the third last. It runs before any function call is possible, so + * it must not call. + * + ****************************************************************************/ + +static inline_function void tc4xx_csa_init(uintptr_t *start, uintptr_t *end) +{ Review Comment: common code ########## arch/tricore/src/tc3xx/tc3xx_start.c: ########## @@ -0,0 +1,277 @@ +/**************************************************************************** + * arch/tricore/src/tc3xx/tc3xx_start.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdbool.h> +#include <stdint.h> + +#include <arch/arch.h> + +#include "tricore_internal.h" +#include "hardware/tc3xx_cpu.h" +#include "hardware/tc3xx_scu.h" +#include "tc3xx_wdt.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The BIV of the single interrupt vector at INTTAB + 0x1fe0 */ + +#define TC3XX_BIV_VECTOR 0x1fe0 + +/**************************************************************************** + * External Function Prototypes + ****************************************************************************/ + +void core0_main(void); + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Provided by the linker script */ + +extern uintptr_t __CSA0[]; +extern uintptr_t __CSA0_END[]; +extern uintptr_t __TRAPTAB_CPU0[]; +extern uintptr_t __INTTAB_CPU0[]; +extern uintptr_t __ISTACK0[]; +extern uintptr_t __START1[]; + +#ifndef CONFIG_TRICORE_TOOLCHAIN_TASKING +extern const uintptr_t __clear_table[]; +extern const uintptr_t __copy_table[]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tc3xx_csa_init + * + * Description: + * Link the CSAs from start to end into the free context list, with LCX + * at the third last. It runs before any function call is possible, so + * it must not call. + * + ****************************************************************************/ + +static inline_function void tc3xx_csa_init(uintptr_t *start, uintptr_t *end) +{ + uint32_t num = ((uintptr_t)end - (uintptr_t)start) / TC_CONTEXT_SIZE; + uintptr_t *prev = NULL; + uintptr_t *csa = start; + uint32_t link; + uint32_t k; + + for (k = 0; k < num; k++) + { + link = tricore_addr2csa(csa); + if (k == 0) + { + tricore_mtcr(TRICORE_CPU_FCX, link); + } + else + { + *prev = link; + } + + if (k == num - 3) + { + tricore_mtcr(TRICORE_CPU_LCX, link); + } + + prev = csa; + csa += TC_CONTEXT_REGS; + } + + *prev = 0; + UP_DSB(); +} + +/**************************************************************************** + * Name: tc3xx_application_reset + ****************************************************************************/ + +static bool tc3xx_application_reset(void) +{ + uint32_t rststat = getreg32(TC3XX_SCU_RSTSTAT); + uint32_t bit; + + if ((rststat & TC3XX_RSTSTAT_POWERON) != 0) + { + return false; + } + + if ((rststat & TC3XX_RSTSTAT_RESET) != 0) + { + rststat &= TC3XX_RSTSTAT_RESET; + for (bit = 31; (rststat & (1u << bit)) == 0; bit--); + + return ((getreg32(TC3XX_SCU_RSTCON) >> (bit << 1)) & 3) == + TC3XX_RSTCON_APPLICATION; + } + + if ((rststat & TC3XX_RSTSTAT_CB3) != 0) + { + return true; + } + + return (getreg32(TC3XX_CPU0_KRST0) & TC3XX_KRST0_RSTSTAT_MASK) != 0; +} + +/**************************************************************************** + * Name: tc3xx_c_init + * + * Description: + * Clear .bss and copy .data, from the tables of the linker script on + * GCC, with the TASKING runtime otherwise. + * + ****************************************************************************/ + +static void tc3xx_c_init(void) Review Comment: common way, not in tc3xx/4xx ########## arch/tricore/src/common/tasking/tricore_head.asm: ########## @@ -0,0 +1,109 @@ +;**************************************************************************** +; arch/tricore/src/common/tasking/tricore_head.asm +; +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed to the Apache Software Foundation (ASF) under one or more +; contributor license agreements. See the NOTICE file distributed with +; this work for additional information regarding copyright ownership. The +; ASF licenses this file to you under the Apache License, Version 2.0 (the +; "License"); you may not use this file except in compliance with the +; License. You may obtain a copy of the License at +; +; http://www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +; License for the specific language governing permissions and limitations +; under the License. +; +;**************************************************************************** +; +; TASKING (astc) version of gnu/tricore_head.S, same code; see there for the +; description. astc does not run the C preprocessor, so the CSFR offsets +; (arch/csfr.h) are written out, and TRICORE_TC4XX is set by the build. +; +;**************************************************************************** + + .extern tricore_start + .extern __USTACK0 + .extern __A0_MEM + .extern __A1_MEM + .extern __A8_MEM + .extern __A9_MEM + .extern __TRAPTAB_CPU0 + + .sdecl ".text.start",code,protect + .sect ".text.start" + .global _START +_START: + .if @DEF('TRICORE_TC4XX') + movh.a a10, #@HIS(0x7010eb00) + lea a10, [a10]@LOS(0x7010eb00) Review Comment: apart from grammatical differences ,your asm should be strictly consistent with gcc -- This is an automated message from the Apache Git Service. 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