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xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
The following commit(s) were added to refs/heads/master by this push:
new 1b1ac6f3b7 Fix nuttx coding style
1b1ac6f3b7 is described below
commit 1b1ac6f3b7fe9349c0a83007d3e8958e97597c87
Author: simbit18 <[email protected]>
AuthorDate: Thu Jul 13 09:52:33 2023 +0200
Fix nuttx coding style
Remove TABs
Fix indentation
Fix Multi-line comments
Fix Comments to the Right of Statements.
Fix nuttx coding style
Fix Comments to the Right of Statements.
---
arch/arm/include/cxd56xx/pm.h | 44 +-
arch/arm/src/rtl8720c/amebaz_coex.h | 8 +-
arch/arm/src/s32k3xx/hardware/s32k3xx_dmamux.h | 4 +-
arch/arm/src/samd5e5/sam_usb.c | 109 ++--
arch/arm/src/samd5e5/sam_wdt.c | 2 +-
arch/arm/src/stm32/stm32_waste.h | 16 +-
arch/arm/src/stm32f7/stm32_waste.h | 16 +-
arch/risc-v/src/esp32c3/hardware/esp32c3_saradc.h | 172 +++---
.../src/esp32c3/hardware/esp32c3_usb_serial_jtag.h | 78 +--
arch/sparc/include/sparc_v8/irq.h | 171 +++---
arch/sparc/src/bm3803/bm3803-uart.h | 34 +-
arch/sparc/src/s698pm/s698pm-uart.h | 4 +-
arch/xtensa/src/esp32/esp32_spi_slave.c | 4 +-
arch/xtensa/src/esp32s3/esp32s3_psram_octal.c | 48 +-
.../src/esp32s3/hardware/esp32s3_usb_serial_jtag.h | 76 +--
.../arm/stm32/nucleo-l152re/src/stm32_ili93418b.c | 12 +-
drivers/audio/wm8994.c | 2 +-
drivers/audio/wm8994.h | 642 +++++++--------------
drivers/sensors/fxos8700cq.c | 4 +-
drivers/wireless/ISM2_905MHzGFSK250kbps.c | 2 +-
drivers/wireless/ieee80211/bcm43xxx/bcmf_ioctl.h | 6 +-
include/nuttx/video/video_controls.h | 4 +-
22 files changed, 597 insertions(+), 861 deletions(-)
diff --git a/arch/arm/include/cxd56xx/pm.h b/arch/arm/include/cxd56xx/pm.h
index 5689b2a683..133ade841f 100644
--- a/arch/arm/include/cxd56xx/pm.h
+++ b/arch/arm/include/cxd56xx/pm.h
@@ -34,26 +34,26 @@
/* Boot Cause definitions */
-#define PM_BOOT_POR_NORMAL (0x00000000ul) /** Power On Reset like as
battery attached */
-#define PM_BOOT_POR_DEADBATT (0x00000001ul) /** Battery charged from
DeadBattery state */
-#define PM_BOOT_WDT_REBOOT (0x00000002ul) /** System WDT expired or
Explicitly Self Reboot */
-#define PM_BOOT_WDT_RESET (0x00000004ul) /** Chip WDT expired (might be
used in HV-only system) */
-#define PM_BOOT_DEEP_WKUPL (0x00000008ul) /** In DeepSleep state,
Detected WKUPL signal */
-#define PM_BOOT_DEEP_WKUPS (0x00000010ul) /** In DeepSleep state,
Detected WKUPS signal */
-#define PM_BOOT_DEEP_RTC (0x00000020ul) /** In DeepSleep state, RTC
Alarm expired */
-#define PM_BOOT_DEEP_USB_ATTACH (0x00000040ul) /** In DeepSleep state, USB
Connected */
-#define PM_BOOT_DEEP_OTHERS (0x00000080ul) /** In DeepSleep state,
Reserved others cause occurred */
-#define PM_BOOT_COLD_SCU_INT (0x00000100ul) /** In ColdSleep state,
Detected SCU Interrupt */
-#define PM_BOOT_COLD_RTC (0x00001e00ul) /** In ColdSleep state, RTC
Alarm Interrupt */
-#define PM_BOOT_COLD_RTC_ALM0 (0x00000200ul) /** In ColdSleep state, RTC
Alarm0 expired */
-#define PM_BOOT_COLD_RTC_ALM1 (0x00000400ul) /** In ColdSleep state, RTC
Alarm1 expired */
-#define PM_BOOT_COLD_RTC_ALM2 (0x00000800ul) /** In ColdSleep state, RTC
Alarm2 expired */
-#define PM_BOOT_COLD_RTC_ALMERR (0x00001000ul) /** In ColdSleep state, RTC
Alarm Error occurred */
-#define PM_BOOT_COLD_GPIO (0x0fff0000ul) /** In ColdSleep state,
Detected GPIO interrupt */
-#define PM_BOOT_COLD_SEN_INT (0x10000000ul) /** In ColdSleep state,
Detected SEN_INT Interrupt */
-#define PM_BOOT_COLD_PMIC_INT (0x20000000ul) /** In ColdSleep state,
Detected PMIC Interrupt */
-#define PM_BOOT_COLD_USB_DETACH (0x40000000ul) /** In ColdSleep state, USB
Disconnected */
-#define PM_BOOT_COLD_USB_ATTACH (0x80000000ul) /** In ColdSleep state, USB
Connected */
+#define PM_BOOT_POR_NORMAL (0x00000000ul) /* Power On Reset like as
battery attached */
+#define PM_BOOT_POR_DEADBATT (0x00000001ul) /* Battery charged from
DeadBattery state */
+#define PM_BOOT_WDT_REBOOT (0x00000002ul) /* System WDT expired or
Explicitly Self Reboot */
+#define PM_BOOT_WDT_RESET (0x00000004ul) /* Chip WDT expired (might be
used in HV-only system) */
+#define PM_BOOT_DEEP_WKUPL (0x00000008ul) /* In DeepSleep state, Detected
WKUPL signal */
+#define PM_BOOT_DEEP_WKUPS (0x00000010ul) /* In DeepSleep state, Detected
WKUPS signal */
+#define PM_BOOT_DEEP_RTC (0x00000020ul) /* In DeepSleep state, RTC
Alarm expired */
+#define PM_BOOT_DEEP_USB_ATTACH (0x00000040ul) /* In DeepSleep state, USB
Connected */
+#define PM_BOOT_DEEP_OTHERS (0x00000080ul) /* In DeepSleep state, Reserved
others cause occurred */
+#define PM_BOOT_COLD_SCU_INT (0x00000100ul) /* In ColdSleep state, Detected
SCU Interrupt */
+#define PM_BOOT_COLD_RTC (0x00001e00ul) /* In ColdSleep state, RTC
Alarm Interrupt */
+#define PM_BOOT_COLD_RTC_ALM0 (0x00000200ul) /* In ColdSleep state, RTC
Alarm0 expired */
+#define PM_BOOT_COLD_RTC_ALM1 (0x00000400ul) /* In ColdSleep state, RTC
Alarm1 expired */
+#define PM_BOOT_COLD_RTC_ALM2 (0x00000800ul) /* In ColdSleep state, RTC
Alarm2 expired */
+#define PM_BOOT_COLD_RTC_ALMERR (0x00001000ul) /* In ColdSleep state, RTC
Alarm Error occurred */
+#define PM_BOOT_COLD_GPIO (0x0fff0000ul) /* In ColdSleep state, Detected
GPIO interrupt */
+#define PM_BOOT_COLD_SEN_INT (0x10000000ul) /* In ColdSleep state, Detected
SEN_INT Interrupt */
+#define PM_BOOT_COLD_PMIC_INT (0x20000000ul) /* In ColdSleep state, Detected
PMIC Interrupt */
+#define PM_BOOT_COLD_USB_DETACH (0x40000000ul) /* In ColdSleep state, USB
Disconnected */
+#define PM_BOOT_COLD_USB_ATTACH (0x80000000ul) /* In ColdSleep state, USB
Connected */
/* SRAM power status definitions */
@@ -350,14 +350,14 @@ int up_pm_reboot(void);
* Name: up_pmic_set_notify
*
* Description:
- * Register a callback for pmic interrupt
+ * Register a callback for pmic interrupt.
*
* Input Parameter:
* kind - A kind of pmic interrupt defined as pmic_notify_e
* cb - A callback function for a kind of pmic interrupt
*
* Returned Value:
- * Return 0 on success. Otherwise, return a negated errno.
+ * Return 0 on success. Otherwise, return a negated errno.
*
****************************************************************************/
diff --git a/arch/arm/src/rtl8720c/amebaz_coex.h
b/arch/arm/src/rtl8720c/amebaz_coex.h
index bac46e5c0c..27782bfd7a 100644
--- a/arch/arm/src/rtl8720c/amebaz_coex.h
+++ b/arch/arm/src/rtl8720c/amebaz_coex.h
@@ -45,18 +45,18 @@
typedef struct net_buf_simple_s
{
- /* * Pointer to the start of data in the buffer. */
+ /* Pointer to the start of data in the buffer. */
uint8_t *data;
- /* * Length of the data behind the data pointer. */
+ /* Length of the data behind the data pointer. */
uint16_t len;
- /* * Amount of data that this buffer can store. */
+ /* Amount of data that this buffer can store. */
uint16_t size;
- /** Start of the data storage. Not to be accessed directly
+ /* Start of the data storage. Not to be accessed directly
* (the data pointer should be used instead).
*/
diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_dmamux.h
b/arch/arm/src/s32k3xx/hardware/s32k3xx_dmamux.h
index 8481579a1e..129b3d1962 100644
--- a/arch/arm/src/s32k3xx/hardware/s32k3xx_dmamux.h
+++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_dmamux.h
@@ -105,7 +105,7 @@
/* DMA Request sources */
-/** edma_mux0 **/
+/* edma_mux0 */
#define DMA_REQ_DISABLED0 (0) /* Channel disabled (default) */
#define DMA_REQ_SIUL_0 (1) /* SIUL DMA request 0 */
@@ -172,7 +172,7 @@
#define DMA_REQ_ENABLED0 (62) /* Always enabled */
#define DMA_REQ_ENABLED1 (63) /* Always enabled */
-/** edma_mux1 **/
+/* edma_mux1 */
#define DMA_REQ_DISABLED1 (DMAMUX_CHCFG_DMAMUX1 | 0) /* Channel disabled
(default) */
#define DMA_REQ_SIUL_8 (DMAMUX_CHCFG_DMAMUX1 | 1) /* SIUL DMA request 8
*/
diff --git a/arch/arm/src/samd5e5/sam_usb.c b/arch/arm/src/samd5e5/sam_usb.c
index d49c974826..4b8da12cee 100644
--- a/arch/arm/src/samd5e5/sam_usb.c
+++ b/arch/arm/src/samd5e5/sam_usb.c
@@ -398,37 +398,35 @@ enum sam_hoststate_e
enum usb_h_pipe_state
{
- USB_H_PIPE_S_FREE = 0x00, /** Pipe is free to allocate */
- USB_H_PIPE_S_CFG = 0x01, /** Pipe is in configuration */
- USB_H_PIPE_S_IDLE = 0x02, /** Pipe is allocated and idle */
- USB_H_PIPE_S_SETUP = 0x03, /** Pipe in control setup stage */
- USB_H_PIPE_S_DATI = 0x05, /** Pipe in data IN stage */
- USB_H_PIPE_S_DATO = 0x06, /** Pipe in data OUT stage */
- USB_H_PIPE_S_ZLPI = 0x07, /** Pipe in data IN ZLP stage */
- USB_H_PIPE_S_ZLPO = 0x08, /** Pipe in data OUT ZLP stage */
- USB_H_PIPE_S_STATI = 0x09, /** Pipe in control status IN stage */
- USB_H_PIPE_S_STATO = 0x0a, /** Pipe in control status OUT stage */
- USB_H_PIPE_S_TAKEN = 0x10 /** Taken by physical pipe (in process) */
+ USB_H_PIPE_S_FREE = 0x00, /* Pipe is free to allocate */
+ USB_H_PIPE_S_CFG = 0x01, /* Pipe is in configuration */
+ USB_H_PIPE_S_IDLE = 0x02, /* Pipe is allocated and idle */
+ USB_H_PIPE_S_SETUP = 0x03, /* Pipe in control setup stage */
+ USB_H_PIPE_S_DATI = 0x05, /* Pipe in data IN stage */
+ USB_H_PIPE_S_DATO = 0x06, /* Pipe in data OUT stage */
+ USB_H_PIPE_S_ZLPI = 0x07, /* Pipe in data IN ZLP stage */
+ USB_H_PIPE_S_ZLPO = 0x08, /* Pipe in data OUT ZLP stage */
+ USB_H_PIPE_S_STATI = 0x09, /* Pipe in control status IN stage */
+ USB_H_PIPE_S_STATO = 0x0a, /* Pipe in control status OUT stage */
+ USB_H_PIPE_S_TAKEN = 0x10 /* Taken by physical pipe (in process) */
};
-/**
- * @brief USB HCD status code
- */
+/* USB HCD status code */
enum usb_h_status
{
- USB_H_OK = 0, /** OK */
- USB_H_BUSY = -4, /** Busy */
- USB_H_DENIED = -17, /** Denied */
- USB_H_TIMEOUT = -8, /** Timeout */
- USB_H_ABORT = -3, /** Abort */
- USB_H_STALL = -25, /** Stall protocol */
- USB_H_RESET = -7, /** Transfer reset by pipe re-configure */
- USB_H_ERR_ARG = -13, /** Argument error */
- USB_H_ERR_UNSP_OP = -27, /** Operation not supported */
- USB_H_ERR_NO_RSC = -28, /** No resource */
- USB_H_ERR_NOT_INIT = -20, /** Not initialized */
- USB_H_ERR = -6 /** Some general error */
+ USB_H_OK = 0, /* OK */
+ USB_H_BUSY = -4, /* Busy */
+ USB_H_DENIED = -17, /* Denied */
+ USB_H_TIMEOUT = -8, /* Timeout */
+ USB_H_ABORT = -3, /* Abort */
+ USB_H_STALL = -25, /* Stall protocol */
+ USB_H_RESET = -7, /* Transfer reset by pipe re-configure */
+ USB_H_ERR_ARG = -13, /* Argument error */
+ USB_H_ERR_UNSP_OP = -27, /* Operation not supported */
+ USB_H_ERR_NO_RSC = -28, /* No resource */
+ USB_H_ERR_NOT_INIT = -20, /* Not initialized */
+ USB_H_ERR = -6 /* Some general error */
};
/* The following enumeration represents the various states of the USB host
@@ -459,8 +457,7 @@ enum sam_chreason_e
CHREASON_CANCELLED /* Transfer cancelled */
};
-/**
- * @brief Transfer descriptor for control transfer
+/* Transfer descriptor for control transfer
*
* Timing in USB 2.0 spec.:
* - 9.2.6.1 : USB sets an upper limit of 5 seconds as the upper
@@ -484,7 +481,7 @@ enum sam_chreason_e
* to the host within 500 ms of receipt of the request. For
* subsequent data packets, if any, the device must be able to
* return them within 500 ms of successful completion of the
- * transmission of the previous packet. The device must then be
+ * transmission of the previous packet. The device must then be
* able to successfully complete the status stage
* within 50 ms after returning the last data packet.
* For standard device requests that require a data stage transfer
@@ -512,49 +509,43 @@ struct usb_h_ctrl_xfer
int8_t status; /* Last transfer status */
};
-/**
- * Transfer descriptor for bulk / interrupt / iso transfer
- */
+/* Transfer descriptor for bulk / interrupt / iso transfer */
struct usb_h_bulk_int_iso_xfer
{
- uint32_t size; /** Expected transfer size */
- uint32_t count; /** Transfer count */
- uint8_t *data; /** Pointer to transfer data */
+ uint32_t size; /* Expected transfer size */
+ uint32_t count; /* Transfer count */
+ uint8_t *data; /* Pointer to transfer data */
uint16_t reserved[3];
- uint8_t state; /** Transfer state */
- int8_t status; /** Last transfer status */
+ uint8_t state; /* Transfer state */
+ int8_t status; /* Last transfer status */
};
-/**
- * Transfer descriptor for periodic high bandwidth transfer
- */
+/* Transfer descriptor for periodic high bandwidth transfer */
struct usb_h_high_bw_xfer
{
- uint32_t size; /** Expected transfer size */
- uint32_t count; /** Transfer count */
- uint8_t *data; /** Pointer to transfer data */
- uint16_t pkt_size[3]; /** Micro frame packet sizes */
- uint8_t state; /** Transfer state */
- int8_t status; /** Last transfer status */
+ uint32_t size; /* Expected transfer size */
+ uint32_t count; /* Transfer count */
+ uint8_t *data; /* Pointer to transfer data */
+ uint16_t pkt_size[3]; /* Micro frame packet sizes */
+ uint8_t state; /* Transfer state */
+ int8_t status; /* Last transfer status */
};
-/**
- * General transfer descriptor
- */
+/* General transfer descriptor */
struct usb_h_xfer
{
- /** Reserved for different transfer */
+ /* Reserved for different transfer */
union
{
uint16_t u16[9];
uint8_t u8[18];
} reserved;
- uint8_t state; /** Transfer state */
- int8_t status; /** Last transfer status */
+ uint8_t state; /* Transfer state */
+ int8_t status; /* Last transfer status */
};
/* USB Host Controller Driver Pipe structure */
@@ -609,7 +600,7 @@ struct sam_pipe_s
uint8_t dma : 1; /* Uses DMA (on transfer) */
uint8_t periodic_start : 1; /* Transfer periodic */
- /** Transfer status */
+ /* Transfer status */
union
{
@@ -650,12 +641,12 @@ struct sam_usbhost_s
uint8_t xfrtype; /* See enum _hxfrdn_e */
sem_t pscsem; /* Semaphore to wait for a port event */
- uint16_t pipes_unfreeze; /** Pipes to unfreeze after wakeup */
- int8_t suspend_start; /** Delayed suspend time in ms */
- int8_t resume_start; /** Delayed resume time in ms */
- int8_t n_ctrl_req_user; /** Control transfer request user count */
- int8_t n_sof_user; /** SOF user count (callback, suspend, resume, ctrl
request) */
- uint8_t pipe_pool_size; /** Pipe pool size in number of pipes */
+ uint16_t pipes_unfreeze; /* Pipes to unfreeze after wakeup */
+ int8_t suspend_start; /* Delayed suspend time in ms */
+ int8_t resume_start; /* Delayed resume time in ms */
+ int8_t n_ctrl_req_user; /* Control transfer request user count */
+ int8_t n_sof_user; /* SOF user count (callback, suspend, resume, ctrl
request) */
+ uint8_t pipe_pool_size; /* Pipe pool size in number of pipes */
#ifdef CONFIG_USBHOST_HUB
diff --git a/arch/arm/src/samd5e5/sam_wdt.c b/arch/arm/src/samd5e5/sam_wdt.c
index 3b0589ee67..a109b18bbf 100644
--- a/arch/arm/src/samd5e5/sam_wdt.c
+++ b/arch/arm/src/samd5e5/sam_wdt.c
@@ -54,7 +54,7 @@
* Pre-processor Definitions
****************************************************************************/
-/** N clock cycles */
+/* N clock cycles */
#define WDT_CLK_8CYCLE 8
#define WDT_CLK_16CYCLE 16
diff --git a/arch/arm/src/stm32/stm32_waste.h b/arch/arm/src/stm32/stm32_waste.h
index be7a0dc794..cef4eff203 100644
--- a/arch/arm/src/stm32/stm32_waste.h
+++ b/arch/arm/src/stm32/stm32_waste.h
@@ -42,16 +42,16 @@ extern "C"
* Public Function Prototypes
****************************************************************************/
-/** Waste CPU Time
+/* Waste CPU Time
*
- * stm32_waste() is the logic that will be executed when portions of kernel
- * or user-app is polling some register or similar, waiting for desired
- * status. This time is wasted away. This function offers a measure of
- * badly written piece of software or some undesired behavior.
+ * stm32_waste() is the logic that will be executed when portions of kernel
+ * or user-app is polling some register or similar, waiting for desired
+ * status. This time is wasted away. This function offers a measure of
+ * badly written piece of software or some undesired behavior.
*
- * At the same time this function adds to some IDLE time which portion
- * cannot be used for other purposes (yet).
- **/
+ * At the same time this function adds to some IDLE time which portion
+ * cannot be used for other purposes (yet).
+ */
void stm32_waste(void);
diff --git a/arch/arm/src/stm32f7/stm32_waste.h
b/arch/arm/src/stm32f7/stm32_waste.h
index 904e6abd73..c83044026e 100644
--- a/arch/arm/src/stm32f7/stm32_waste.h
+++ b/arch/arm/src/stm32f7/stm32_waste.h
@@ -42,16 +42,16 @@ extern "C"
* Public Function Prototypes
****************************************************************************/
-/** Waste CPU Time
+/* Waste CPU Time
*
- * stm32_waste() is the logic that will be executed when portions of kernel
- * or user-app is polling some register or similar, waiting for desired
- * status. This time is wasted away. This function offers a measure of
- * badly written piece of software or some undesired behavior.
+ * stm32_waste() is the logic that will be executed when portions of kernel
+ * or user-app is polling some register or similar, waiting for desired
+ * status. This time is wasted away. This function offers a measure of
+ * badly written piece of software or some undesired behavior.
*
- * At the same time this function adds to some IDLE time which portion
- * cannot be used for other purposes (yet).
- **/
+ * At the same time this function adds to some IDLE time which portion
+ * cannot be used for other purposes (yet).
+ */
void stm32_waste(void);
diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_saradc.h
b/arch/risc-v/src/esp32c3/hardware/esp32c3_saradc.h
index d0f110b834..3d6a281e1c 100644
--- a/arch/risc-v/src/esp32c3/hardware/esp32c3_saradc.h
+++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_saradc.h
@@ -33,11 +33,11 @@
#define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x000)
-/** APB_SARADC_WAIT_ARB_CYCLE : R/W ;bitpos:[31:30] ;default: 2'd1 ;
+/* APB_SARADC_WAIT_ARB_CYCLE : R/W ;bitpos:[31:30] ;default: 2'd1 ;
* description: wait arbit signal stable after sar_done
*/
-#define APB_SARADC_WAIT_ARB_CYCLE 0x00000003
+#define APB_SARADC_WAIT_ARB_CYCLE 0x00000003
#define APB_SARADC_WAIT_ARB_CYCLE_M
((APB_SARADC_WAIT_ARB_CYCLE_V)<<(APB_SARADC_WAIT_ARB_CYCLE_S))
#define APB_SARADC_WAIT_ARB_CYCLE_V 0x3
#define APB_SARADC_WAIT_ARB_CYCLE_S 30
@@ -46,7 +46,7 @@
/* description: force option to xpd sar blocks */
-#define APB_SARADC_XPD_SAR_FORCE 0x00000003
+#define APB_SARADC_XPD_SAR_FORCE 0x00000003
#define APB_SARADC_XPD_SAR_FORCE_M
((APB_SARADC_XPD_SAR_FORCE_V)<<(APB_SARADC_XPD_SAR_FORCE_S))
#define APB_SARADC_XPD_SAR_FORCE_V 0x3
#define APB_SARADC_XPD_SAR_FORCE_S 27
@@ -64,7 +64,7 @@
/* description: 0 ~ 15 means length 1 ~ 16 */
-#define APB_SARADC_SAR_PATT_LEN 0x00000007
+#define APB_SARADC_SAR_PATT_LEN 0x00000007
#define APB_SARADC_SAR_PATT_LEN_M
((APB_SARADC_SAR_PATT_LEN_V)<<(APB_SARADC_SAR_PATT_LEN_S))
#define APB_SARADC_SAR_PATT_LEN_V 0x7
#define APB_SARADC_SAR_PATT_LEN_S 15
@@ -73,7 +73,7 @@
/* description: SAR clock divider */
-#define APB_SARADC_SAR_CLK_DIV 0x000000FF
+#define APB_SARADC_SAR_CLK_DIV 0x000000FF
#define APB_SARADC_SAR_CLK_DIV_M
((APB_SARADC_SAR_CLK_DIV_V)<<(APB_SARADC_SAR_CLK_DIV_S))
#define APB_SARADC_SAR_CLK_DIV_V 0xFF
#define APB_SARADC_SAR_CLK_DIV_S 7
@@ -147,7 +147,7 @@
/* description: max conversion number */
-#define APB_SARADC_MAX_MEAS_NUM 0x000000FF
+#define APB_SARADC_MAX_MEAS_NUM 0x000000FF
#define APB_SARADC_MAX_MEAS_NUM_M
((APB_SARADC_MAX_MEAS_NUM_V)<<(APB_SARADC_MAX_MEAS_NUM_S))
#define APB_SARADC_MAX_MEAS_NUM_V 0xFF
#define APB_SARADC_MAX_MEAS_NUM_S 1
@@ -156,7 +156,7 @@
/* description: */
-#define APB_SARADC_MEAS_NUM_LIMIT (BIT(0))
+#define APB_SARADC_MEAS_NUM_LIMIT (BIT(0))
#define APB_SARADC_MEAS_NUM_LIMIT_M (BIT(0))
#define APB_SARADC_MEAS_NUM_LIMIT_V 0x1
#define APB_SARADC_MEAS_NUM_LIMIT_S 0
@@ -167,7 +167,7 @@
/* description: */
-#define APB_SARADC_FILTER_FACTOR0 0x00000007
+#define APB_SARADC_FILTER_FACTOR0 0x00000007
#define APB_SARADC_FILTER_FACTOR0_M
((APB_SARADC_FILTER_FACTOR0_V)<<(APB_SARADC_FILTER_FACTOR0_S))
#define APB_SARADC_FILTER_FACTOR0_V 0x7
#define APB_SARADC_FILTER_FACTOR0_S 29
@@ -176,7 +176,7 @@
/* description: */
-#define APB_SARADC_FILTER_FACTOR1 0x00000007
+#define APB_SARADC_FILTER_FACTOR1 0x00000007
#define APB_SARADC_FILTER_FACTOR1_M
((APB_SARADC_FILTER_FACTOR1_V)<<(APB_SARADC_FILTER_FACTOR1_S))
#define APB_SARADC_FILTER_FACTOR1_V 0x7
#define APB_SARADC_FILTER_FACTOR1_S 26
@@ -187,7 +187,7 @@
/* description: */
-#define APB_SARADC_STANDBY_WAIT 0x000000FF
+#define APB_SARADC_STANDBY_WAIT 0x000000FF
#define APB_SARADC_STANDBY_WAIT_M
((APB_SARADC_STANDBY_WAIT_V)<<(APB_SARADC_STANDBY_WAIT_S))
#define APB_SARADC_STANDBY_WAIT_V 0xFF
#define APB_SARADC_STANDBY_WAIT_S 16
@@ -196,7 +196,7 @@
/* description: */
-#define APB_SARADC_RSTB_WAIT 0x000000FF
+#define APB_SARADC_RSTB_WAIT 0x000000FF
#define APB_SARADC_RSTB_WAIT_M
((APB_SARADC_RSTB_WAIT_V)<<(APB_SARADC_RSTB_WAIT_S))
#define APB_SARADC_RSTB_WAIT_V 0xFF
#define APB_SARADC_RSTB_WAIT_S 8
@@ -205,7 +205,7 @@
/* description: */
-#define APB_SARADC_XPD_WAIT 0x000000FF
+#define APB_SARADC_XPD_WAIT 0x000000FF
#define APB_SARADC_XPD_WAIT_M
((APB_SARADC_XPD_WAIT_V)<<(APB_SARADC_XPD_WAIT_S))
#define APB_SARADC_XPD_WAIT_V 0xFF
#define APB_SARADC_XPD_WAIT_S 0
@@ -216,7 +216,7 @@
/* description: */
-#define APB_SARADC_SAR1_STATUS 0xFFFFFFFF
+#define APB_SARADC_SAR1_STATUS 0xFFFFFFFF
#define APB_SARADC_SAR1_STATUS_M
((APB_SARADC_SAR1_STATUS_V)<<(APB_SARADC_SAR1_STATUS_S))
#define APB_SARADC_SAR1_STATUS_V 0xFFFFFFFF
#define APB_SARADC_SAR1_STATUS_S 0
@@ -227,7 +227,7 @@
/* description: */
-#define APB_SARADC_SAR2_STATUS 0xFFFFFFFF
+#define APB_SARADC_SAR2_STATUS 0xFFFFFFFF
#define APB_SARADC_SAR2_STATUS_M
((APB_SARADC_SAR2_STATUS_V)<<(APB_SARADC_SAR2_STATUS_S))
#define APB_SARADC_SAR2_STATUS_V 0xFFFFFFFF
#define APB_SARADC_SAR2_STATUS_S 0
@@ -238,7 +238,7 @@
/* description: item 0 ~ 3 for pattern table 1 (each item one byte) */
-#define APB_SARADC_SAR_PATT_TAB1 0x00FFFFFF
+#define APB_SARADC_SAR_PATT_TAB1 0x00FFFFFF
#define APB_SARADC_SAR_PATT_TAB1_M
((APB_SARADC_SAR_PATT_TAB1_V)<<(APB_SARADC_SAR_PATT_TAB1_S))
#define APB_SARADC_SAR_PATT_TAB1_V 0xFFFFFF
#define APB_SARADC_SAR_PATT_TAB1_S 0
@@ -249,7 +249,7 @@
/* description: Item 4 ~ 7 for pattern table 1 (each item one byte) */
-#define APB_SARADC_SAR_PATT_TAB2 0x00FFFFFF
+#define APB_SARADC_SAR_PATT_TAB2 0x00FFFFFF
#define APB_SARADC_SAR_PATT_TAB2_M
((APB_SARADC_SAR_PATT_TAB2_V)<<(APB_SARADC_SAR_PATT_TAB2_S))
#define APB_SARADC_SAR_PATT_TAB2_V 0xFFFFFF
#define APB_SARADC_SAR_PATT_TAB2_S 0
@@ -260,7 +260,7 @@
/* description: */
-#define APB_SARADC1_ONETIME_SAMPLE (BIT(31))
+#define APB_SARADC1_ONETIME_SAMPLE (BIT(31))
#define APB_SARADC1_ONETIME_SAMPLE_M (BIT(31))
#define APB_SARADC1_ONETIME_SAMPLE_V 0x1
#define APB_SARADC1_ONETIME_SAMPLE_S 31
@@ -269,7 +269,7 @@
/* description: */
-#define APB_SARADC2_ONETIME_SAMPLE (BIT(30))
+#define APB_SARADC2_ONETIME_SAMPLE (BIT(30))
#define APB_SARADC2_ONETIME_SAMPLE_M (BIT(30))
#define APB_SARADC2_ONETIME_SAMPLE_V 0x1
#define APB_SARADC2_ONETIME_SAMPLE_S 30
@@ -278,7 +278,7 @@
/* description: */
-#define APB_SARADC_ONETIME_START (BIT(29))
+#define APB_SARADC_ONETIME_START (BIT(29))
#define APB_SARADC_ONETIME_START_M (BIT(29))
#define APB_SARADC_ONETIME_START_V 0x1
#define APB_SARADC_ONETIME_START_S 29
@@ -287,7 +287,7 @@
/* description: */
-#define APB_SARADC_ONETIME_CHANNEL 0x0000000F
+#define APB_SARADC_ONETIME_CHANNEL 0x0000000F
#define APB_SARADC_ONETIME_CHANNEL_M
((APB_SARADC_ONETIME_CHANNEL_V)<<(APB_SARADC_ONETIME_CHANNEL_S))
#define APB_SARADC_ONETIME_CHANNEL_V 0xF
#define APB_SARADC_ONETIME_CHANNEL_S 25
@@ -296,7 +296,7 @@
/* description: */
-#define APB_SARADC_ONETIME_ATTEN 0x00000003
+#define APB_SARADC_ONETIME_ATTEN 0x00000003
#define APB_SARADC_ONETIME_ATTEN_M
((APB_SARADC_ONETIME_ATTEN_V)<<(APB_SARADC_ONETIME_ATTEN_S))
#define APB_SARADC_ONETIME_ATTEN_V 0x3
#define APB_SARADC_ONETIME_ATTEN_S 23
@@ -307,7 +307,7 @@
/* description: adc2 arbiter uses fixed priority */
-#define APB_SARADC_ADC_ARB_FIX_PRIORITY (BIT(12))
+#define APB_SARADC_ADC_ARB_FIX_PRIORITY (BIT(12))
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M (BIT(12))
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V 0x1
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S 12
@@ -316,7 +316,7 @@
/* description: Set adc2 arbiter wifi priority */
-#define APB_SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003
+#define APB_SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M
((APB_SARADC_ADC_ARB_WIFI_PRIORITY_V)<<(APB_SARADC_ADC_ARB_WIFI_PRIORITY_S))
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V 0x3
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S 10
@@ -325,7 +325,7 @@
/* description: Set adc2 arbiter rtc priority */
-#define APB_SARADC_ADC_ARB_RTC_PRIORITY 0x00000003
+#define APB_SARADC_ADC_ARB_RTC_PRIORITY 0x00000003
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M
((APB_SARADC_ADC_ARB_RTC_PRIORITY_V)<<(APB_SARADC_ADC_ARB_RTC_PRIORITY_S))
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V 0x3
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S 8
@@ -334,7 +334,7 @@
/* description: Set adc2 arbiterapb priority */
-#define APB_SARADC_ADC_ARB_APB_PRIORITY 0x00000003
+#define APB_SARADC_ADC_ARB_APB_PRIORITY 0x00000003
#define APB_SARADC_ADC_ARB_APB_PRIORITY_M
((APB_SARADC_ADC_ARB_APB_PRIORITY_V)<<(APB_SARADC_ADC_ARB_APB_PRIORITY_S))
#define APB_SARADC_ADC_ARB_APB_PRIORITY_V 0x3
#define APB_SARADC_ADC_ARB_APB_PRIORITY_S 6
@@ -343,7 +343,7 @@
/* description: adc2 arbiter force grant */
-#define APB_SARADC_ADC_ARB_GRANT_FORCE (BIT(5))
+#define APB_SARADC_ADC_ARB_GRANT_FORCE (BIT(5))
#define APB_SARADC_ADC_ARB_GRANT_FORCE_M (BIT(5))
#define APB_SARADC_ADC_ARB_GRANT_FORCE_V 0x1
#define APB_SARADC_ADC_ARB_GRANT_FORCE_S 5
@@ -352,7 +352,7 @@
/* description: adc2 arbiter force to enable wifi controller */
-#define APB_SARADC_ADC_ARB_WIFI_FORCE (BIT(4))
+#define APB_SARADC_ADC_ARB_WIFI_FORCE (BIT(4))
#define APB_SARADC_ADC_ARB_WIFI_FORCE_M (BIT(4))
#define APB_SARADC_ADC_ARB_WIFI_FORCE_V 0x1
#define APB_SARADC_ADC_ARB_WIFI_FORCE_S 4
@@ -361,7 +361,7 @@
/* description: adc2 arbiter force to enable rtc controller */
-#define APB_SARADC_ADC_ARB_RTC_FORCE (BIT(3))
+#define APB_SARADC_ADC_ARB_RTC_FORCE (BIT(3))
#define APB_SARADC_ADC_ARB_RTC_FORCE_M (BIT(3))
#define APB_SARADC_ADC_ARB_RTC_FORCE_V 0x1
#define APB_SARADC_ADC_ARB_RTC_FORCE_S 3
@@ -370,7 +370,7 @@
/* description: adc2 arbiter force to enableapb controller */
-#define APB_SARADC_ADC_ARB_APB_FORCE (BIT(2))
+#define APB_SARADC_ADC_ARB_APB_FORCE (BIT(2))
#define APB_SARADC_ADC_ARB_APB_FORCE_M (BIT(2))
#define APB_SARADC_ADC_ARB_APB_FORCE_V 0x1
#define APB_SARADC_ADC_ARB_APB_FORCE_S 2
@@ -381,7 +381,7 @@
/* description: enable apb_adc1_filter */
-#define APB_SARADC_FILTER_RESET (BIT(31))
+#define APB_SARADC_FILTER_RESET (BIT(31))
#define APB_SARADC_FILTER_RESET_M (BIT(31))
#define APB_SARADC_FILTER_RESET_V 0x1
#define APB_SARADC_FILTER_RESET_S 31
@@ -390,7 +390,7 @@
/* description: apb_adc1_filter_factor */
-#define APB_SARADC_FILTER_CHANNEL0 0x0000000F
+#define APB_SARADC_FILTER_CHANNEL0 0x0000000F
#define APB_SARADC_FILTER_CHANNEL0_M
((APB_SARADC_FILTER_CHANNEL0_V)<<(APB_SARADC_FILTER_CHANNEL0_S))
#define APB_SARADC_FILTER_CHANNEL0_V 0xF
#define APB_SARADC_FILTER_CHANNEL0_S 22
@@ -399,7 +399,7 @@
/* description: */
-#define APB_SARADC_FILTER_CHANNEL1 0x0000000F
+#define APB_SARADC_FILTER_CHANNEL1 0x0000000F
#define APB_SARADC_FILTER_CHANNEL1_M
((APB_SARADC_FILTER_CHANNEL1_V)<<(APB_SARADC_FILTER_CHANNEL1_S))
#define APB_SARADC_FILTER_CHANNEL1_V 0xF
#define APB_SARADC_FILTER_CHANNEL1_S 18
@@ -410,7 +410,7 @@
/* description: */
-#define APB_SARADC_ADC1_DATA 0x0001FFFF
+#define APB_SARADC_ADC1_DATA 0x0001FFFF
#define APB_SARADC_ADC1_DATA_M
((APB_SARADC_ADC1_DATA_V)<<(APB_SARADC_ADC1_DATA_S))
#define APB_SARADC_ADC1_DATA_V 0x1FFFF
#define APB_SARADC_ADC1_DATA_S 0
@@ -421,7 +421,7 @@
/* description: */
-#define APB_SARADC_ADC2_DATA 0x0001FFFF
+#define APB_SARADC_ADC2_DATA 0x0001FFFF
#define APB_SARADC_ADC2_DATA_M
((APB_SARADC_ADC2_DATA_V)<<(APB_SARADC_ADC2_DATA_S))
#define APB_SARADC_ADC2_DATA_V 0x1FFFF
#define APB_SARADC_ADC2_DATA_S 0
@@ -432,7 +432,7 @@
/* description: saradc1's thres0 monitor thres */
-#define APB_SARADC_THRES0_LOW 0x00001FFF
+#define APB_SARADC_THRES0_LOW 0x00001FFF
#define APB_SARADC_THRES0_LOW_M
((APB_SARADC_THRES0_LOW_V)<<(APB_SARADC_THRES0_LOW_S))
#define APB_SARADC_THRES0_LOW_V 0x1FFF
#define APB_SARADC_THRES0_LOW_S 18
@@ -441,7 +441,7 @@
/* description: saradc1's thres0 monitor thres */
-#define APB_SARADC_THRES0_HIGH 0x00001FFF
+#define APB_SARADC_THRES0_HIGH 0x00001FFF
#define APB_SARADC_THRES0_HIGH_M
((APB_SARADC_THRES0_HIGH_V)<<(APB_SARADC_THRES0_HIGH_S))
#define APB_SARADC_THRES0_HIGH_V 0x1FFF
#define APB_SARADC_THRES0_HIGH_S 5
@@ -450,7 +450,7 @@
/* description: */
-#define APB_SARADC_THRES0_CHANNEL 0x0000000F
+#define APB_SARADC_THRES0_CHANNEL 0x0000000F
#define APB_SARADC_THRES0_CHANNEL_M
((APB_SARADC_THRES0_CHANNEL_V)<<(APB_SARADC_THRES0_CHANNEL_S))
#define APB_SARADC_THRES0_CHANNEL_V 0xF
#define APB_SARADC_THRES0_CHANNEL_S 0
@@ -461,7 +461,7 @@
/* description: saradc1's thres0 monitor thres */
-#define APB_SARADC_THRES1_LOW 0x00001FFF
+#define APB_SARADC_THRES1_LOW 0x00001FFF
#define APB_SARADC_THRES1_LOW_M
((APB_SARADC_THRES1_LOW_V)<<(APB_SARADC_THRES1_LOW_S))
#define APB_SARADC_THRES1_LOW_V 0x1FFF
#define APB_SARADC_THRES1_LOW_S 18
@@ -470,7 +470,7 @@
/* description: saradc1's thres0 monitor thres */
-#define APB_SARADC_THRES1_HIGH 0x00001FFF
+#define APB_SARADC_THRES1_HIGH 0x00001FFF
#define APB_SARADC_THRES1_HIGH_M
((APB_SARADC_THRES1_HIGH_V)<<(APB_SARADC_THRES1_HIGH_S))
#define APB_SARADC_THRES1_HIGH_V 0x1FFF
#define APB_SARADC_THRES1_HIGH_S 5
@@ -479,7 +479,7 @@
/* description: */
-#define APB_SARADC_THRES1_CHANNEL 0x0000000F
+#define APB_SARADC_THRES1_CHANNEL 0x0000000F
#define APB_SARADC_THRES1_CHANNEL_M
((APB_SARADC_THRES1_CHANNEL_V)<<(APB_SARADC_THRES1_CHANNEL_S))
#define APB_SARADC_THRES1_CHANNEL_V 0xF
#define APB_SARADC_THRES1_CHANNEL_S 0
@@ -490,7 +490,7 @@
/* description: */
-#define APB_SARADC_THRES0_EN (BIT(31))
+#define APB_SARADC_THRES0_EN (BIT(31))
#define APB_SARADC_THRES0_EN_M (BIT(31))
#define APB_SARADC_THRES0_EN_V 0x1
#define APB_SARADC_THRES0_EN_S 31
@@ -499,14 +499,14 @@
/* description: */
-#define APB_SARADC_THRES1_EN (BIT(30))
+#define APB_SARADC_THRES1_EN (BIT(30))
#define APB_SARADC_THRES1_EN_M (BIT(30))
#define APB_SARADC_THRES1_EN_V 0x1
#define APB_SARADC_THRES1_EN_S 30
/* description: */
-#define APB_SARADC_THRES_ALL_EN (BIT(27))
+#define APB_SARADC_THRES_ALL_EN (BIT(27))
#define APB_SARADC_THRES_ALL_EN_M (BIT(27))
#define APB_SARADC_THRES_ALL_EN_V 0x1
#define APB_SARADC_THRES_ALL_EN_S 27
@@ -517,7 +517,7 @@
/* description: */
-#define APB_SARADC_ADC1_DONE_INT_ENA (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_ENA (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_ENA_M (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_ENA_V 0x1
#define APB_SARADC_ADC1_DONE_INT_ENA_S 31
@@ -526,7 +526,7 @@
/* description: */
-#define APB_SARADC_ADC2_DONE_INT_ENA (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_ENA (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_ENA_M (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_ENA_V 0x1
#define APB_SARADC_ADC2_DONE_INT_ENA_S 30
@@ -535,7 +535,7 @@
/* description: */
-#define APB_SARADC_THRES0_HIGH_INT_ENA (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_ENA (BIT(29))
#define APB_SARADC_THRES0_HIGH_INT_ENA_M (BIT(29))
#define APB_SARADC_THRES0_HIGH_INT_ENA_V 0x1
#define APB_SARADC_THRES0_HIGH_INT_ENA_S 29
@@ -544,7 +544,7 @@
/* description: */
-#define APB_SARADC_THRES1_HIGH_INT_ENA (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_ENA (BIT(28))
#define APB_SARADC_THRES1_HIGH_INT_ENA_M (BIT(28))
#define APB_SARADC_THRES1_HIGH_INT_ENA_V 0x1
#define APB_SARADC_THRES1_HIGH_INT_ENA_S 28
@@ -553,7 +553,7 @@
/* description: */
-#define APB_SARADC_THRES0_LOW_INT_ENA (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_ENA (BIT(27))
#define APB_SARADC_THRES0_LOW_INT_ENA_M (BIT(27))
#define APB_SARADC_THRES0_LOW_INT_ENA_V 0x1
#define APB_SARADC_THRES0_LOW_INT_ENA_S 27
@@ -562,18 +562,18 @@
/* description: */
-#define APB_SARADC_THRES1_LOW_INT_ENA (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_ENA (BIT(26))
#define APB_SARADC_THRES1_LOW_INT_ENA_M (BIT(26))
#define APB_SARADC_THRES1_LOW_INT_ENA_V 0x1
#define APB_SARADC_THRES1_LOW_INT_ENA_S 26
-#define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x044)
+#define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x044)
/* APB_SARADC_ADC1_DONE_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */
/* description: */
-#define APB_SARADC_ADC1_DONE_INT_RAW (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_RAW (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_RAW_M (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_RAW_V 0x1
#define APB_SARADC_ADC1_DONE_INT_RAW_S 31
@@ -582,7 +582,7 @@
/* description: */
-#define APB_SARADC_ADC2_DONE_INT_RAW (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_RAW (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_RAW_M (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_RAW_V 0x1
#define APB_SARADC_ADC2_DONE_INT_RAW_S 30
@@ -591,7 +591,7 @@
/* description: */
-#define APB_SARADC_THRES0_HIGH_INT_RAW (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_RAW (BIT(29))
#define APB_SARADC_THRES0_HIGH_INT_RAW_M (BIT(29))
#define APB_SARADC_THRES0_HIGH_INT_RAW_V 0x1
#define APB_SARADC_THRES0_HIGH_INT_RAW_S 29
@@ -600,7 +600,7 @@
/* description: */
-#define APB_SARADC_THRES1_HIGH_INT_RAW (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_RAW (BIT(28))
#define APB_SARADC_THRES1_HIGH_INT_RAW_M (BIT(28))
#define APB_SARADC_THRES1_HIGH_INT_RAW_V 0x1
#define APB_SARADC_THRES1_HIGH_INT_RAW_S 28
@@ -609,7 +609,7 @@
/* description: */
-#define APB_SARADC_THRES0_LOW_INT_RAW (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_RAW (BIT(27))
#define APB_SARADC_THRES0_LOW_INT_RAW_M (BIT(27))
#define APB_SARADC_THRES0_LOW_INT_RAW_V 0x1
#define APB_SARADC_THRES0_LOW_INT_RAW_S 27
@@ -618,7 +618,7 @@
/* description: */
-#define APB_SARADC_THRES1_LOW_INT_RAW (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_RAW (BIT(26))
#define APB_SARADC_THRES1_LOW_INT_RAW_M (BIT(26))
#define APB_SARADC_THRES1_LOW_INT_RAW_V 0x1
#define APB_SARADC_THRES1_LOW_INT_RAW_S 26
@@ -629,7 +629,7 @@
/* description: */
-#define APB_SARADC_ADC1_DONE_INT_ST (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_ST (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_ST_M (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_ST_V 0x1
#define APB_SARADC_ADC1_DONE_INT_ST_S 31
@@ -638,7 +638,7 @@
/* description: */
-#define APB_SARADC_ADC2_DONE_INT_ST (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_ST (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_ST_M (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_ST_V 0x1
#define APB_SARADC_ADC2_DONE_INT_ST_S 30
@@ -647,7 +647,7 @@
/* description: */
-#define APB_SARADC_THRES0_HIGH_INT_ST (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_ST (BIT(29))
#define APB_SARADC_THRES0_HIGH_INT_ST_M (BIT(29))
#define APB_SARADC_THRES0_HIGH_INT_ST_V 0x1
#define APB_SARADC_THRES0_HIGH_INT_ST_S 29
@@ -656,7 +656,7 @@
/* description: */
-#define APB_SARADC_THRES1_HIGH_INT_ST (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_ST (BIT(28))
#define APB_SARADC_THRES1_HIGH_INT_ST_M (BIT(28))
#define APB_SARADC_THRES1_HIGH_INT_ST_V 0x1
#define APB_SARADC_THRES1_HIGH_INT_ST_S 28
@@ -665,7 +665,7 @@
/* description: */
-#define APB_SARADC_THRES0_LOW_INT_ST (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_ST (BIT(27))
#define APB_SARADC_THRES0_LOW_INT_ST_M (BIT(27))
#define APB_SARADC_THRES0_LOW_INT_ST_V 0x1
#define APB_SARADC_THRES0_LOW_INT_ST_S 27
@@ -674,7 +674,7 @@
/* description: */
-#define APB_SARADC_THRES1_LOW_INT_ST (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_ST (BIT(26))
#define APB_SARADC_THRES1_LOW_INT_ST_M (BIT(26))
#define APB_SARADC_THRES1_LOW_INT_ST_V 0x1
#define APB_SARADC_THRES1_LOW_INT_ST_S 26
@@ -685,7 +685,7 @@
/* description: */
-#define APB_SARADC_ADC1_DONE_INT_CLR (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_CLR (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_CLR_M (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_CLR_V 0x1
#define APB_SARADC_ADC1_DONE_INT_CLR_S 31
@@ -694,7 +694,7 @@
/* description: */
-#define APB_SARADC_ADC2_DONE_INT_CLR (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_CLR (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_CLR_M (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_CLR_V 0x1
#define APB_SARADC_ADC2_DONE_INT_CLR_S 30
@@ -703,7 +703,7 @@
/* description: */
-#define APB_SARADC_THRES0_HIGH_INT_CLR (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_CLR (BIT(29))
#define APB_SARADC_THRES0_HIGH_INT_CLR_M (BIT(29))
#define APB_SARADC_THRES0_HIGH_INT_CLR_V 0x1
#define APB_SARADC_THRES0_HIGH_INT_CLR_S 29
@@ -712,7 +712,7 @@
/* description: */
-#define APB_SARADC_THRES1_HIGH_INT_CLR (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_CLR (BIT(28))
#define APB_SARADC_THRES1_HIGH_INT_CLR_M (BIT(28))
#define APB_SARADC_THRES1_HIGH_INT_CLR_V 0x1
#define APB_SARADC_THRES1_HIGH_INT_CLR_S 28
@@ -721,7 +721,7 @@
/* description: */
-#define APB_SARADC_THRES0_LOW_INT_CLR (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_CLR (BIT(27))
#define APB_SARADC_THRES0_LOW_INT_CLR_M (BIT(27))
#define APB_SARADC_THRES0_LOW_INT_CLR_V 0x1
#define APB_SARADC_THRES0_LOW_INT_CLR_S 27
@@ -730,7 +730,7 @@
/* description: */
-#define APB_SARADC_THRES1_LOW_INT_CLR (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_CLR (BIT(26))
#define APB_SARADC_THRES1_LOW_INT_CLR_M (BIT(26))
#define APB_SARADC_THRES1_LOW_INT_CLR_V 0x1
#define APB_SARADC_THRES1_LOW_INT_CLR_S 26
@@ -741,7 +741,7 @@
/* description: enable apb_adc use spi_dma */
-#define APB_SARADC_APB_ADC_TRANS (BIT(31))
+#define APB_SARADC_APB_ADC_TRANS (BIT(31))
#define APB_SARADC_APB_ADC_TRANS_M (BIT(31))
#define APB_SARADC_APB_ADC_TRANS_V 0x1
#define APB_SARADC_APB_ADC_TRANS_S 31
@@ -750,7 +750,7 @@
/* description: reset_apb_adc_state */
-#define APB_SARADC_APB_ADC_RESET_FSM (BIT(30))
+#define APB_SARADC_APB_ADC_RESET_FSM (BIT(30))
#define APB_SARADC_APB_ADC_RESET_FSM_M (BIT(30))
#define APB_SARADC_APB_ADC_RESET_FSM_V 0x1
#define APB_SARADC_APB_ADC_RESET_FSM_S 30
@@ -759,7 +759,7 @@
/* description: the dma_in_suc_eof gen when sample cnt = spi_eof_num */
-#define APB_SARADC_APB_ADC_EOF_NUM 0x0000FFFF
+#define APB_SARADC_APB_ADC_EOF_NUM 0x0000FFFF
#define APB_SARADC_APB_ADC_EOF_NUM_M
((APB_SARADC_APB_ADC_EOF_NUM_V)<<(APB_SARADC_APB_ADC_EOF_NUM_S))
#define APB_SARADC_APB_ADC_EOF_NUM_V 0xFFFF
#define APB_SARADC_APB_ADC_EOF_NUM_S 0
@@ -770,7 +770,7 @@
/* description: Set this bit to enable clk_apll */
-#define APB_SARADC_CLK_SEL 0x00000003
+#define APB_SARADC_CLK_SEL 0x00000003
#define APB_SARADC_CLK_SEL_M ((APB_SARADC_CLK_SEL_V)<<(APB_SARADC_CLK_SEL_S))
#define APB_SARADC_CLK_SEL_V 0x3
#define APB_SARADC_CLK_SEL_S 21
@@ -779,7 +779,7 @@
/* description: */
-#define APB_SARADC_CLK_EN (BIT(20))
+#define APB_SARADC_CLK_EN (BIT(20))
#define APB_SARADC_CLK_EN_M (BIT(20))
#define APB_SARADC_CLK_EN_V 0x1
#define APB_SARADC_CLK_EN_S 20
@@ -788,7 +788,7 @@
/* description: Fractional clock divider denominator value */
-#define APB_SARADC_CLKM_DIV_A 0x0000003F
+#define APB_SARADC_CLKM_DIV_A 0x0000003F
#define APB_SARADC_CLKM_DIV_A_M
((APB_SARADC_CLKM_DIV_A_V)<<(APB_SARADC_CLKM_DIV_A_S))
#define APB_SARADC_CLKM_DIV_A_V 0x3F
#define APB_SARADC_CLKM_DIV_A_S 14
@@ -797,7 +797,7 @@
/* description: Fractional clock divider numerator value */
-#define APB_SARADC_CLKM_DIV_B 0x0000003F
+#define APB_SARADC_CLKM_DIV_B 0x0000003F
#define APB_SARADC_CLKM_DIV_B_M
((APB_SARADC_CLKM_DIV_B_V)<<(APB_SARADC_CLKM_DIV_B_S))
#define APB_SARADC_CLKM_DIV_B_V 0x3F
#define APB_SARADC_CLKM_DIV_B_S 8
@@ -806,7 +806,7 @@
/* description: Integral I2S clock divider value */
-#define APB_SARADC_CLKM_DIV_NUM 0x000000FF
+#define APB_SARADC_CLKM_DIV_NUM 0x000000FF
#define APB_SARADC_CLKM_DIV_NUM_M
((APB_SARADC_CLKM_DIV_NUM_V)<<(APB_SARADC_CLKM_DIV_NUM_S))
#define APB_SARADC_CLKM_DIV_NUM_V 0xFF
#define APB_SARADC_CLKM_DIV_NUM_S 0
@@ -817,7 +817,7 @@
/* description: */
-#define APB_SARADC_TSENS_PU (BIT(22))
+#define APB_SARADC_TSENS_PU (BIT(22))
#define APB_SARADC_TSENS_PU_M (BIT(22))
#define APB_SARADC_TSENS_PU_V 0x1
#define APB_SARADC_TSENS_PU_S 22
@@ -826,7 +826,7 @@
/* description: */
-#define APB_SARADC_TSENS_CLK_DIV 0x000000FF
+#define APB_SARADC_TSENS_CLK_DIV 0x000000FF
#define APB_SARADC_TSENS_CLK_DIV_M
((APB_SARADC_TSENS_CLK_DIV_V)<<(APB_SARADC_TSENS_CLK_DIV_S))
#define APB_SARADC_TSENS_CLK_DIV_V 0xFF
#define APB_SARADC_TSENS_CLK_DIV_S 14
@@ -835,7 +835,7 @@
/* description: */
-#define APB_SARADC_TSENS_IN_INV (BIT(13))
+#define APB_SARADC_TSENS_IN_INV (BIT(13))
#define APB_SARADC_TSENS_IN_INV_M (BIT(13))
#define APB_SARADC_TSENS_IN_INV_V 0x1
#define APB_SARADC_TSENS_IN_INV_S 13
@@ -844,7 +844,7 @@
/* description: */
-#define APB_SARADC_TSENS_OUT 0x000000FF
+#define APB_SARADC_TSENS_OUT 0x000000FF
#define APB_SARADC_TSENS_OUT_M
((APB_SARADC_TSENS_OUT_V)<<(APB_SARADC_TSENS_OUT_S))
#define APB_SARADC_TSENS_OUT_V 0xFF
#define APB_SARADC_TSENS_OUT_S 0
@@ -855,7 +855,7 @@
/* description: */
-#define APB_SARADC_TSENS_CLK_SEL (BIT(15))
+#define APB_SARADC_TSENS_CLK_SEL (BIT(15))
#define APB_SARADC_TSENS_CLK_SEL_M (BIT(15))
#define APB_SARADC_TSENS_CLK_SEL_V 0x1
#define APB_SARADC_TSENS_CLK_SEL_S 15
@@ -864,7 +864,7 @@
/* description: */
-#define APB_SARADC_TSENS_CLK_INV (BIT(14))
+#define APB_SARADC_TSENS_CLK_INV (BIT(14))
#define APB_SARADC_TSENS_CLK_INV_M (BIT(14))
#define APB_SARADC_TSENS_CLK_INV_V 0x1
#define APB_SARADC_TSENS_CLK_INV_S 14
@@ -873,7 +873,7 @@
/* description: */
-#define APB_SARADC_TSENS_XPD_FORCE 0x00000003
+#define APB_SARADC_TSENS_XPD_FORCE 0x00000003
#define APB_SARADC_TSENS_XPD_FORCE_M
((APB_SARADC_TSENS_XPD_FORCE_V)<<(APB_SARADC_TSENS_XPD_FORCE_S))
#define APB_SARADC_TSENS_XPD_FORCE_V 0x3
#define APB_SARADC_TSENS_XPD_FORCE_S 12
@@ -882,7 +882,7 @@
/* description: */
-#define APB_SARADC_TSENS_XPD_WAIT 0x00000FFF
+#define APB_SARADC_TSENS_XPD_WAIT 0x00000FFF
#define APB_SARADC_TSENS_XPD_WAIT_M
((APB_SARADC_TSENS_XPD_WAIT_V)<<(APB_SARADC_TSENS_XPD_WAIT_S))
#define APB_SARADC_TSENS_XPD_WAIT_V 0xFFF
#define APB_SARADC_TSENS_XPD_WAIT_S 0
@@ -893,7 +893,7 @@
/* description: */
-#define APB_SARADC_CALI_CFG 0x0001FFFF
+#define APB_SARADC_CALI_CFG 0x0001FFFF
#define APB_SARADC_CALI_CFG_M
((APB_SARADC_CALI_CFG_V)<<(APB_SARADC_CALI_CFG_S))
#define APB_SARADC_CALI_CFG_V 0x1FFFF
#define APB_SARADC_CALI_CFG_S 0
@@ -904,7 +904,7 @@
/* description: */
-#define APB_SARADC_DATE 0xFFFFFFFF
+#define APB_SARADC_DATE 0xFFFFFFFF
#define APB_SARADC_DATE_M ((APB_SARADC_DATE_V)<<(APB_SARADC_DATE_S))
#define APB_SARADC_DATE_V 0xFFFFFFFF
#define APB_SARADC_DATE_S 0
diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_usb_serial_jtag.h
b/arch/risc-v/src/esp32c3/hardware/esp32c3_usb_serial_jtag.h
index d1dcba4a90..3295e07fbf 100644
--- a/arch/risc-v/src/esp32c3/hardware/esp32c3_usb_serial_jtag.h
+++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_usb_serial_jtag.h
@@ -31,10 +31,10 @@
* Pre-processor Definitions
****************************************************************************/
-/** Configuration Registers */
+/* Configuration Registers */
-/** USB_SERIAL_JTAG_EP1_REG register
- * USB_SERIAL_JTAG_EP1_REG.
+/* USB_SERIAL_JTAG_EP1_REG register
+ * USB_SERIAL_JTAG_EP1_REG.
*/
#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0)
@@ -55,8 +55,8 @@
#define USB_SERIAL_JTAG_RDWR_BYTE_V 0x000000ff
#define USB_SERIAL_JTAG_RDWR_BYTE_S 0
-/** USB_SERIAL_JTAG_CONF0_REG register
- * USB_SERIAL_JTAG_CONF0_REG.
+/* USB_SERIAL_JTAG_CONF0_REG register
+ * USB_SERIAL_JTAG_CONF0_REG.
*/
#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18)
@@ -191,8 +191,8 @@
#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V 0x00000001
#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S 14
-/** USB_SERIAL_JTAG_TEST_REG register
- * USB_SERIAL_JTAG_TEST_REG.
+/* USB_SERIAL_JTAG_TEST_REG register
+ * USB_SERIAL_JTAG_TEST_REG.
*/
#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c)
@@ -237,8 +237,8 @@
#define USB_SERIAL_JTAG_TEST_TX_DM_V 0x00000001
#define USB_SERIAL_JTAG_TEST_TX_DM_S 3
-/** USB_SERIAL_JTAG_MISC_CONF_REG register
- * USB_SERIAL_JTAG_MISC_CONF_REG.
+/* USB_SERIAL_JTAG_MISC_CONF_REG register
+ * USB_SERIAL_JTAG_MISC_CONF_REG.
*/
#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44)
@@ -254,8 +254,8 @@
#define USB_SERIAL_JTAG_CLK_EN_V 0x00000001
#define USB_SERIAL_JTAG_CLK_EN_S 0
-/** USB_SERIAL_JTAG_MEM_CONF_REG register
- * USB_SERIAL_JTAG_MEM_CONF_REG.
+/* USB_SERIAL_JTAG_MEM_CONF_REG register
+ * USB_SERIAL_JTAG_MEM_CONF_REG.
*/
#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48)
@@ -280,10 +280,10 @@
#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V 0x00000001
#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S 1
-/** Status Registers */
+/* Status Registers */
-/** USB_SERIAL_JTAG_EP1_CONF_REG register
- * USB_SERIAL_JTAG_EP1_CONF_REG.
+/* USB_SERIAL_JTAG_EP1_CONF_REG register
+ * USB_SERIAL_JTAG_EP1_CONF_REG.
*/
#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4)
@@ -321,8 +321,8 @@
#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V 0x00000001
#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S 2
-/** USB_SERIAL_JTAG_JFIFO_ST_REG register
- * USB_SERIAL_JTAG_JFIFO_ST_REG.
+/* USB_SERIAL_JTAG_JFIFO_ST_REG register
+ * USB_SERIAL_JTAG_JFIFO_ST_REG.
*/
#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20)
@@ -406,8 +406,8 @@
#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V 0x00000001
#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S 9
-/** USB_SERIAL_JTAG_FRAM_NUM_REG register
- * USB_SERIAL_JTAG_FRAM_NUM_REG.
+/* USB_SERIAL_JTAG_FRAM_NUM_REG register
+ * USB_SERIAL_JTAG_FRAM_NUM_REG.
*/
#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24)
@@ -422,8 +422,8 @@
#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V 0x000007ff
#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S 0
-/** USB_SERIAL_JTAG_IN_EP0_ST_REG register
- * USB_SERIAL_JTAG_IN_EP0_ST_REG.
+/* USB_SERIAL_JTAG_IN_EP0_ST_REG register
+ * USB_SERIAL_JTAG_IN_EP0_ST_REG.
*/
#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28)
@@ -455,8 +455,8 @@
#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V 0x0000007f
#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S 9
-/** USB_SERIAL_JTAG_IN_EP1_ST_REG register
- * USB_SERIAL_JTAG_IN_EP1_ST_REG.
+/* USB_SERIAL_JTAG_IN_EP1_ST_REG register
+ * USB_SERIAL_JTAG_IN_EP1_ST_REG.
*/
#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c)
@@ -489,8 +489,8 @@
#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V 0x0000007f
#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S 9
-/** USB_SERIAL_JTAG_IN_EP2_ST_REG register
- * USB_SERIAL_JTAG_IN_EP2_ST_REG.
+/* USB_SERIAL_JTAG_IN_EP2_ST_REG register
+ * USB_SERIAL_JTAG_IN_EP2_ST_REG.
*/
#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30)
@@ -525,8 +525,8 @@
#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V 0x0000007f
#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S 9
-/** USB_SERIAL_JTAG_IN_EP3_ST_REG register
- * USB_SERIAL_JTAG_IN_EP3_ST_REG.
+/* USB_SERIAL_JTAG_IN_EP3_ST_REG register
+ * USB_SERIAL_JTAG_IN_EP3_ST_REG.
*/
#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34)
@@ -561,8 +561,8 @@
#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V 0x0000007f
#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S 9
-/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register
- * USB_SERIAL_JTAG_OUT_EP0_ST_REG.
+/* USB_SERIAL_JTAG_OUT_EP0_ST_REG register
+ * USB_SERIAL_JTAG_OUT_EP0_ST_REG.
*/
#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38)
@@ -599,8 +599,8 @@
#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V 0x0000007f
#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S 9
-/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register
- * USB_SERIAL_JTAG_OUT_EP1_ST_REG.
+/* USB_SERIAL_JTAG_OUT_EP1_ST_REG register
+ * USB_SERIAL_JTAG_OUT_EP1_ST_REG.
*/
#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c)
@@ -647,8 +647,8 @@
#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V 0x0000007f
#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S 16
-/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register
- * USB_SERIAL_JTAG_OUT_EP2_ST_REG.
+/* USB_SERIAL_JTAG_OUT_EP2_ST_REG register
+ * USB_SERIAL_JTAG_OUT_EP2_ST_REG.
*/
#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40)
@@ -685,10 +685,10 @@
#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V 0x0000007f
#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S 9
-/** Interrupt Registers */
+/* Interrupt Registers */
-/** USB_SERIAL_JTAG_INT_RAW_REG register
- * USB_SERIAL_JTAG_INT_RAW_REG.
+/* USB_SERIAL_JTAG_INT_RAW_REG register
+ * USB_SERIAL_JTAG_INT_RAW_REG.
*/
#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8)
@@ -824,8 +824,8 @@
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V 0x00000001
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S 11
-/** USB_SERIAL_JTAG_INT_ST_REG register
- * USB_SERIAL_JTAG_INT_ST_REG.
+/* USB_SERIAL_JTAG_INT_ST_REG register
+ * USB_SERIAL_JTAG_INT_ST_REG.
*/
#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc)
@@ -955,8 +955,8 @@
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x00000001
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11
-/** USB_SERIAL_JTAG_INT_ENA_REG register
- * USB_SERIAL_JTAG_INT_ENA_REG.
+/* USB_SERIAL_JTAG_INT_ENA_REG register
+ * USB_SERIAL_JTAG_INT_ENA_REG.
*/
#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10)
diff --git a/arch/sparc/include/sparc_v8/irq.h
b/arch/sparc/include/sparc_v8/irq.h
index ae3de3eac8..ce034e802d 100644
--- a/arch/sparc/include/sparc_v8/irq.h
+++ b/arch/sparc/include/sparc_v8/irq.h
@@ -100,6 +100,7 @@
#define XCPTCONTEXT_REGS (68)
#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS)
+
/* Alternate register names *************************************************/
/* %psr: processor status register */
@@ -211,69 +212,67 @@
#define SPARC_SWTRAP_SYSCALL 0
#define SPARC_SWTRAP_IRQDIS 9
#define SPARC_SWTRAP_IRQEN 10
-/**
- * PSR masks and starting bit positions
- *
+/* PSR masks and starting bit positions
* NOTE: Reserved bits are ignored.
*/
#define SPARC_PSR_CWP_MASK 0x00000007 /* bits 0 - 4 */
-/** This constant is a mask for the ET bits in the PSR. */
+/* This constant is a mask for the ET bits in the PSR. */
#define SPARC_PSR_ET_MASK 0x00000020 /* bit 5 */
-/** This constant is a mask for the PS bits in the PSR. */
+/* This constant is a mask for the PS bits in the PSR. */
#define SPARC_PSR_PS_MASK 0x00000040 /* bit 6 */
-/** This constant is a mask for the S bits in the PSR. */
+/* This constant is a mask for the S bits in the PSR. */
#define SPARC_PSR_S_MASK 0x00000080 /* bit 7 */
-/** This constant is a mask for the PIL bits in the PSR. */
+/* This constant is a mask for the PIL bits in the PSR. */
#define SPARC_PSR_PIL_MASK 0x00000F00 /* bits 8 - 11 */
-/** This constant is a mask for the EF bits in the PSR. */
+/* This constant is a mask for the EF bits in the PSR. */
#define SPARC_PSR_EF_MASK 0x00001000 /* bit 12 */
-/** This constant is a mask for the EC bits in the PSR. */
+/* This constant is a mask for the EC bits in the PSR. */
#define SPARC_PSR_EC_MASK 0x00002000 /* bit 13 */
-/** This constant is a mask for the ICC bits in the PSR. */
+/* This constant is a mask for the ICC bits in the PSR. */
#define SPARC_PSR_ICC_MASK 0x00F00000 /* bits 20 - 23 */
-/** This constant is a mask for the VER bits in the PSR. */
+/* This constant is a mask for the VER bits in the PSR. */
#define SPARC_PSR_VER_MASK 0x0F000000 /* bits 24 - 27 */
-/** This constant is a mask for the IMPL bits in the PSR. */
+/* This constant is a mask for the IMPL bits in the PSR. */
#define SPARC_PSR_IMPL_MASK 0xF0000000 /* bits 28 - 31 */
-/** This constant is the starting bit position of the CWP in the PSR. */
+/* This constant is the starting bit position of the CWP in the PSR. */
#define SPARC_PSR_CWP_BIT_POSITION 0 /* bits 0 - 4 */
-/** This constant is the starting bit position of the ET in the PSR. */
+/* This constant is the starting bit position of the ET in the PSR. */
#define SPARC_PSR_ET_BIT_POSITION 5 /* bit 5 */
-/** This constant is the starting bit position of the PS in the PSR. */
+/* This constant is the starting bit position of the PS in the PSR. */
#define SPARC_PSR_PS_BIT_POSITION 6 /* bit 6 */
-/** This constant is the starting bit position of the S in the PSR. */
+/* This constant is the starting bit position of the S in the PSR. */
#define SPARC_PSR_S_BIT_POSITION 7 /* bit 7 */
-/** This constant is the starting bit position of the PIL in the PSR. */
+/* This constant is the starting bit position of the PIL in the PSR. */
#define SPARC_PSR_PIL_BIT_POSITION 8 /* bits 8 - 11 */
-/** This constant is the starting bit position of the EF in the PSR. */
+/* This constant is the starting bit position of the EF in the PSR. */
#define SPARC_PSR_EF_BIT_POSITION 12 /* bit 12 */
-/** This constant is the starting bit position of the EC in the PSR. */
+/* This constant is the starting bit position of the EC in the PSR. */
#define SPARC_PSR_EC_BIT_POSITION 13 /* bit 13 */
-/** This constant is the starting bit position of the ICC in the PSR. */
+/* This constant is the starting bit position of the ICC in the PSR. */
#define SPARC_PSR_ICC_BIT_POSITION 20 /* bits 20 - 23 */
-/** This constant is the starting bit position of the VER in the PSR. */
+/* This constant is the starting bit position of the VER in the PSR. */
#define SPARC_PSR_VER_BIT_POSITION 24 /* bits 24 - 27 */
-/** This constant is the starting bit position of the IMPL in the PSR. */
+/* This constant is the starting bit position of the IMPL in the PSR. */
#define SPARC_PSR_IMPL_BIT_POSITION 28 /* bits 28 - 31 */
#define SPARC_NUMBER_OF_REGISTER_WINDOWS 8
@@ -296,20 +295,20 @@
#define CPU_STACK_FRAME_PAD0_OFFSET 0x5c
#define CPU_MINIMUM_STACK_FRAME_SIZE 0x60
-#define ISF_STACK_FRAME_OFFSET 0x00
-
-#define ISF_PSR_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x00)
-#define ISF_PC_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x04)
-#define ISF_NPC_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x08)
-#define ISF_G1_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x0c)
-#define ISF_G2_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x10)
-#define ISF_G4_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x18)
-#define ISF_G6_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x20)
-#define ISF_I0_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x28)
-#define ISF_I2_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x30)
-#define ISF_I4_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x38)
-#define ISF_I6_FP_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x40)
-#define ISF_Y_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x48)
+#define ISF_STACK_FRAME_OFFSET 0x00
+
+#define ISF_PSR_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x00)
+#define ISF_PC_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x04)
+#define ISF_NPC_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x08)
+#define ISF_G1_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x0c)
+#define ISF_G2_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x10)
+#define ISF_G4_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x18)
+#define ISF_G6_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x20)
+#define ISF_I0_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x28)
+#define ISF_I2_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x30)
+#define ISF_I4_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x38)
+#define ISF_I6_FP_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x40)
+#define ISF_Y_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x48)
#define ISF_FSR_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x4c)
@@ -335,46 +334,46 @@
#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE (CPU_MINIMUM_STACK_FRAME_SIZE +
0x50 + 32*4)
-/* Offsets of fields with Context_Control for assembly routines. */
+/* Offsets of fields with Context_Control for assembly routines. */
-/** This macro defines an offset into the context for use in assembly. */
+/* This macro defines an offset into the context for use in assembly. */
#define PSR_OFFSET 0x00
-/** This macro defines an offset into the context for use in assembly. */
+/* This macro defines an offset into the context for use in assembly. */
#define PC_OFFSET 0x04
-/** This macro defines an offset into the context for use in assembly. */
+/* This macro defines an offset into the context for use in assembly. */
#define NPC_OFFSET 0x08
-/** This macro defines an offset into the context for use in assembly. */
+/* This macro defines an offset into the context for use in assembly. */
#define G1_OFFSET 0x0C
-/** This macro defines an offset into the context for use in assembly. */
+/* This macro defines an offset into the context for use in assembly. */
#define G2_OFFSET 0x10
-/** This macro defines an offset into the context for use in assembly. */
+/* This macro defines an offset into the context for use in assembly. */
#define G3_OFFSET 0x14
-/** This macro defines an offset into the context for use in assembly. */
+/* This macro defines an offset into the context for use in assembly. */
#define G4_OFFSET 0x18
-/** This macro defines an offset into the context for use in assembly. */
+/* This macro defines an offset into the context for use in assembly. */
#define G5_OFFSET 0x1C
-/** This macro defines an offset into the context for use in assembly. */
+/* This macro defines an offset into the context for use in assembly. */
#define G6_OFFSET 0x20
-/** This macro defines an offset into the context for use in assembly. */
+/* This macro defines an offset into the context for use in assembly. */
#define G7_OFFSET 0x24
-/** This macro defines an offset into the context for use in assembly. */
+/* This macro defines an offset into the context for use in assembly. */
#define O0_OFFSET 0x28
-/** This macro defines an offset into the context for use in assembly. */
+/* This macro defines an offset into the context for use in assembly. */
#define O1_OFFSET 0x2C
-/** This macro defines an offset into the context for use in assembly. */
+/* This macro defines an offset into the context for use in assembly. */
#define O2_OFFSET 0x30
-/** This macro defines an offset into the context for use in assembly. */
+/* This macro defines an offset into the context for use in assembly. */
#define O3_OFFSET 0x34
-/** This macro defines an offset into the context for use in assembly. */
+/* This macro defines an offset into the context for use in assembly. */
#define O4_OFFSET 0x38
-/** This macro defines an offset into the context for use in assembly. */
+/* This macro defines an offset into the context for use in assembly. */
#define O5_OFFSET 0x3C
-/** This macro defines an offset into the context for use in assembly. */
+/* This macro defines an offset into the context for use in assembly. */
#define O6_SP_OFFSET 0x40
-/** This macro defines an offset into the context for use in assembly. */
+/* This macro defines an offset into the context for use in assembly. */
#define O7_OFFSET 0x44
#define Y_OFFSET 0x48
@@ -401,8 +400,7 @@
#define F30_OFFSET 0xc8
#if ( SPARC_HAS_FPU == 1 )
- /**
- * @brief Offset of the CPU_Per_CPU_control::fsr field relative to the
+ /* Offset of the CPU_Per_CPU_control::fsr field relative to the
* Per_CPU_Control begin.
*/
#define SPARC_PER_CPU_FSR_OFFSET 4
@@ -477,9 +475,7 @@ struct xcptcontext
* Inline functions
****************************************************************************/
-/**
- * @brief Macro to set the PSR.
- *
+/* Macro to set the PSR.
* This macro sets the PSR register to the value in @a _psr.
*/
#define sparc_set_psr( _psr ) \
@@ -490,9 +486,7 @@ struct xcptcontext
nop(); \
} while ( 0 )
-/**
- * @brief Macro to obtain the PSR.
- *
+/* Macro to obtain the PSR.
* This macro returns the current contents of the PSR register in @a _psr.
*/
#define sparc_get_psr( _psr ) \
@@ -501,17 +495,14 @@ struct xcptcontext
__asm__ volatile( "rd %%psr, %0" : "=r" (_psr) : "0" (_psr) ); \
} while ( 0 )
-/**
- * This macro is a standard nop instruction.
+/* This macro is a standard nop instruction.
*/
#define nop() \
do { \
__asm__ volatile ( "nop" ); \
} while ( 0 )
-/**
- * @brief Macro to obtain the TBR.
- *
+/* Macro to obtain the TBR.
* This macro returns the current contents of the TBR register in @a _tbr.
*/
#define sparc_get_tbr( _tbr ) \
@@ -520,9 +511,7 @@ struct xcptcontext
__asm__ volatile( "rd %%tbr, %0" : "=r" (_tbr) : "0" (_tbr) ); \
} while ( 0 )
-/**
- * @brief Macro to set the TBR.
- *
+/* Macro to set the TBR.
* This macro sets the TBR register to the value in @a _tbr.
*/
#define sparc_set_tbr( _tbr ) \
@@ -530,9 +519,7 @@ struct xcptcontext
__asm__ volatile( "wr %0, 0, %%tbr" : "=r" (_tbr) : "0" (_tbr) ); \
} while ( 0 )
-/**
- * @brief Macro to obtain the WIM.
- *
+/* Macro to obtain the WIM.
* This macro returns the current contents of the WIM field in @a _wim.
*/
#define sparc_get_wim( _wim ) \
@@ -540,9 +527,7 @@ struct xcptcontext
__asm__ volatile( "rd %%wim, %0" : "=r" (_wim) : "0" (_wim) ); \
} while ( 0 )
-/**
- * @brief Macro to set the WIM.
- *
+/* Macro to set the WIM.
* This macro sets the WIM field to the value in @a _wim.
*/
#define sparc_set_wim( _wim ) \
@@ -553,9 +538,7 @@ struct xcptcontext
nop(); \
} while ( 0 )
-/**
- * @brief Macro to obtain the Y register.
- *
+/* Macro to obtain the Y register.
* This macro returns the current contents of the Y register in @a _y.
*/
#define sparc_get_y( _y ) \
@@ -563,9 +546,7 @@ struct xcptcontext
__asm__ volatile( "rd %%y, %0" : "=r" (_y) : "0" (_y) ); \
} while ( 0 )
-/**
- * @brief Macro to set the Y register.
- *
+/* Macro to set the Y register.
* This macro sets the Y register to the value in @a _y.
*/
#define sparc_set_y( _y ) \
@@ -573,9 +554,7 @@ struct xcptcontext
__asm__ volatile( "wr %0, %%y" : "=r" (_y) : "0" (_y) ); \
} while ( 0 )
-/**
- * @brief Macro to obtain the asr17.
- *
+/* Macro to obtain the asr17.
* This macro returns the current contents of the asr17 register in _asr17.
*/
#define sparc_get_asr17( _asr17 ) \
@@ -584,11 +563,8 @@ struct xcptcontext
__asm__ volatile( "rd %%asr17, %0" : "=r" (_asr17) : "0" (_asr17) ); \
} while ( 0 )
-/**
- * @brief SPARC disable processor interrupts.
- *
+/* SPARC disable processor interrupts.
* This method is invoked to disable all maskable interrupts.
- *
* @return This method returns the entire PSR contents.
*/
@@ -599,11 +575,8 @@ static inline uint32_t sparc_disable_interrupts(void)
return psr;
}
-/**
- * @brief SPARC enable processor interrupts.
- *
+/* SPARC enable processor interrupts.
* This method is invoked to enable all maskable interrupts.
- *
* @param[in] psr is the PSR returned by @ref sparc_disable_interrupts.
*/
@@ -620,11 +593,8 @@ static inline void sparc_enable_interrupts(uint32_t psr)
__asm__ volatile ("ta %0\nnop\n" :: "i" (SPARC_SWTRAP_IRQEN), "r" (_psr));
}
-/**
- * @brief SPARC flash processor interrupts.
- *
+/* SPARC flash processor interrupts.
* This method is invoked to temporarily enable all maskable interrupts.
- *
* @param[in] _psr is the PSR returned by @ref sparc_disable_interrupts.
*/
@@ -634,11 +604,8 @@ static inline void sparc_enable_interrupts(uint32_t psr)
_psr = sparc_disable_interrupts(); \
} while ( 0 )
-/**
- * @brief SPARC obtain interrupt level.
- *
+/* SPARC obtain interrupt level.
* This method is invoked to obtain the current interrupt disable level.
- *
* @param[in] _level is the PSR returned by @ref sparc_disable_interrupts.
*/
diff --git a/arch/sparc/src/bm3803/bm3803-uart.h
b/arch/sparc/src/bm3803/bm3803-uart.h
index f3567c8fc4..a480ede2b5 100644
--- a/arch/sparc/src/bm3803/bm3803-uart.h
+++ b/arch/sparc/src/bm3803/bm3803-uart.h
@@ -67,16 +67,16 @@
/* Register Bit-Field Definitions *******************************************/
-#define ODD 1
+#define ODD 1
#define EVEN 0
-#define ON 1
+#define ON 1
#define OFF 0
#define NONE 2
#define RX 0
#define TX 1
#define RXTX 3
-/** Uart control list - Mask */
+/* Uart control list - Mask */
#define MSK_UART_ENABLE_RX 0x01
#define MSK_UART_ENABLE_TX 0x02
@@ -109,9 +109,9 @@
#define UART_BRG_MASK 0xfff
-#define uart1_set_baudrate(baudrate) (BM3803_REG.uart_scaler1 =
(uint32_t)((((BOARD_CPU_CLOCK*10)/(baudrate * 8))-5)/10))
+#define uart1_set_baudrate(baudrate) (BM3803_REG.uart_scaler1 =
(uint32_t)((((BOARD_CPU_CLOCK*10)/(baudrate * 8))-5)/10))
-#define uart1_parity_config(uart_parity) ( uart_parity == ODD
\
+#define uart1_parity_config(uart_parity) ( uart_parity == ODD
\
? (BM3803_REG.uart_ctrl1 =
((BM3803_REG.uart_ctrl1 | MSK_UART_PAR) | MSK_UART_ENABLE_PAR)) \
: ( uart_parity == EVEN
\
? (BM3803_REG.uart_ctrl1 =
((BM3803_REG.uart_ctrl1 & ~MSK_UART_PAR) | MSK_UART_ENABLE_PAR)) \
@@ -130,12 +130,12 @@
)
\
)
-#define uart1_flow_ctrl_config(uart_flow) ( uart_flow == ON
\
+#define uart1_flow_ctrl_config(uart_flow) ( uart_flow == ON
\
? (BM3803_REG.uart_ctrl1 |=
MSK_UART_ENABLE_FLOW) \
: (BM3803_REG.uart_ctrl1 &=
~MSK_UART_ENABLE_FLOW) \
)
-#define uart1_loopback_config(uart_loopb) ( uart_loopb == ON
\
+#define uart1_loopback_config(uart_loopb) ( uart_loopb == ON
\
? (BM3803_REG.uart_ctrl1 |=
MSK_UART_LOOPBACK) \
: (BM3803_REG.uart_ctrl1 &=
~MSK_UART_LOOPBACK) \
)
@@ -146,11 +146,11 @@
#define uart1_tx_ready() ((BM3803_REG.uart_status1 &
MSK_UART_TXH_READY) == MSK_UART_TXH_READY )
#define uart1_rx_ready() ((BM3803_REG.uart_status1 &
MSK_UART_DATA_READY) == MSK_UART_DATA_READY)
-#define uart1_send_byte(ch) (BM3803_REG.uart_data1 = ch)
+#define uart1_send_byte(ch) (BM3803_REG.uart_data1 = ch)
-#define uart2_set_baudrate(baudrate) (BM3803_REG.uart_scaler2 =
(((BOARD_CPU_CLOCK*10)/(baudrate*8))-5)/10)
+#define uart2_set_baudrate(baudrate) (BM3803_REG.uart_scaler2 =
(((BOARD_CPU_CLOCK*10)/(baudrate*8))-5)/10)
-#define uart2_parity_config(uart_parity) ( uart_parity == ODD
\
+#define uart2_parity_config(uart_parity) ( uart_parity == ODD
\
? (BM3803_REG.uart_ctrl2 =
((BM3803_REG.uart_ctrl2 | MSK_UART_PAR) | MSK_UART_ENABLE_PAR)) \
: ( uart_parity == EVEN
\
? (BM3803_REG.uart_ctrl2 =
((BM3803_REG.uart_ctrl2 & ~MSK_UART_PAR) | MSK_UART_ENABLE_PAR)) \
@@ -158,12 +158,12 @@
)
\
)
-#define uart2_flow_ctrl_config(uart_flow) ( uart_flow == ON
\
+#define uart2_flow_ctrl_config(uart_flow) ( uart_flow == ON
\
? (BM3803_REG.uart_ctrl2 |=
MSK_UART_ENABLE_FLOW) \
: (BM3803_REG.uart_ctrl2 &=
~MSK_UART_ENABLE_FLOW) \
)
-#define uart2_loopback_config(uart_loopb) ( uart_loopb == ON
\
+#define uart2_loopback_config(uart_loopb) ( uart_loopb == ON
\
? (BM3803_REG.uart_ctrl2 |=
MSK_UART_LOOPBACK) \
: (BM3803_REG.uart_ctrl2 &=
~MSK_UART_LOOPBACK) \
)
@@ -174,11 +174,11 @@
#define uart2_tx_ready() ((BM3803_REG.uart_status2 &
MSK_UART_TXH_READY) == MSK_UART_TXH_READY )
#define uart2_rx_ready() ((BM3803_REG.uart_status2 &
MSK_UART_DATA_READY) == MSK_UART_DATA_READY)
-#define uart2_send_byte(ch) (BM3803_REG.uart_data2 = ch)
+#define uart2_send_byte(ch) (BM3803_REG.uart_data2 = ch)
-#define uart3_set_baudrate(baudrate) (BM3803_REG.uart_scaler3 =
(((BOARD_CPU_CLOCK*10)/(baudrate*8))-5)/10)
+#define uart3_set_baudrate(baudrate) (BM3803_REG.uart_scaler3 =
(((BOARD_CPU_CLOCK*10)/(baudrate*8))-5)/10)
-#define uart3_parity_config(uart_parity) ( uart_parity == ODD
\
+#define uart3_parity_config(uart_parity) ( uart_parity == ODD
\
? (BM3803_REG.uart_ctrl3 =
((BM3803_REG.uart_ctrl3 | MSK_UART_PAR) | MSK_UART_ENABLE_PAR)) \
: ( uart_parity == EVEN
\
? (BM3803_REG.uart_ctrl3 =
((BM3803_REG.uart_ctrl3 & ~MSK_UART_PAR) | MSK_UART_ENABLE_PAR)) \
@@ -186,7 +186,7 @@
)
\
)
-#define uart3_flow_ctrl_config(uart_flow) ( uart_flow == ON
\
+#define uart3_flow_ctrl_config(uart_flow) ( uart_flow == ON
\
? (BM3803_REG.uart_ctrl3 |=
MSK_UART_ENABLE_FLOW) \
: (BM3803_REG.uart_ctrl3 &=
~MSK_UART_ENABLE_FLOW) \
)
@@ -202,7 +202,7 @@
#define uart3_tx_ready() ((BM3803_REG.uart_status3 &
MSK_UART_TXH_READY) == MSK_UART_TXH_READY )
#define uart3_rx_ready() ((BM3803_REG.uart_status3 &
MSK_UART_DATA_READY) == MSK_UART_DATA_READY)
-#define uart3_send_byte(ch) (BM3803_REG.uart_data3 = ch)
+#define uart3_send_byte(ch) (BM3803_REG.uart_data3 = ch)
/****************************************************************************
* Public Types
diff --git a/arch/sparc/src/s698pm/s698pm-uart.h
b/arch/sparc/src/s698pm/s698pm-uart.h
index 3ba70a2da3..deea27d6de 100644
--- a/arch/sparc/src/s698pm/s698pm-uart.h
+++ b/arch/sparc/src/s698pm/s698pm-uart.h
@@ -84,7 +84,7 @@
#define TX 1
#define RXTX 3
-/** Uart control list - Mask */
+/* Uart control list - Mask */
#define MSK_UART_ENABLE_RX 0x01
#define MSK_UART_ENABLE_TX 0x02
@@ -162,7 +162,7 @@
#define uart_tx_ready() ((S698PM_REG.uart_status1 &
UART_STA_TF) != UART_STA_TF)
#define uart_rx_ready() ((S698PM_REG.uart_status1 &
UART_STA_DR) == UART_STA_DR)
-#define uart_send_byte(ch) (S698PM_REG.uart_data1 = ch)
+#define uart_send_byte(ch) (S698PM_REG.uart_data1 = ch)
/****************************************************************************
* Public Types
diff --git a/arch/xtensa/src/esp32/esp32_spi_slave.c
b/arch/xtensa/src/esp32/esp32_spi_slave.c
index 24083ac26a..a452cc8c9b 100644
--- a/arch/xtensa/src/esp32/esp32_spi_slave.c
+++ b/arch/xtensa/src/esp32/esp32_spi_slave.c
@@ -755,7 +755,7 @@ static void esp32_spislv_rx(struct esp32_spislv_priv_s
*priv)
if (recv_n < priv->rxlen)
{
- /** If upper layer does not receive all data of receive
+ /* If upper layer does not receive all data of receive
* buffer, move the rest data to head of the buffer
*/
@@ -831,7 +831,7 @@ static int esp32_spislv_interrupt(int irq, void *context,
void *arg)
if (!priv->dma_chan)
{
- /** With DMA, software should copy data from register
+ /* With DMA, software should copy data from register
* to receive buffer
*/
diff --git a/arch/xtensa/src/esp32s3/esp32s3_psram_octal.c
b/arch/xtensa/src/esp32s3/esp32s3_psram_octal.c
index 4499a19962..92a9ef067b 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_psram_octal.c
+++ b/arch/xtensa/src/esp32s3/esp32s3_psram_octal.c
@@ -242,7 +242,7 @@ static void get_psram_reg(int spi_num, struct opi_psram_reg
*out_reg)
int dummy = OCT_PSRAM_RD_DUMMY_BITLEN;
int data_bit_len = 16;
- /** Read MR0~1 register */
+ /* Read MR0~1 register */
esp_rom_opiflash_exec_cmd(spi_num, mode,
OPI_PSRAM_REG_READ,
@@ -256,7 +256,7 @@ static void get_psram_reg(int spi_num, struct opi_psram_reg
*out_reg)
BIT(1),
false);
- /** Read MR2~3 register */
+ /* Read MR2~3 register */
esp_rom_opiflash_exec_cmd(spi_num, mode,
OPI_PSRAM_REG_READ,
@@ -270,7 +270,7 @@ static void get_psram_reg(int spi_num, struct opi_psram_reg
*out_reg)
BIT(1),
false);
- /** Read MR4 register */
+ /* Read MR4 register */
data_bit_len = 8;
esp_rom_opiflash_exec_cmd(spi_num, mode,
@@ -285,7 +285,7 @@ static void get_psram_reg(int spi_num, struct opi_psram_reg
*out_reg)
BIT(1),
false);
- /** Read MR8 register */
+ /* Read MR8 register */
esp_rom_opiflash_exec_cmd(spi_num, mode,
OPI_PSRAM_REG_READ,
@@ -365,8 +365,7 @@ static void print_psram_reg(const struct opi_psram_reg
*psram_reg)
static void init_cs_timing(void)
{
- /**
- * SPI0/1 share the cs_hold / cs_setup, cd_hold_time / cd_setup_time,
+ /* SPI0/1 share the cs_hold / cs_setup, cd_hold_time / cd_setup_time,
* cs_hold_delay registers for PSRAM, so we only need to set SPI0
* related registers here.
*/
@@ -383,7 +382,7 @@ static void init_cs_timing(void)
OCT_PSRAM_CS_SETUP_TIME,
SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S);
- /** CS1 high time */
+ /* CS1 high time */
SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(0),
SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_V,
@@ -432,7 +431,7 @@ static void init_psram_pins(void)
static void config_psram_spi_phases(void)
{
- /** Config Write CMD phase for SPI0 to access PSRAM */
+ /* Config Write CMD phase for SPI0 to access PSRAM */
SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0),
SPI_MEM_CACHE_SRAM_USR_WCMD_M);
@@ -445,7 +444,7 @@ static void config_psram_spi_phases(void)
OPI_PSRAM_SYNC_WRITE,
SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S);
- /** Config Read CMD phase for SPI0 to access PSRAM */
+ /* Config Read CMD phase for SPI0 to access PSRAM */
SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0),
SPI_MEM_CACHE_SRAM_USR_RCMD_M);
@@ -458,7 +457,7 @@ static void config_psram_spi_phases(void)
OPI_PSRAM_SYNC_READ,
SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S);
- /** Config ADDR phase */
+ /* Config ADDR phase */
SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0),
SPI_MEM_SRAM_ADDR_BITLEN_V,
@@ -467,7 +466,7 @@ static void config_psram_spi_phases(void)
SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0),
SPI_MEM_CACHE_USR_SCMD_4BYTE_M);
- /** Config RD/WR Dummy phase */
+ /* Config RD/WR Dummy phase */
SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0),
SPI_MEM_USR_RD_SRAM_DUMMY_M |
@@ -518,12 +517,10 @@ static void config_psram_spi_phases(void)
static inline void spi_flash_set_rom_required_regs(void)
{
#ifdef CONFIG_ESP32S3_FLASH_MODE_OCT
- /**
- * Disable the variable dummy mode when doing timing tuning.
- *
+
+ /* Disable the variable dummy mode when doing timing tuning.
* STR /DTR mode setting is done every time when
* "esp_rom_opiflash_exec_cmd" is called.
- *
* Add any registers that are not set in ROM SPI flash functions here
* in the future.
*/
@@ -549,8 +546,7 @@ static inline void spi_flash_set_rom_required_regs(void)
static inline void flash_set_vendor_required_regs(void)
{
#ifdef CONFIG_ESP32S3_FLASH_MODE_OCT
- /**
- * Set MSPI specifical configuration,
+ /* Set MSPI specifical configuration,
* "esp32s3_bsp_opiflash_set_required_regs" is board defined function.
*/
@@ -561,7 +557,7 @@ static inline void flash_set_vendor_required_regs(void)
1,
SPI_MEM_CACHE_USR_CMD_4BYTE_S);
#else
- /** Restore MSPI registers after Octal PSRAM initialization. */
+ /* Restore MSPI registers after Octal PSRAM initialization. */
SET_PERI_REG_BITS(SPI_MEM_CACHE_FCTRL_REG(1),
SPI_MEM_CACHE_USR_CMD_4BYTE_V,
@@ -584,16 +580,16 @@ int IRAM_ATTR psram_enable(int mode, int vaddrmode)
init_psram_pins();
init_cs_timing();
- /** enter MSPI slow mode to init PSRAM device registers */
+ /* enter MSPI slow mode to init PSRAM device registers */
esp32s3_spi_timing_set_mspi_low_speed(true);
- /** set to variable dummy mode */
+ /* set to variable dummy mode */
SET_PERI_REG_MASK(SPI_MEM_DDR_REG(1), SPI_MEM_SPI_FMEM_VAR_DUMMY);
esp_rom_spi_set_dtr_swap_mode(1, false, false);
- /** Set PSRAM read latency and drive strength */
+ /* Set PSRAM read latency and drive strength */
psram_reg.mr0.lt = 1;
psram_reg.mr0.read_latency = 2;
@@ -613,16 +609,13 @@ int IRAM_ATTR psram_enable(int mode, int vaddrmode)
esp32s3_spi_timing_set_mspi_high_speed(true);
- /**
- * Tuning may change SPI1 regs, whereas legacy spi_flash APIs rely on
+ /* Tuning may change SPI1 regs, whereas legacy spi_flash APIs rely on
* these regs. This function is to restore SPI1 init state.
*/
spi_flash_set_rom_required_regs();
- /**
- * Flash chip requires MSPI specifically, call this function to set them
- */
+ /* Flash chip requires MSPI specifically, call this function to set them */
flash_set_vendor_required_regs();
@@ -637,8 +630,7 @@ int psram_get_physical_size(uint32_t *out_size_bytes)
return g_psram_size > 0 ? OK : -EINVAL;
}
-/* This function is to get the available physical psram size in bytes.
- */
+/* This function is to get the available physical psram size in bytes. */
int psram_get_available_size(uint32_t *out_size_bytes)
{
diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_usb_serial_jtag.h
b/arch/xtensa/src/esp32s3/hardware/esp32s3_usb_serial_jtag.h
index 7b351b327f..1286d57af1 100644
--- a/arch/xtensa/src/esp32s3/hardware/esp32s3_usb_serial_jtag.h
+++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_usb_serial_jtag.h
@@ -31,10 +31,10 @@
* Pre-processor Definitions
****************************************************************************/
-/** Configuration Registers */
+/* Configuration Registers */
-/** USB_SERIAL_JTAG_EP1_REG register
- * USB_SERIAL_JTAG_EP1_REG.
+/* USB_SERIAL_JTAG_EP1_REG register
+ * USB_SERIAL_JTAG_EP1_REG.
*/
#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_DEVICE_BASE + 0x0)
@@ -55,7 +55,7 @@
#define USB_SERIAL_JTAG_RDWR_BYTE_V 0x000000ff
#define USB_SERIAL_JTAG_RDWR_BYTE_S 0
-/** USB_SERIAL_JTAG_CONF0_REG register
+/* USB_SERIAL_JTAG_CONF0_REG register
* USB_SERIAL_JTAG_CONF0_REG.
*/
@@ -191,8 +191,8 @@
#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V 0x00000001
#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S 14
-/** USB_SERIAL_JTAG_TEST_REG register
- * USB_SERIAL_JTAG_TEST_REG.
+/* USB_SERIAL_JTAG_TEST_REG register
+ * USB_SERIAL_JTAG_TEST_REG.
*/
#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_DEVICE_BASE + 0x1c)
@@ -237,8 +237,8 @@
#define USB_SERIAL_JTAG_TEST_TX_DM_V 0x00000001
#define USB_SERIAL_JTAG_TEST_TX_DM_S 3
-/** USB_SERIAL_JTAG_MISC_CONF_REG register
- * USB_SERIAL_JTAG_MISC_CONF_REG.
+/* USB_SERIAL_JTAG_MISC_CONF_REG register
+ * USB_SERIAL_JTAG_MISC_CONF_REG.
*/
#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x44)
@@ -254,8 +254,8 @@
#define USB_SERIAL_JTAG_CLK_EN_V 0x00000001
#define USB_SERIAL_JTAG_CLK_EN_S 0
-/** USB_SERIAL_JTAG_MEM_CONF_REG register
- * USB_SERIAL_JTAG_MEM_CONF_REG.
+/* USB_SERIAL_JTAG_MEM_CONF_REG register
+ * USB_SERIAL_JTAG_MEM_CONF_REG.
*/
#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x48)
@@ -280,10 +280,10 @@
#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V 0x00000001
#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S 1
-/** Status Registers */
+/* Status Registers */
-/** USB_SERIAL_JTAG_EP1_CONF_REG register
- * USB_SERIAL_JTAG_EP1_CONF_REG.
+/* USB_SERIAL_JTAG_EP1_CONF_REG register
+ * USB_SERIAL_JTAG_EP1_CONF_REG.
*/
#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x4)
@@ -321,8 +321,8 @@
#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V 0x00000001
#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S 2
-/** USB_SERIAL_JTAG_JFIFO_ST_REG register
- * USB_SERIAL_JTAG_JFIFO_ST_REG.
+/* USB_SERIAL_JTAG_JFIFO_ST_REG register
+ * USB_SERIAL_JTAG_JFIFO_ST_REG.
*/
#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_DEVICE_BASE + 0x20)
@@ -406,8 +406,8 @@
#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V 0x00000001
#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S 9
-/** USB_SERIAL_JTAG_FRAM_NUM_REG register
- * USB_SERIAL_JTAG_FRAM_NUM_REG.
+/* USB_SERIAL_JTAG_FRAM_NUM_REG register
+ * USB_SERIAL_JTAG_FRAM_NUM_REG.
*/
#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_DEVICE_BASE + 0x24)
@@ -422,8 +422,8 @@
#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V 0x000007ff
#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S 0
-/** USB_SERIAL_JTAG_IN_EP0_ST_REG register
- * USB_SERIAL_JTAG_IN_EP0_ST_REG.
+/* USB_SERIAL_JTAG_IN_EP0_ST_REG register
+ * USB_SERIAL_JTAG_IN_EP0_ST_REG.
*/
#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x28)
@@ -455,8 +455,8 @@
#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V 0x0000007f
#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S 9
-/** USB_SERIAL_JTAG_IN_EP1_ST_REG register
- * USB_SERIAL_JTAG_IN_EP1_ST_REG.
+/* USB_SERIAL_JTAG_IN_EP1_ST_REG register
+ * USB_SERIAL_JTAG_IN_EP1_ST_REG.
*/
#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x2c)
@@ -489,8 +489,8 @@
#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V 0x0000007f
#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S 9
-/** USB_SERIAL_JTAG_IN_EP2_ST_REG register
- * USB_SERIAL_JTAG_IN_EP2_ST_REG.
+/* USB_SERIAL_JTAG_IN_EP2_ST_REG register
+ * USB_SERIAL_JTAG_IN_EP2_ST_REG.
*/
#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x30)
@@ -525,8 +525,8 @@
#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V 0x0000007f
#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S 9
-/** USB_SERIAL_JTAG_IN_EP3_ST_REG register
- * USB_SERIAL_JTAG_IN_EP3_ST_REG.
+/* USB_SERIAL_JTAG_IN_EP3_ST_REG register
+ * USB_SERIAL_JTAG_IN_EP3_ST_REG.
*/
#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_DEVICE_BASE + 0x34)
@@ -561,8 +561,8 @@
#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V 0x0000007f
#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S 9
-/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register
- * USB_SERIAL_JTAG_OUT_EP0_ST_REG.
+/* USB_SERIAL_JTAG_OUT_EP0_ST_REG register
+ * USB_SERIAL_JTAG_OUT_EP0_ST_REG.
*/
#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x38)
@@ -599,8 +599,8 @@
#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V 0x0000007f
#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S 9
-/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register
- * USB_SERIAL_JTAG_OUT_EP1_ST_REG.
+/* USB_SERIAL_JTAG_OUT_EP1_ST_REG register
+ * USB_SERIAL_JTAG_OUT_EP1_ST_REG.
*/
#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x3c)
@@ -647,8 +647,8 @@
#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V 0x0000007f
#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S 16
-/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register
- * USB_SERIAL_JTAG_OUT_EP2_ST_REG.
+/* USB_SERIAL_JTAG_OUT_EP2_ST_REG register
+ * USB_SERIAL_JTAG_OUT_EP2_ST_REG.
*/
#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x40)
@@ -685,10 +685,10 @@
#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V 0x0000007f
#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S 9
-/** Interrupt Registers */
+/* Interrupt Registers */
-/** USB_SERIAL_JTAG_INT_RAW_REG register
- * USB_SERIAL_JTAG_INT_RAW_REG.
+/* USB_SERIAL_JTAG_INT_RAW_REG register
+ * USB_SERIAL_JTAG_INT_RAW_REG.
*/
#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_DEVICE_BASE + 0x8)
@@ -824,8 +824,8 @@
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V 0x00000001
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S 11
-/** USB_SERIAL_JTAG_INT_ST_REG register
- * USB_SERIAL_JTAG_INT_ST_REG.
+/* USB_SERIAL_JTAG_INT_ST_REG register
+ * USB_SERIAL_JTAG_INT_ST_REG.
*/
#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_DEVICE_BASE + 0xc)
@@ -955,8 +955,8 @@
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x00000001
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11
-/** USB_SERIAL_JTAG_INT_ENA_REG register
- * USB_SERIAL_JTAG_INT_ENA_REG.
+/* USB_SERIAL_JTAG_INT_ENA_REG register
+ * USB_SERIAL_JTAG_INT_ENA_REG.
*/
#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_DEVICE_BASE + 0x10)
diff --git a/boards/arm/stm32/nucleo-l152re/src/stm32_ili93418b.c
b/boards/arm/stm32/nucleo-l152re/src/stm32_ili93418b.c
index 6f2b9d74d8..2b19edf4af 100644
--- a/boards/arm/stm32/nucleo-l152re/src/stm32_ili93418b.c
+++ b/boards/arm/stm32/nucleo-l152re/src/stm32_ili93418b.c
@@ -233,7 +233,7 @@ static inline void write_byte(uint8_t data)
LCD_WR_SET;
}
-/** references https://controllerstech.com/interface-tft-display-with-stm32/
+/* references https://controllerstech.com/interface-tft-display-with-stm32/
* #define READ() (((getreg32(STM32_GPIOA_IDR) & (1 << GPIO_PIN9)) >> 9) | \
* ((getreg32(STM32_GPIOC_IDR) & (1 << GPIO_PIN7)) >> 6) | \
* ((getreg32(STM32_GPIOA_IDR) & (1 << GPIO_PIN10)) >> 8) | \
@@ -304,13 +304,13 @@ static inline uint8_t read_byte(void)
static int stm32_ili93418b_recvblock(struct ili9341_lcd_s *lcd,
uint16_t *wd, uint16_t nwords)
{
- /** ili9341 uses a 18-bit pixel format packed in a 24-bit stream per pixel.
- * The following format is transmitted: RRRRRR00 GGGGGG00 BBBBBB00
- * Convert it to: RRRRRGGG GGGBBBBB
+ /* ili9341 uses a 18-bit pixel format packed in a 24-bit stream per pixel.
+ * The following format is transmitted: RRRRRR00 GGGGGG00 BBBBBB00
+ * Convert it to: RRRRRGGG GGGBBBBB
*/
- /** 8-bit parallel mode is enabled for pixel data operations.
- * Each pixel must be received by three read operations.
+ /* 8-bit parallel mode is enabled for pixel data operations.
+ * Each pixel must be received by three read operations.
*/
uint16_t *dest = (uint16_t *)wd;
diff --git a/drivers/audio/wm8994.c b/drivers/audio/wm8994.c
index 275666abcf..b3aefbccd3 100644
--- a/drivers/audio/wm8994.c
+++ b/drivers/audio/wm8994.c
@@ -1458,7 +1458,7 @@ static int wm8994_enqueuebuffer(FAR struct
audio_lowerhalf_s *dev,
return ret;
}
-/** Name: wm8994_cancelbuffer
+/* Name: wm8994_cancelbuffer
*
* Description: Called when an enqueued buffer is being cancelled.
*
diff --git a/drivers/audio/wm8994.h b/drivers/audio/wm8994.h
index f64667e8d1..e59e20cb49 100644
--- a/drivers/audio/wm8994.h
+++ b/drivers/audio/wm8994.h
@@ -545,8 +545,7 @@
#define WM8994_AIF3_TRI_NO (0)
/* AIF3 pins operate normally */
#define WM8994_AIF3_TRI_YES (WM8994_AIF3_TRI)
/* Tri-State all AIF3 interface pins */
-/* R21 (0x15) - Input Mixer (1)
- */
+/* R21 (0x15) - Input Mixer (1) */
/* Bits 0-5: Reserved */
#define WM8994_INPUTS_CLAMP (1 << 6)
/* Bit 6: Input pad VMID clamp */
@@ -560,8 +559,7 @@
#define WM8994_IN1RP_MIXINR_BOOST_P_15dB (WM8994_IN1RP_MIXINR_BOOST)
/* Maximu gain is +15dB */
/* Bits 9-15: Reserved */
-/* R24 (0x18) - Left Line Input 1&2 Volume
- */
+/* R24 (0x18) - Left Line Input 1&2 Volume */
#define WM8994_IN1L_VOL (0)
/* Bits 0-4: IN1L Volume */
#define WM8994_IN1L_VOL_MIN (0 << 0)
/* -16.5dB */
@@ -578,8 +576,7 @@
/* Bits 9-15: Reserved */
-/* R25 (0x19) - Left Line Input 3&4 Volume
- */
+/* R25 (0x19) - Left Line Input 3&4 Volume */
#define WM8994_IN2L_VOL_SHIFT (0)
/* Bits 0-4: IN2L Volume */
#define WM8994_IN2L_VOL_MIN (0 << WM8994_IN2L_VOL_SHIFT)
/* -16.5dB */
@@ -596,8 +593,7 @@
/* Bits 9-15: Reserved */
-/* R26 (0x1A) - Right Line Input 1&2 Volume
- */
+/* R26 (0x1A) - Right Line Input 1&2 Volume */
#define WM8994_IN1R_VOL_SHIFT (0)
/* Bits 0-4: IN1R Volume */
#define WM8994_IN1R_VOL_MIN (0 << WM8994_IN1R_VOL_SHIFT)
/* -16.5dB */
@@ -633,8 +629,7 @@
#define WM8994_IN2_VU (1 << 8)
/* Bit 8: Input PGA Voluem Update. Writing a 1 to this bit cause
IN2L and IN2R input PGA volumes to updated simultaneously */
#endif
-/* R28 (0x1C) - Left Output Volume
- */
+/* R28 (0x1C) - Left Output Volume */
#define WM8994_HPOUT1L_VOL_SHIFT (0)
/* Bits 0-5: HPOUT1LVOL (Left Headphone Output PGA) Volume */
#define WM8994_HPOUT1L_VOL_MIN (0 <<
WM8994_HPOUT1L_VOL_SHIFT) /* -57dB */
@@ -652,8 +647,7 @@
#define WM8994_HPOUT1_VU_ENABLED (1 <<
WM8994_HPOUT1_VU_SHIFT) /* Writing a 1 to this bit will update
HPOUT1LVOL and
* HPOUT1RVOL volumes simultaneously */
-/* R29 (0x1D) - Right Output Volume
- */
+/* R29 (0x1D) - Right Output Volume */
#define WM8994_HPOUT1R_VOL_SHIFT (0)
/* Bits 0-5: HPOUT1RVOL (Right Headphone Output PGA) Volume */
#define WM8994_HPOUT1R_VOL_MIN (0 <<
WM8994_HPOUT1R_VOL_SHIFT) /* -57dB */
@@ -708,23 +702,17 @@
/* R39 (0x27) - Speaker Volume Right
*/
-/* R40 (0x28) - Input Mixer (2)
- */
+/* R40 (0x28) - Input Mixer (2) */
-/* R41 (0x29) - Input Mixer (3)
- */
+/* R41 (0x29) - Input Mixer (3) */
-/* R42 (0x2A) - Input Mixer (4)
- */
+/* R42 (0x2A) - Input Mixer (4) */
-/* R43 (0x2B) - Input Mixer (5)
- */
+/* R43 (0x2B) - Input Mixer (5) */
-/* R44 (0x2C) - Input Mixer (6)
- */
+/* R44 (0x2C) - Input Mixer (6) */
-/* R45 (0x2D) - Output Mixer (1)
- */
+/* R45 (0x2D) - Output Mixer (1) */
#define WM8994_DAC1L_TO_MIXOUTL (1 << 0)
/* Bit 0: Left DAC1 to MIXOUTL Mute */
#define WM8994_DAC1L_TO_MIXOUTL_MUTE (0)
/* Mute */
@@ -755,8 +743,7 @@
#define WM8994_DAC1L_TO_HPOUT1L_DAC1L (WM8994_DAC1L_TO_HPOUT1L)
/* DAC1L */
/* Bits 9-15: Reserved */
-/* R46 (0x2E) - Output Mixer (2)
- */
+/* R46 (0x2E) - Output Mixer (2) */
#define WM8994_DAC1R_TO_MIXOUTR (1 << 0)
/* Bit 0: Right DAC1 to MIXOUTR Mute */
#define WM8994_DAC1R_TO_MIXOUTR_MUTE (0)
/* Mute */
@@ -786,29 +773,21 @@
#define WM8994_DAC1R_TO_HPOUT1R_MIXOUTL (0)
/* MIXOUTR */
#define WM8994_DAC1R_TO_HPOUT1R_DAC1L (WM8994_DAC1R_TO_HPOUT1R)
/* DAC1R */
-/* R47 (0x2F) - Output Mixer (3)
- */
+/* R47 (0x2F) - Output Mixer (3) */
-/* R48 (0x30) - Output Mixer (4)
- */
+/* R48 (0x30) - Output Mixer (4) */
-/* R49 (0x31) - Output Mixer (5)
- */
+/* R49 (0x31) - Output Mixer (5) */
-/* R50 (0x32) - Output Mixer (6)
- */
+/* R50 (0x32) - Output Mixer (6) */
-/* R51 (0x33) - HPOUT2 Mixer
- */
+/* R51 (0x33) - HPOUT2 Mixer */
-/* R52 (0x34) - Line Mixer (1)
- */
+/* R52 (0x34) - Line Mixer (1) */
-/* R53 (0x35) - Line Mixer (2)
- */
+/* R53 (0x35) - Line Mixer (2) */
-/* R54 (0x36) - Speaker Mixer
- */
+/* R54 (0x36) - Speaker Mixer */
#define WM8994_DAC2L_TO_SPKMIXL (1 << 9)
/* Bit 9: Left DAC2 to SPKMXL Mute */
#define WM8994_DAC2L_TO_SPKMIXL_MUTE (0)
/* Mute */
@@ -841,14 +820,11 @@
#define WM8994_DAC1R_TO_SPKMIXR_MUTE (0)
/* Mute */
#define WM8994_DAC1R_TO_SPKMIXR_UNMUTE (WM8994_DAC1R_TO_SPKMIXR)
/* Un-mute */
-/* R55 (0x37) - Additional Control
- */
+/* R55 (0x37) - Additional Control */
-/* R56 (0x38) - AntiPOP (1)
- */
+/* R56 (0x38) - AntiPOP (1) */
-/* R57 (0x39) - AntiPOP (2)
- */
+/* R57 (0x39) - AntiPOP (2) */
/* Bits 8-15: Reserved */
#define WM8994_MICB2_DISCH (1 << 8)
/* Bit 7: Microphone Bias 2 Discharge */
@@ -873,40 +849,31 @@
#define WM8994_VMID_RAMP_SOFT_SLOW_START (2 <<
WM8994_VMID_RAMP_SHIFT) /* Soft slow start */
#define WM8994_VMID_RAMP_SOFT_FAST_START (3 <<
WM8994_VMID_RAMP_SHIFT) /* Soft fast start */
-/* R58 (0x3A) - MICBIAS
- */
+/* R58 (0x3A) - MICBIAS */
-/* R59 (0x3B) - LDO 1
- */
+/* R59 (0x3B) - LDO 1 */
-/* R60 (0x3C) - LDO 2
- */
+/* R60 (0x3C) - LDO 2 */
-/* R61 (0x3D) - MICBIAS1
- */
+/* R61 (0x3D) - MICBIAS1 */
-/* R62 (0x3E) - MICBIAS2
- */
+/* R62 (0x3E) - MICBIAS2 */
-/* R210 (0xD2) - Mic Detect 3
- */
+/* R210 (0xD2) - Mic Detect 3 */
-/* R76 (0x4C) - Charge Pump (1)
- */
+/* R76 (0x4C) - Charge Pump (1) */
#define WM8994_CP_ENA (1 << 15)
/* Bit 15: Enable charge-pump digits */
#define WM8994_CP_ENA_DISABLE (0)
/* Diable */
#define WM8994_CP_ENA_ENABLE (WM8994_CP_ENA)
/* Enable */
-/* R77 (0x4D) - Charge Pump (2)
- */
+/* R77 (0x4D) - Charge Pump (2) */
#define WM8994_CP_DISCH (1 << 15)
/* Bit 15: Charge Pump Discharge Select */
#define WM8994_CP_DISCH_FLOAT (0)
/* Charge Pump outputs floating when disabled */
#define WM8994_CP_DISCH_DISCHARGE (WM8994_CP_DISCH)
/* Charge Pump outputs discharged when disabled */
-/* R81 (0x51) - Class W (1)
- */
+/* R81 (0x51) - Class W (1) */
#define WM8994_CP_DYN_SRC_SEL_SHIFT 8
/* Bits 8-9: Selects the digitial audio source for
* envelope tracking */
@@ -919,8 +886,7 @@
#define WM8994_CP_DYN_PWR_CG (0)
/* Charge pump controlled by volume register (Class G) */
#define WM8994_CP_DYN_PWR_CW (WM8994_CP_DYN_PWR)
/* Charge pump controlled by real-time audio lev. (Class W) */
-/* R84 (0x54) - DC Servo (1)
- */
+/* R84 (0x54) - DC Servo (1) */
#define WM8994_DCS_TRIG_SINGLE_1 (1 << 13)
/* Bit 13: Writing 1 to this bit selects a single DC offset
* correction for HPOUT1R. In readback, a value of 1
@@ -969,17 +935,13 @@
#define WM8994_DCS_ENA_CHAN_0_DISABLE (0)
/* Diable */
#define WM8994_DCS_ENA_CHAN_0_ENABLE (WM8994_DCS_ENA_CHAN_0)
/* Enable */
-/* R85 (0x55) - DC Servo (2)
- */
+/* R85 (0x55) - DC Servo (2) */
-/* R87 (0x57) - DC Servo (4)
- */
+/* R87 (0x57) - DC Servo (4) */
-/* R88 (0x58) - DC Servo Readback
- */
+/* R88 (0x58) - DC Servo Readback */
-/* R96 (0x60) - Analogue HP (1)
- */
+/* R96 (0x60) - Analogue HP (1) */
#define WM8994_HPOUT1L_RMV_SHORT (1 << 7)
/* Bit 7: Removes HPOUT1L short */
#define WM8994_HPOUT1L_RMV_SHORT_DISABLE (0)
/* HPOUT1L short diabled */
@@ -1000,23 +962,17 @@
#define WM8994_HPOUT1R_DLY_DISABLE (0)
/* Diable */
#define WM8994_HPOUT1R_DLY_ENABLE (WM8994_HPOUT1R_DLY)
/* Enable */
-/* R208 (0xD0) - Mic Detect 1
- */
+/* R208 (0xD0) - Mic Detect 1 */
-/* R209 (0xD1) - Mic Detect 2
- */
+/* R209 (0xD1) - Mic Detect 2 */
-/* R210 (0xD2) - Mic Detect 3
- */
+/* R210 (0xD2) - Mic Detect 3 */
-/* R256 (0x100) - Chip Revision
- */
+/* R256 (0x100) - Chip Revision */
-/** R257 (0x101) - Control Interface
- */
+/* R257 (0x101) - Control Interface */
-/* R272 (0x110) - Write Sequencer Ctrl (1)
- */
+/* R272 (0x110) - Write Sequencer Ctrl (1) */
#define WM8994_WSEQ_ENA (1 << 15)
/* Bit 15: Write Sequencer Enable */
#define WM8994_WSEQ_ENA_DISABLE (0)
/* Diable */
@@ -1026,15 +982,13 @@
#define WM8994_WSEQ_START_INDEX_SHIFT (0)
/* Bits 0-6: Sequence start index */
#define WM8994_WSEQ_START_INDEX_MASK (0x7F <<
WM8994_WSEQ_START_INDEX_SHIFT)
-/* R273 (0x111) - Write Sequencer Ctrl (2)
- */
+/* R273 (0x111) - Write Sequencer Ctrl (2) */
#define WM8994_WSEQ_BUSY (1 << 8)
/* Bit 8: Sequencer busy flag (read only) */
#define WM8994_WSEQ_CURRENT_INDEX_SHIFT (0)
/* Bits 0-6: Sequence current index */
#define WM8994_WSEQ_CURRENT_INDEX_MASK (0x7F <<
W8994_WSEQ_CURRENT_INDEX_SHIFT)
-/* R512 (0x200) - AIF1 Clocking (1)
- */
+/* R512 (0x200) - AIF1 Clocking (1) */
#define WM8994_AIF1CLK_ENA (1 << 0)
/* Bit 0: AIF1CLK Enable */
#define WM8994_AIF1CLK_DIV (1 << 1)
/* Bit 1: AIF1CLK Divider */
@@ -1051,17 +1005,13 @@
#define WM8994_AIF1CLK_SRC_PLL2 (3 <<
WM8994_AIF1CLK_SRC_SHIFT) /* PLL2 */
/* Bits 5-15: Reserved */
-/* R513 (0x201) - AIF1 Clocking (2)
- */
+/* R513 (0x201) - AIF1 Clocking (2) */
-/* R516 (0x204) - AIF2 Clocking (1)
- */
+/* R516 (0x204) - AIF2 Clocking (1) */
-/* R517 (0x205) - AIF2 Clocking (2)
- */
+/* R517 (0x205) - AIF2 Clocking (2) */
-/* R520 (0x208) - Clocking (1)
- */
+/* R520 (0x208) - Clocking (1) */
#define WM8994_SYSCLK_SRC (1 << 0)
/* Bit 0: SYSCLK Source Select */
#define WM8994_SYSCLK_SRC_AIF1CLK (0)
/* AIF1CLK */
@@ -1072,11 +1022,9 @@
#define WM8994_TOCLK_ENA (1 << 4)
/* Bit 4: Slow Clock(TOCLK) Enable */
/* Bits 5-15: Reserved */
-/* R521 (0x209) - Clocking (2)
- */
+/* R521 (0x209) - Clocking (2) */
-/* R528 (0x210) - AIF1 Rate
- */
+/* R528 (0x210) - AIF1 Rate */
#define WM8994_AIF1CLK_RATE_SHIFT (0)
/* Bits 0-3: Selects the AIF1CLK/fs ratio */
#define WM8994_AIF1CLK_RATE_MASK (0xf <<
WM8994_AIF1CLK_RATE_SHIFT)
@@ -1105,56 +1053,39 @@
#define WM8994_AIF1_SR_96K (10 << WM8994_AIF1_SR_SHIFT)
/* 96kHz */
/* Bits 8-15: Reserved */
-/* R529 (0x211) - AIF2 Rate
- */
+/* R529 (0x211) - AIF2 Rate */
-/* R530 (0x212) - Rate Status
- */
+/* R530 (0x212) - Rate Status */
-/* R544 (0x220) - FLL1 Control (1)
- */
+/* R544 (0x220) - FLL1 Control (1) */
-/* R545 (0x221) - FLL1 Control (2)
- */
+/* R545 (0x221) - FLL1 Control (2) */
-/* R546 (0x222) - FLL1 Control (3)
- */
+/* R546 (0x222) - FLL1 Control (3) */
-/* R547 (0x223) - FLL1 Control (4)
- */
+/* R547 (0x223) - FLL1 Control (4) */
-/* R548 (0x224) - FLL1 Control (5)
- */
+/* R548 (0x224) - FLL1 Control (5) */
-/* R550 (0x226) - FLL1 EFS 1
- */
+/* R550 (0x226) - FLL1 EFS 1 */
-/* R551 (0x227) - FLL1 EFS 2
- */
+/* R551 (0x227) - FLL1 EFS 2 */
-/* R576 (0x240) - FLL2 Control (1)
- */
+/* R576 (0x240) - FLL2 Control (1) */
-/* R577 (0x241) - FLL2 Control (2)
- */
+/* R577 (0x241) - FLL2 Control (2) */
-/* R578 (0x242) - FLL2 Control (3)
- */
+/* R578 (0x242) - FLL2 Control (3) */
-/* R579 (0x243) - FLL2 Control (4)
- */
+/* R579 (0x243) - FLL2 Control (4) */
-/* R580 (0x244) - FLL2 Control (5)
- */
+/* R580 (0x244) - FLL2 Control (5) */
-/* R582 (0x246) - FLL2 EFS 1
- */
+/* R582 (0x246) - FLL2 EFS 1 */
-/* R583 (0x247) - FLL2 EFS 2
- */
+/* R583 (0x247) - FLL2 EFS 2 */
-/* R768 (0x300) - AIF1 Control (1)
- */
+/* R768 (0x300) - AIF1 Control (1) */
/* Bits 0-2: Reserved */
#define WM8994_AIF1_FMT_SHIFT (3)
/* Bits 3-4: AIF1 Digital Audio Interface Format */
@@ -1179,11 +1110,9 @@
#define WM8994_AIF1ADCL_LEFT_ADC (0)
/* Left ADC data is output on left channel */
#define WM8994_AIF1ADCL_RIGHT_ADC (WM8994_AIF1ADCL_SRC)
/* Right ADC data is output on left channel */
-/* R769 (0x301) - AIF1 Control (2)
- */
+/* R769 (0x301) - AIF1 Control (2) */
-/* R770 (0x302) - AIF1 Master/Slave
- */
+/* R770 (0x302) - AIF1 Master/Slave */
/* Bits 0-11: Reserved */
#define WM8994_AIF1_LRCLK_FRC (1 << 12)
/* Bit 12: Forces LRCLK1 and ADCLRCLK1 to enabled when all AIF1
audio channels are disabled */
@@ -1199,100 +1128,73 @@
#define WM8994_AIF1_TRI_NORMAL (0)
/* AIF1 pins operate normally */
#define WM8994_AIF1_TRI_TRI (WM8994_AIF1_TRI)
/* Tri-state all AIF1 interface pins */
-/* R771 (0x303) - AIF1 BCLK
- */
+/* R771 (0x303) - AIF1 BCLK */
-/* R772 (0x304) - AIF1ADC LRCLK
- */
+/* R772 (0x304) - AIF1ADC LRCLK */
-/* R773 (0x305) - AIF1DAC LRCLK
- */
+/* R773 (0x305) - AIF1DAC LRCLK */
-/* R774 (0x306) - AIF1DAC Data
- */
+/* R774 (0x306) - AIF1DAC Data */
-/* R775 (0x307) - AIF1ADC Data
- */
+/* R775 (0x307) - AIF1ADC Data */
-/* R784 (0x310) - AIF2 Control (1)
- */
+/* R784 (0x310) - AIF2 Control (1) */
-/* R785 (0x311) - AIF2 Control (2)
- */
+/* R785 (0x311) - AIF2 Control (2) */
-/* R786 (0x312) - AIF2 Master/Slave
- */
+/* R786 (0x312) - AIF2 Master/Slave */
-/* R787 (0x313) - AIF2 BCLK
- */
+/* R787 (0x313) - AIF2 BCLK */
-/* R788 (0x314) - AIF2ADC LRCLK
- */
+/* R788 (0x314) - AIF2ADC LRCLK */
-/* R789 (0x315) - AIF2DAC LRCLK
- */
+/* R789 (0x315) - AIF2DAC LRCLK */
-/* R790 (0x316) - AIF2DAC Data
- */
+/* R790 (0x316) - AIF2DAC Data */
-/* R791 (0x317) - AIF2ADC Data
- */
+/* R791 (0x317) - AIF2ADC Data */
-/* R800 (0x320) - AIF3 Control (1)
- */
+/* R800 (0x320) - AIF3 Control (1) */
-/* R801 (0x321) - AIF3 Control (2)
- */
+/* R801 (0x321) - AIF3 Control (2) */
-/* R802 (0x322) - AIF3DAC Data
- */
+/* R802 (0x322) - AIF3DAC Data */
-/* R803 (0x323) - AIF3ADC Data
- */
+/* R803 (0x323) - AIF3ADC Data */
-/* R1024 (0x400) - AIF1 ADC1 Left Volume
- */
+/* R1024 (0x400) - AIF1 ADC1 Left Volume */
-/* R1025 (0x401) - AIF1 ADC1 Right Volume
- */
+/* R1025 (0x401) - AIF1 ADC1 Right Volume */
-/* R1026 (0x402) - AIF1 DAC1 Left Volume
- */
+/* R1026 (0x402) - AIF1 DAC1 Left Volume */
#define WM8994_AIF1DAC1_VU (1 << 8)
/* Bit 8: AIF1DAC1 input path (AIF1, TS 0) Vol Update */
#define WM8994_AIF1DAC1L_VOL_SHIFT (0)
/* Bits 0-7: AIF1DAC1 (Left) input path, Digital Vol. */
#define WM8994_AIF1DAC1L_VOL_MASK (0xFF <<
WM8994_AIF1DAC1L_VOL_SHIFT)
-/* R1027 (0x403) - AIF1 DAC1 Right Volume
- */
+/* R1027 (0x403) - AIF1 DAC1 Right Volume */
#define WM8994_AIF1DAC1R_VOL_SHIFT (0)
/* Bits 0-7: AIF1DAC1 (Right) input path, Digital Vol. */
#define WM8994_AIF1DAC1R_VOL_MASK (0xFF <<
WM8994_AIF1DAC1R_VOL_SHIFT)
-/* R1028 (0x404) - AIF1 ADC2 Left Volume
- */
+/* R1028 (0x404) - AIF1 ADC2 Left Volume */
-/* R1029 (0x405) - AIF1 ADC2 Right Volume
- */
+/* R1029 (0x405) - AIF1 ADC2 Right Volume */
-/* R1030 (0x406) - AIF1 DAC2 Left Volume
- */
+/* R1030 (0x406) - AIF1 DAC2 Left Volume */
#define WM8994_AIF1DAC2_VU (1 << 8)
/* Bit 8: AIF1DAC2 input path (AIF1, TS 1) Vol Update */
#define WM8994_AIF1DAC2L_VOL_SHIFT (0)
/* Bits 0-7: AIF1DAC2 (Left) input path, Digital Vol. */
#define WM8994_AIF1DAC2L_VOL_MASK (0xFF <<
WM8994_AIF1DAC2L_VOL_SHIFT)
-/* R1031 (0x407) - AIF1 DAC2 Right Volume
- */
+/* R1031 (0x407) - AIF1 DAC2 Right Volume */
#define WM8994_AIF1DAC2R_VOL_SHIFT (0)
/* Bits 0-7: AIF1DAC2 (Right) input path, Digital Vol. */
#define WM8994_AIF1DAC2R_VOL_MASK (0xFF <<
WM8994_AIF1DAC2R_VOL_SHIFT)
-/* R1040 (0x410) - AIF1 ADC1 Filters
- */
+/* R1040 (0x410) - AIF1 ADC1 Filters */
-/* R1041 (0x411) - AIF1 ADC2 Filters
- */
+/* R1041 (0x411) - AIF1 ADC2 Filters */
#define WM8994_AIF1ADC2_HPF_CUT_SHIFT (13)
/* Bits 13-14: AIF1ADC2 output path (AIF1, TS 1), HPF CO */
#define WM8994_AIF1ADC2_HPF_CUT_MASK (3 <<
WM8994_AIF1ADC2_HPF_CUT_SHIFT)
@@ -1307,8 +1209,7 @@
#define WM8994_AIF1ADC2R_HPF_DISABLE (0)
/* Disable */
#define WM8994_AIF1ADC2R_HPF_ENABLE (WM8994_AIF1ADC2R_HPF)
/* Enable */
-/* R1056 (0x420) - AIF1 DAC1 Filters (1)
- */
+/* R1056 (0x420) - AIF1 DAC1 Filters (1) */
#define WM8994_AIF1DAC1_MUTE (1 << 9)
/* Bit 9: AIF1DAC1 input path (AIF1, TS 0) Soft Mute Control */
#define WM8994_AIF1DAC1_MUTE_UNMUTE (0)
/* Un-mute */
@@ -1329,11 +1230,9 @@
#define WM8994_AIF1DAC1_DEEMP_44KHZ (2 <<
WM8994_AIF1DAC1_DEEMP_SHIFT) /* 44.1kHz sample rate */
#define WM8994_AIF1DAC1_DEEMP_48KHZ (3 <<
WM8994_AIF1DAC1_DEEMP_SHIFT) /* 48kHz sample rate*/
-/* R1057 (0x421) - AIF1 DAC1 Filters (2)
- */
+/* R1057 (0x421) - AIF1 DAC1 Filters (2) */
-/* R1058 (0x422) - AIF1 DAC2 Filters (1)
- */
+/* R1058 (0x422) - AIF1 DAC2 Filters (1) */
#define WM8994_AIF1DAC2_MUTE (1 << 9)
/* Bit 9: AIF1DAC2 input path (AIF1, TS 1) Soft Mute Control */
#define WM8994_AIF1DAC2_MUTE_UNMUTE (0)
/* Un-mute */
@@ -1354,269 +1253,181 @@
#define WM8994_AIF1DAC2_DEEMP_44KHZ (2 <<
WM8994_AIF1DAC2_DEEMP_SHIFT) /* 44.1kHz sample rate */
#define WM8994_AIF1DAC2_DEEMP_48KHZ (3 <<
WM8994_AIF1DAC2_DEEMP_SHIFT) /* 48kHz sample rate*/
-/* R1059 (0x423) - AIF1 DAC2 Filters (2)
- */
+/* R1059 (0x423) - AIF1 DAC2 Filters (2) */
-/* R1072 (0x430) - AIF1 DAC1 Noise Gate
- */
+/* R1072 (0x430) - AIF1 DAC1 Noise Gate */
-/* R1073 (0x431) - AIF1 DAC2 Noise Gate
- */
+/* R1073 (0x431) - AIF1 DAC2 Noise Gate */
-/* R1088 (0x440) - AIF1 DRC1 (1)
- */
+/* R1088 (0x440) - AIF1 DRC1 (1) */
-/* R1089 (0x441) - AIF1 DRC1 (2)
- */
+/* R1089 (0x441) - AIF1 DRC1 (2) */
-/* R1090 (0x442) - AIF1 DRC1 (3)
- */
+/* R1090 (0x442) - AIF1 DRC1 (3) */
-/* R1091 (0x443) - AIF1 DRC1 (4)
- */
+/* R1091 (0x443) - AIF1 DRC1 (4) */
-/* R1092 (0x444) - AIF1 DRC1 (5)
- */
+/* R1092 (0x444) - AIF1 DRC1 (5) */
-/* R1104 (0x450) - AIF1 DRC2 (1)
- */
+/* R1104 (0x450) - AIF1 DRC2 (1) */
-/* R1105 (0x451) - AIF1 DRC2 (2)
- */
+/* R1105 (0x451) - AIF1 DRC2 (2) */
-/* R1106 (0x452) - AIF1 DRC2 (3)
- */
+/* R1106 (0x452) - AIF1 DRC2 (3) */
-/* R1107 (0x453) - AIF1 DRC2 (4)
- */
+/* R1107 (0x453) - AIF1 DRC2 (4) */
-/* R1108 (0x454) - AIF1 DRC2 (5)
- */
+/* R1108 (0x454) - AIF1 DRC2 (5) */
-/* R1152 (0x480) - AIF1 DAC1 EQ Gains (1)
- */
+/* R1152 (0x480) - AIF1 DAC1 EQ Gains (1) */
-/* R1153 (0x481) - AIF1 DAC1 EQ Gains (2)
- */
+/* R1153 (0x481) - AIF1 DAC1 EQ Gains (2) */
-/* R1154 (0x482) - AIF1 DAC1 EQ Band 1 A
- */
+/* R1154 (0x482) - AIF1 DAC1 EQ Band 1 A */
-/* R1155 (0x483) - AIF1 DAC1 EQ Band 1 B
- */
+/* R1155 (0x483) - AIF1 DAC1 EQ Band 1 B */
-/* R1156 (0x484) - AIF1 DAC1 EQ Band 1 PG
- */
+/* R1156 (0x484) - AIF1 DAC1 EQ Band 1 PG */
-/* R1157 (0x485) - AIF1 DAC1 EQ Band 2 A
- */
+/* R1157 (0x485) - AIF1 DAC1 EQ Band 2 A */
-/* R1158 (0x486) - AIF1 DAC1 EQ Band 2 B
- */
+/* R1158 (0x486) - AIF1 DAC1 EQ Band 2 B */
-/* R1159 (0x487) - AIF1 DAC1 EQ Band 2 C
- */
+/* R1159 (0x487) - AIF1 DAC1 EQ Band 2 C */
-/* R1160 (0x488) - AIF1 DAC1 EQ Band 2 PG
- */
+/* R1160 (0x488) - AIF1 DAC1 EQ Band 2 PG */
-/* R1161 (0x489) - AIF1 DAC1 EQ Band 3 A
- */
+/* R1161 (0x489) - AIF1 DAC1 EQ Band 3 A */
-/* R1162 (0x48A) - AIF1 DAC1 EQ Band 3 B
- */
+/* R1162 (0x48A) - AIF1 DAC1 EQ Band 3 B */
-/* R1163 (0x48B) - AIF1 DAC1 EQ Band 3 C
- */
+/* R1163 (0x48B) - AIF1 DAC1 EQ Band 3 C */
-/* R1164 (0x48C) - AIF1 DAC1 EQ Band 3 PG
- */
+/* R1164 (0x48C) - AIF1 DAC1 EQ Band 3 PG */
-/* R1165 (0x48D) - AIF1 DAC1 EQ Band 4 A
- */
+/* R1165 (0x48D) - AIF1 DAC1 EQ Band 4 A */
-/* R1166 (0x48E) - AIF1 DAC1 EQ Band 4 B
- */
+/* R1166 (0x48E) - AIF1 DAC1 EQ Band 4 B */
-/* R1167 (0x48F) - AIF1 DAC1 EQ Band 4 C
- */
+/* R1167 (0x48F) - AIF1 DAC1 EQ Band 4 C */
-/* R1168 (0x490) - AIF1 DAC1 EQ Band 4 PG
- */
+/* R1168 (0x490) - AIF1 DAC1 EQ Band 4 PG */
-/* R1169 (0x491) - AIF1 DAC1 EQ Band 5 A
- */
+/* R1169 (0x491) - AIF1 DAC1 EQ Band 5 A */
-/* R1170 (0x492) - AIF1 DAC1 EQ Band 5 B
- */
+/* R1170 (0x492) - AIF1 DAC1 EQ Band 5 B */
-/* R1171 (0x493) - AIF1 DAC1 EQ Band 5 PG
- */
+/* R1171 (0x493) - AIF1 DAC1 EQ Band 5 PG */
-/* R1184 (0x4A0) - AIF1 DAC2 EQ Gains (1)
- */
+/* R1184 (0x4A0) - AIF1 DAC2 EQ Gains (1) */
-/* R1185 (0x4A1) - AIF1 DAC2 EQ Gains (2)
- */
+/* R1185 (0x4A1) - AIF1 DAC2 EQ Gains (2) */
-/* R1186 (0x4A2) - AIF1 DAC2 EQ Band 1 A
- */
+/* R1186 (0x4A2) - AIF1 DAC2 EQ Band 1 A */
-/* R1187 (0x4A3) - AIF1 DAC2 EQ Band 1 B
- */
+/* R1187 (0x4A3) - AIF1 DAC2 EQ Band 1 B */
-/* R1188 (0x4A4) - AIF1 DAC2 EQ Band 1 PG
- */
+/* R1188 (0x4A4) - AIF1 DAC2 EQ Band 1 PG */
-/* R1189 (0x4A5) - AIF1 DAC2 EQ Band 2 A
- */
+/* R1189 (0x4A5) - AIF1 DAC2 EQ Band 2 A */
-/* R1190 (0x4A6) - AIF1 DAC2 EQ Band 2 B
- */
+/* R1190 (0x4A6) - AIF1 DAC2 EQ Band 2 B */
-/* R1191 (0x4A7) - AIF1 DAC2 EQ Band 2 C
- */
+/* R1191 (0x4A7) - AIF1 DAC2 EQ Band 2 C */
-/* R1192 (0x4A8) - AIF1 DAC2 EQ Band 2 PG
- */
+/* R1192 (0x4A8) - AIF1 DAC2 EQ Band 2 PG */
-/* R1193 (0x4A9) - AIF1 DAC2 EQ Band 3 A
- */
+/* R1193 (0x4A9) - AIF1 DAC2 EQ Band 3 A */
-/* R1194 (0x4AA) - AIF1 DAC2 EQ Band 3 B
- */
+/* R1194 (0x4AA) - AIF1 DAC2 EQ Band 3 B */
-/* R1195 (0x4AB) - AIF1 DAC2 EQ Band 3 C
- */
+/* R1195 (0x4AB) - AIF1 DAC2 EQ Band 3 C */
-/* R1196 (0x4AC) - AIF1 DAC2 EQ Band 3 PG
- */
+/* R1196 (0x4AC) - AIF1 DAC2 EQ Band 3 PG */
-/* R1197 (0x4AD) - AIF1 DAC2 EQ Band 4 A
- */
+/* R1197 (0x4AD) - AIF1 DAC2 EQ Band 4 A */
-/* R1198 (0x4AE) - AIF1 DAC2 EQ Band 4 B
- */
+/* R1198 (0x4AE) - AIF1 DAC2 EQ Band 4 B */
-/* R1199 (0x4AF) - AIF1 DAC2 EQ Band 4 C
- */
+/* R1199 (0x4AF) - AIF1 DAC2 EQ Band 4 C */
-/* R1200 (0x4B0) - AIF1 DAC2 EQ Band 4 PG
- */
+/* R1200 (0x4B0) - AIF1 DAC2 EQ Band 4 PG */
-/* R1201 (0x4B1) - AIF1 DAC2 EQ Band 5 A
- */
+/* R1201 (0x4B1) - AIF1 DAC2 EQ Band 5 A */
-/* R1202 (0x4B2) - AIF1 DAC2 EQ Band 5 B
- */
+/* R1202 (0x4B2) - AIF1 DAC2 EQ Band 5 B */
-/* R1203 (0x4B3) - AIF1 DAC2 EQ Band 5 PG
- */
+/* R1203 (0x4B3) - AIF1 DAC2 EQ Band 5 PG */
-/* R1280 (0x500) - AIF2 ADC Left Volume
- */
+/* R1280 (0x500) - AIF2 ADC Left Volume */
-/* R1281 (0x501) - AIF2 ADC Right Volume
- */
+/* R1281 (0x501) - AIF2 ADC Right Volume */
-/* R1282 (0x502) - AIF2 DAC Left Volume
- */
+/* R1282 (0x502) - AIF2 DAC Left Volume */
-/* R1283 (0x503) - AIF2 DAC Right Volume
- */
+/* R1283 (0x503) - AIF2 DAC Right Volume */
-/* R1296 (0x510) - AIF2 ADC Filters
- */
+/* R1296 (0x510) - AIF2 ADC Filters */
-/* R1312 (0x520) - AIF2 DAC Filters (1)
- */
+/* R1312 (0x520) - AIF2 DAC Filters (1) */
-/* R1313 (0x521) - AIF2 DAC Filters (2)
- */
+/* R1313 (0x521) - AIF2 DAC Filters (2) */
-/* R1328 (0x530) - AIF2 DAC Noise Gate
- */
+/* R1328 (0x530) - AIF2 DAC Noise Gate */
-/* R1344 (0x540) - AIF2 DRC (1)
- */
+/* R1344 (0x540) - AIF2 DRC (1) */
-/* R1345 (0x541) - AIF2 DRC (2)
- */
+/* R1345 (0x541) - AIF2 DRC (2) */
-/* R1346 (0x542) - AIF2 DRC (3)
- */
+/* R1346 (0x542) - AIF2 DRC (3) */
-/* R1347 (0x543) - AIF2 DRC (4)
- */
+/* R1347 (0x543) - AIF2 DRC (4) */
-/* R1348 (0x544) - AIF2 DRC (5)
- */
+/* R1348 (0x544) - AIF2 DRC (5) */
-/* R1408 (0x580) - AIF2 EQ Gains (1)
- */
+/* R1408 (0x580) - AIF2 EQ Gains (1) */
-/* R1409 (0x581) - AIF2 EQ Gains (2)
- */
+/* R1409 (0x581) - AIF2 EQ Gains (2) */
-/* R1410 (0x582) - AIF2 EQ Band 1 A
- */
+/* R1410 (0x582) - AIF2 EQ Band 1 A */
-/* R1411 (0x583) - AIF2 EQ Band 1 B
- */
+/* R1411 (0x583) - AIF2 EQ Band 1 B */
-/* R1412 (0x584) - AIF2 EQ Band 1 PG
- */
+/* R1412 (0x584) - AIF2 EQ Band 1 PG */
-/* R1413 (0x585) - AIF2 EQ Band 2 A
- */
+/* R1413 (0x585) - AIF2 EQ Band 2 A */
-/* R1414 (0x586) - AIF2 EQ Band 2 B
- */
+/* R1414 (0x586) - AIF2 EQ Band 2 B */
-/* R1415 (0x587) - AIF2 EQ Band 2 C
- */
+/* R1415 (0x587) - AIF2 EQ Band 2 C */
-/* R1416 (0x588) - AIF2 EQ Band 2 PG
- */
+/* R1416 (0x588) - AIF2 EQ Band 2 PG */
-/* R1417 (0x589) - AIF2 EQ Band 3 A
- */
+/* R1417 (0x589) - AIF2 EQ Band 3 A */
-/* R1418 (0x58A) - AIF2 EQ Band 3 B
- */
+/* R1418 (0x58A) - AIF2 EQ Band 3 B */
-/* R1419 (0x58B) - AIF2 EQ Band 3 C
- */
+/* R1419 (0x58B) - AIF2 EQ Band 3 C */
-/* R1420 (0x58C) - AIF2 EQ Band 3 PG
- */
+/* R1420 (0x58C) - AIF2 EQ Band 3 PG */
-/* R1421 (0x58D) - AIF2 EQ Band 4 A
- */
+/* R1421 (0x58D) - AIF2 EQ Band 4 A */
-/* R1422 (0x58E) - AIF2 EQ Band 4 B
- */
+/* R1422 (0x58E) - AIF2 EQ Band 4 B */
-/* R1423 (0x58F) - AIF2 EQ Band 4 C
- */
+/* R1423 (0x58F) - AIF2 EQ Band 4 C */
-/* R1424 (0x590) - AIF2 EQ Band 4 PG
- */
+/* R1424 (0x590) - AIF2 EQ Band 4 PG */
-/* R1425 (0x591) - AIF2 EQ Band 5 A
- */
+/* R1425 (0x591) - AIF2 EQ Band 5 A */
-/* R1426 (0x592) - AIF2 EQ Band 5 B
- */
+/* R1426 (0x592) - AIF2 EQ Band 5 B */
-/* R1427 (0x593) - AIF2 EQ Band 5 PG
- */
+/* R1427 (0x593) - AIF2 EQ Band 5 PG */
-/* R1536 (0x600) - DAC1 Mixer Volumes
- */
+/* R1536 (0x600) - DAC1 Mixer Volumes */
-/* R1537 (0x601) - DAC1 Left Mixer Routing
- */
+/* R1537 (0x601) - DAC1 Left Mixer Routing */
#define WM8994_AIF1DAC1L_TO_DAC1L_ENA (1 << 0)
/* Bit 0: Enable AIF1(Timeslot 0, Left) to DAC1L */
#define WM8994_AIF1DAC2L_TO_DAC1L_ENA (1 << 1)
/* Bit 1: Enable AIF1(Timeslot 1, Left) to DAC1L */
@@ -1626,8 +1437,7 @@
#define WM8994_ADCR_TO_DAC1L_ENA (1 << 5)
/* Bit 5: Enable Sidetone STR to DAC1L */
/* Bits 6-15: Reserved */
-/* R1538 (0x602) - DAC1 Right Mixer Routing
- */
+/* R1538 (0x602) - DAC1 Right Mixer Routing */
#define WM8994_AIF1DAC1R_TO_DAC1R_ENA (1 << 0)
/* Bit 0: Enable AIF1(Timeslot 0, Right) to DAC1R */
#define WM8994_AIF1DAC2R_TO_DAC1R_ENA (1 << 1)
/* Bit 1: Enable AIF1(Timeslot 1, Right) to DAC1R */
@@ -1637,16 +1447,14 @@
#define WM8994_ADCR_TO_DAC1R_ENA (1 << 5)
/* Bit 5: Enable Sidetone STR to DAC1R */
/* Bits 6-15: Reserved */
-/* R1539 (0x603) - DAC2 Mixer Volumes
- */
+/* R1539 (0x603) - DAC2 Mixer Volumes */
#define WM8994_ADCR_DAC2_VOL_SHIFT (5)
/* Bits 5-8: Sidetone STR to DAC2L and DAC2R Volume */
#define WM8994_ADCR_DAC2_VOL_MASK (0xF <<
WM8994_ADCR_DAC2_VOL_SHIFT) /* 0000 = -36 DB, 1100 = 0dB */
#define WM8994_ADCL_DAC2_VOL_SHIFT (0)
/* Bits 0-3: Sidetone STL to DAC2L and DAC2R Volume */
#define WM8994_ADCL_DAC2_VOL_MASK (0xF <<
WM8994_ADCL_DAC2_VOL_SHIFT /* 0000 = -36 DB, 1100 = 0dB */
-/* R1540 (0x604) - DAC2 Left Mixer Routing
- */
+/* R1540 (0x604) - DAC2 Left Mixer Routing */
#define WM8994_AIF1DAC1L_TO_DAC2L_ENA (1 << 0)
/* Bit 0: Enable AIF1(Timeslot 0, Left) to DAC2L */
#define WM8994_AIF1DAC2L_TO_DAC2L_ENA (1 << 1)
/* Bit 1: Enable AIF1(Timeslot 1, Left) to DAC2L */
@@ -1656,8 +1464,7 @@
#define WM8994_ADCR_TO_DAC2L_ENA (1 << 5)
/* Bit 5: Enable Sidetone STR to DAC2L */
/* Bits 6-15: Reserved */
-/* R1541 (0x605) - DAC2 Right Mixer Routing
- */
+/* R1541 (0x605) - DAC2 Right Mixer Routing */
#define WM8994_AIF1DAC1R_TO_DAC2R_ENA (1 << 0)
/* Bit 0: Enable AIF1(Timeslot 0, Right) to DAC2R */
#define WM8994_AIF1DAC2R_TO_DAC2R_ENA (1 << 1)
/* Bit 1: Enable AIF1(Timeslot 1, Right) to DAC2R */
@@ -1667,20 +1474,15 @@
#define WM8994_ADCR_TO_DAC2R_ENA (1 << 5)
/* Bit 5: Enable Sidetone STR to DAC2R */
/* Bits 6-15: Reserved */
-/* R1542 (0x606) - AIF1 ADC1 Left Mixer Routing
- */
+/* R1542 (0x606) - AIF1 ADC1 Left Mixer Routing */
-/* R1543 (0x607) - AIF1 ADC1 Right Mixer Routing
- */
+/* R1543 (0x607) - AIF1 ADC1 Right Mixer Routing */
-/* R1544 (0x608) - AIF1 ADC2 Left Mixer Routing
- */
+/* R1544 (0x608) - AIF1 ADC2 Left Mixer Routing */
-/* R1545 (0x609) - AIF1 ADC2 Right mixer Routing
- */
+/* R1545 (0x609) - AIF1 ADC2 Right mixer Routing */
-/* R1552 (0x610) - DAC1 Left Volume
- */
+/* R1552 (0x610) - DAC1 Left Volume */
#define WM8994_DAC1L_MUTE (1 << 9)
/* Bit 9: DAC1L Soft Mute Control */
#define WM8994_DAC1L_MUTE_UNMUTE (0)
/* DAC Un-mute */
@@ -1689,8 +1491,7 @@
#define WM8994_DAC1L_VOL_SHIFT (0)
/* Bits 0-7: DAC1L Digital Volume */
#define WM8994_DAC1L_VOL_MASK (0xFF <<
WM8994_DAC1L_VOL_SHIFT)
-/* R1553 (0x611) - DAC1 Right Volume
- */
+/* R1553 (0x611) - DAC1 Right Volume */
#define WM8994_DAC1R_MUTE (1 << 9)
/* Bit 9: DAC1R Soft Mute Control */
#define WM8994_DAC1R_MUTE_UNMUTE (0)
/* DAC Un-mute */
@@ -1698,8 +1499,7 @@
#define WM8994_DAC1R_VOL_SHIFT (0)
/* Bits 0-7: DAC1R Digital Volume */
#define WM8994_DAC1R_VOL_MASK (0xFF <<
WM8994_DAC1R_VOL_SHIFT)
-/* R1554 (0x612) - DAC2 Left Volume
- */
+/* R1554 (0x612) - DAC2 Left Volume */
#define WM8994_DAC2L_MUTE (1 << 9)
/* Bit 9: DAC2L Soft Mute Control */
#define WM8994_DAC2L_MUTE_UNMUTE (0)
/* DAC Un-mute */
@@ -1708,8 +1508,7 @@
#define WM8994_DAC2L_VOL_SHIFT (0)
/* Bits 0-7: DAC2L Digital Volume */
#define WM8994_DAC2L_VOL_MASK (0xFF <<
WM8994_DAC2L_VOL_SHIFT)
-/* R1555 (0x613) - DAC2 Right Volume
- */
+/* R1555 (0x613) - DAC2 Right Volume */
#define WM8994_DAC2R_MUTE (1 << 9)
/* Bit 9: DAC2R Soft Mute Control */
#define WM8994_DAC2R_MUTE_UNMUTE (0)
/* DAC Un-mute */
@@ -1717,44 +1516,31 @@
#define WM8994_DAC2R_VOL_SHIFT (0)
/* Bits 0-7: DAC2R Digital Volume */
#define WM8994_DAC2R_VOL_MASK (0xFF <<
WM8994_DAC2R_VOL_SHIFT)
-/* R1556 (0x614) - DAC Softmute
- */
+/* R1556 (0x614) - DAC Softmute */
-/* R1568 (0x620) - Oversampling
- */
+/* R1568 (0x620) - Oversampling */
-/* R1569 (0x621) - Sidetone
- */
+/* R1569 (0x621) - Sidetone */
-/* R1797 (0x705) - JACKDET Ctrl
- */
+/* R1797 (0x705) - JACKDET Ctrl */
-/* R1824 (0x720) - Pull Control (1)
- */
+/* R1824 (0x720) - Pull Control (1) */
-/* R1825 (0x721) - Pull Control (2)
- */
+/* R1825 (0x721) - Pull Control (2) */
-/* R1840 (0x730) - Interrupt Status 1
- */
+/* R1840 (0x730) - Interrupt Status 1 */
-/* R1841 (0x731) - Interrupt Status 2
- */
+/* R1841 (0x731) - Interrupt Status 2 */
-/* R1842 (0x732) - Interrupt Raw Status 2
- */
+/* R1842 (0x732) - Interrupt Raw Status 2 */
-/* R1848 (0x738) - Interrupt Status 1 Mask
- */
+/* R1848 (0x738) - Interrupt Status 1 Mask */
-/* R1849 (0x739) - Interrupt Status 2 Mask
- */
+/* R1849 (0x739) - Interrupt Status 2 Mask */
-/* R1856 (0x740) - Interrupt Control
- */
+/* R1856 (0x740) - Interrupt Control */
-/* R1864 (0x748) - IRQ Debounce
- */
+/* R1864 (0x748) - IRQ Debounce */
/* Register Default Values */
diff --git a/drivers/sensors/fxos8700cq.c b/drivers/sensors/fxos8700cq.c
index 21edd96869..afb307d85d 100644
--- a/drivers/sensors/fxos8700cq.c
+++ b/drivers/sensors/fxos8700cq.c
@@ -64,7 +64,7 @@
/* Values */
#define FXOS8700CQ_WHOAMI_VAL 0xC7
-/** status byte + x,y,z for accelerometer and magnetometer */
+/* status byte + x,y,z for accelerometer and magnetometer */
#define FXOS8700CQ_READ_LEN ((8 + (16 * 3 + 16 * 3)) / 8)
/****************************************************************************
@@ -103,7 +103,7 @@ static int fxos8700cq_checkid(FAR struct fxos8700cq_dev_s
*priv);
* Private Data
****************************************************************************/
-/** vtable that supports the character driver interface */
+/* vtable that supports the character driver interface */
static const struct file_operations g_fxos8700cqfops =
{
diff --git a/drivers/wireless/ISM2_905MHzGFSK250kbps.c
b/drivers/wireless/ISM2_905MHzGFSK250kbps.c
index d75b99a53f..81d52b861e 100644
--- a/drivers/wireless/ISM2_905MHzGFSK250kbps.c
+++ b/drivers/wireless/ISM2_905MHzGFSK250kbps.c
@@ -28,7 +28,7 @@
* Public Data
****************************************************************************/
-/** Settings for 905 MHz, GFSK at 250kbps
+/* Settings for 905 MHz, GFSK at 250kbps
*
* ISM Region 2 (America) only, Band 902–928 MHz
*
diff --git a/drivers/wireless/ieee80211/bcm43xxx/bcmf_ioctl.h
b/drivers/wireless/ieee80211/bcm43xxx/bcmf_ioctl.h
index 3251780905..fbced6df52 100644
--- a/drivers/wireless/ieee80211/bcm43xxx/bcmf_ioctl.h
+++ b/drivers/wireless/ieee80211/bcm43xxx/bcmf_ioctl.h
@@ -267,7 +267,7 @@ typedef struct wl_join_scan_params
}
end_packed_struct wl_join_scan_params_t;
-/** used for association with a specific BSSID and chanspec list */
+/* used for association with a specific BSSID and chanspec list */
begin_packed_struct
typedef struct wl_assoc_params
@@ -285,11 +285,11 @@ typedef struct wl_assoc_params
}
end_packed_struct wl_assoc_params_t;
-/** used for association to a specific BSSID and channel */
+/* used for association to a specific BSSID and channel */
typedef wl_assoc_params_t wl_join_assoc_params_t;
-/** extended join params */
+/* extended join params */
begin_packed_struct
typedef struct wl_extjoin_params
diff --git a/include/nuttx/video/video_controls.h
b/include/nuttx/video/video_controls.h
index 6373080a6f..c2ee205e97 100644
--- a/include/nuttx/video/video_controls.h
+++ b/include/nuttx/video/video_controls.h
@@ -56,7 +56,7 @@
#define V4L2_CID_COLOR_KILLER (15) /* Color killer */
#define V4L2_CID_COLORFX (16) /* Color effect */
-/** Enumeration for V4L2_CID_COLORFX */
+/* Enumeration for V4L2_CID_COLORFX */
enum v4l2_colorfx
{
@@ -87,7 +87,7 @@ enum v4l2_colorfx
/* Enumeration for V4L2_CID_EXPOSURE_AUTO */
-enum v4l2_exposure_auto_type
+enum v4l2_exposure_auto_type
{
/* Exposure time:auto, iris aperture:auto */
