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xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
The following commit(s) were added to refs/heads/master by this push:
new b0965ab963 Fix nuttx coding style
b0965ab963 is described below
commit b0965ab9631ed923924b3ec93102f13851fff8f4
Author: simbit18 <[email protected]>
AuthorDate: Thu Jul 13 15:50:40 2023 +0200
Fix nuttx coding style
Remove TABs
Fix indentation
Fix Multi-line comments
Fix Comments to the Right of Statements.
---
arch/arm/src/cxd56xx/cxd56_dmac.c | 46 ++---
arch/arm/src/cxd56xx/cxd56_dmac.h | 10 +-
arch/arm/src/efm32/hardware/efm32_rmu.h | 206 ++++++++++-----------
arch/arm/src/phy62xx/rom_sym_def.h | 4 +-
arch/arm64/src/a64/hardware/a64_twi.h | 44 ++---
arch/arm64/src/common/arm64_arch_timer.h | 6 +-
arch/risc-v/src/esp32c3/esp32c3_bignum.h | 18 +-
arch/risc-v/src/esp32c3/esp32c3_efuse.h | 40 ++--
arch/risc-v/src/esp32c3/esp32c3_rsa.h | 40 ++--
arch/risc-v/src/esp32c3/hardware/esp32c3_iomux.h | 46 ++---
arch/risc-v/src/esp32c3/hardware/esp32c3_rtccntl.h | 4 +-
arch/risc-v/src/hpm6750/hpm6750_serial.h | 72 ++++---
arch/risc-v/src/litex/hardware/litex_uart.h | 4 +-
arch/x86/include/i486/irq.h | 2 +-
arch/xtensa/include/esp32/memory_layout.h | 4 +-
arch/xtensa/src/esp32/chip_macros.h | 2 +-
arch/xtensa/src/esp32/hardware/esp32_dport.h | 10 +-
arch/xtensa/src/esp32/hardware/esp32_tim.h | 94 +++++-----
arch/xtensa/src/esp32s2/esp32s2_efuse.h | 40 ++--
arch/xtensa/src/esp32s2/esp32s2_serial.c | 2 +-
.../src/esp32s2/hardware/esp32s2_gpio_sigmap.h | 4 +-
arch/xtensa/src/esp32s3/chip_macros.h | 2 +-
arch/xtensa/src/esp32s3/esp32s3_efuse.h | 40 ++--
arch/xtensa/src/esp32s3/hardware/esp32s3_soc.h | 2 +-
boards/arm/cxd56xx/drivers/sensors/bmi160_scu.c | 4 +-
.../arm/cxd56xx/spresense/include/cxd56_gpioif.h | 18 +-
boards/arm/imxrt/imxrt1020-evk/src/imxrt1020-evk.h | 2 +-
boards/arm/lpc43xx/lpc4337-ws/include/board.h | 34 ++--
boards/arm/lpc43xx/lpc4370-link2/include/board.h | 34 ++--
boards/arm/samd5e5/metro-m4/include/board.h | 4 +-
.../stm32h745i-disco/src/stm32h745i_disco.h | 6 +-
drivers/modem/alt1250/altcom_pkt.h | 6 +-
drivers/sensors/bmi270.c | 2 +-
33 files changed, 423 insertions(+), 429 deletions(-)
diff --git a/arch/arm/src/cxd56xx/cxd56_dmac.c
b/arch/arm/src/cxd56xx/cxd56_dmac.c
index e5cf71d88a..f4b6cdec13 100644
--- a/arch/arm/src/cxd56xx/cxd56_dmac.c
+++ b/arch/arm/src/cxd56xx/cxd56_dmac.c
@@ -147,29 +147,29 @@ typedef struct
uint32_t control; /* Transfer control */
} dmac_lli_t;
-#define CXD56_DMAC_M2M 0 /**< Memory to memory */
-#define CXD56_DMAC_M2P 1 /**< Memory to peripheral, DMAC controlled */
-#define CXD56_DMAC_P2M 2 /**< Peripheral to memory, DMAC controlled */
-#define CXD56_DMAC_P2P 3 /**< Peripheral to peripheral */
-#define CXD56_DMAC_P2CP 4 /**< P2P destination controlled */
-#define CXD56_DMAC_M2CP 5 /**< M2P peripheral controlled */
-#define CXD56_DMAC_CP2M 6 /**< P2M peripheral controlled */
-#define CXD56_DMAC_CP2P 7 /**< P2P source controlled */
-
-#define CXD56_DMAC_BSIZE1 0 /**< 1 burst */
-#define CXD56_DMAC_BSIZE4 1 /**< 4 burst */
-#define CXD56_DMAC_BSIZE8 2 /**< 8 burst */
-#define CXD56_DMAC_BSIZE16 3 /**< 16 burst */
-#define CXD56_DMAC_BSIZE32 4 /**< 32 burst */
-#define CXD56_DMAC_BSIZE64 5 /**< 64 burst */
-#define CXD56_DMAC_BSIZE128 6 /**< 128 burst */
-#define CXD56_DMAC_BSIZE256 7 /**< 256 burst */
-
-#define CXD56_DMAC_LITTLE_ENDIAN 0 /**< Little endian */
-#define CXD56_DMAC_BIG_ENDIAN 1 /**< Bit endian */
-
-#define CXD56_DMAC_MASTER1 0 /**< AHB master 1 */
-#define CXD56_DMAC_MASTER2 1 /**< AHB master 2 */
+#define CXD56_DMAC_M2M 0 /* Memory to memory */
+#define CXD56_DMAC_M2P 1 /* Memory to peripheral, DMAC controlled */
+#define CXD56_DMAC_P2M 2 /* Peripheral to memory, DMAC controlled */
+#define CXD56_DMAC_P2P 3 /* Peripheral to peripheral */
+#define CXD56_DMAC_P2CP 4 /* P2P destination controlled */
+#define CXD56_DMAC_M2CP 5 /* M2P peripheral controlled */
+#define CXD56_DMAC_CP2M 6 /* P2M peripheral controlled */
+#define CXD56_DMAC_CP2P 7 /* P2P source controlled */
+
+#define CXD56_DMAC_BSIZE1 0 /* 1 burst */
+#define CXD56_DMAC_BSIZE4 1 /* 4 burst */
+#define CXD56_DMAC_BSIZE8 2 /* 8 burst */
+#define CXD56_DMAC_BSIZE16 3 /* 16 burst */
+#define CXD56_DMAC_BSIZE32 4 /* 32 burst */
+#define CXD56_DMAC_BSIZE64 5 /* 64 burst */
+#define CXD56_DMAC_BSIZE128 6 /* 128 burst */
+#define CXD56_DMAC_BSIZE256 7 /* 256 burst */
+
+#define CXD56_DMAC_LITTLE_ENDIAN 0 /* Little endian */
+#define CXD56_DMAC_BIG_ENDIAN 1 /* Bit endian */
+
+#define CXD56_DMAC_MASTER1 0 /* AHB master 1 */
+#define CXD56_DMAC_MASTER2 1 /* AHB master 2 */
/* max transfer size at a time */
diff --git a/arch/arm/src/cxd56xx/cxd56_dmac.h
b/arch/arm/src/cxd56xx/cxd56_dmac.h
index 0b398af95a..17716518c6 100644
--- a/arch/arm/src/cxd56xx/cxd56_dmac.h
+++ b/arch/arm/src/cxd56xx/cxd56_dmac.h
@@ -41,12 +41,12 @@
#define CXD56_DMA_PERIPHERAL_SPI5_TX (4)
#define CXD56_DMA_PERIPHERAL_SPI5_RX (5)
-#define CXD56_DMA_INTR_ITC (1u<<0) /**< Terminal count interrupt status */
-#define CXD56_DMA_INTR_ERR (1u<<1) /**< Error interrupt status */
+#define CXD56_DMA_INTR_ITC (1u<<0) /* Terminal count interrupt status */
+#define CXD56_DMA_INTR_ERR (1u<<1) /* Error interrupt status */
-#define CXD56_DMAC_WIDTH8 0 /**< 8 bit width */
-#define CXD56_DMAC_WIDTH16 1 /**< 16 bit width */
-#define CXD56_DMAC_WIDTH32 2 /**< 32 bit width */
+#define CXD56_DMAC_WIDTH8 0 /* 8 bit width */
+#define CXD56_DMAC_WIDTH16 1 /* 16 bit width */
+#define CXD56_DMAC_WIDTH32 2 /* 32 bit width */
/****************************************************************************
* Public Types
diff --git a/arch/arm/src/efm32/hardware/efm32_rmu.h
b/arch/arm/src/efm32/hardware/efm32_rmu.h
index 24a0af0f8c..65c295ff66 100644
--- a/arch/arm/src/efm32/hardware/efm32_rmu.h
+++ b/arch/arm/src/efm32/hardware/efm32_rmu.h
@@ -92,115 +92,115 @@
/* Bit fields for RMU CTRL */
-#define _RMU_CTRL_RESETVALUE 0x00000002UL
/**< Default value for RMU_CTRL */
-#define _RMU_CTRL_MASK 0x00000003UL
/**< Mask for RMU_CTRL */
-
-#define RMU_CTRL_LOCKUPRDIS (0x1UL << 0)
/**< Lockup Reset Disable */
-#define _RMU_CTRL_LOCKUPRDIS_SHIFT 0
/**< Shift value for RMU_LOCKUPRDIS */
-#define _RMU_CTRL_LOCKUPRDIS_MASK 0x1UL
/**< Bit mask for RMU_LOCKUPRDIS */
-#define _RMU_CTRL_LOCKUPRDIS_DEFAULT 0x00000000UL
/**< Mode DEFAULT for RMU_CTRL */
-#define RMU_CTRL_LOCKUPRDIS_DEFAULT (_RMU_CTRL_LOCKUPRDIS_DEFAULT <<
0) /**< Shifted mode DEFAULT for RMU_CTRL */
-#define RMU_CTRL_BURSTEN (0x1UL << 1)
/**< Backup domain reset enable */
-#define _RMU_CTRL_BURSTEN_SHIFT 1
/**< Shift value for RMU_BURSTEN */
-#define _RMU_CTRL_BURSTEN_MASK 0x2UL
/**< Bit mask for RMU_BURSTEN */
-#define _RMU_CTRL_BURSTEN_DEFAULT 0x00000001UL
/**< Mode DEFAULT for RMU_CTRL */
-#define RMU_CTRL_BURSTEN_DEFAULT (_RMU_CTRL_BURSTEN_DEFAULT << 1)
/**< Shifted mode DEFAULT for RMU_CTRL */
+#define _RMU_CTRL_RESETVALUE 0x00000002UL
/* Default value for RMU_CTRL */
+#define _RMU_CTRL_MASK 0x00000003UL
/* Mask for RMU_CTRL */
+
+#define RMU_CTRL_LOCKUPRDIS (0x1UL << 0)
/* Lockup Reset Disable */
+#define _RMU_CTRL_LOCKUPRDIS_SHIFT 0
/* Shift value for RMU_LOCKUPRDIS */
+#define _RMU_CTRL_LOCKUPRDIS_MASK 0x1UL
/* Bit mask for RMU_LOCKUPRDIS */
+#define _RMU_CTRL_LOCKUPRDIS_DEFAULT 0x00000000UL
/* Mode DEFAULT for RMU_CTRL */
+#define RMU_CTRL_LOCKUPRDIS_DEFAULT (_RMU_CTRL_LOCKUPRDIS_DEFAULT <<
0) /* Shifted mode DEFAULT for RMU_CTRL */
+#define RMU_CTRL_BURSTEN (0x1UL << 1)
/* Backup domain reset enable */
+#define _RMU_CTRL_BURSTEN_SHIFT 1
/* Shift value for RMU_BURSTEN */
+#define _RMU_CTRL_BURSTEN_MASK 0x2UL
/* Bit mask for RMU_BURSTEN */
+#define _RMU_CTRL_BURSTEN_DEFAULT 0x00000001UL
/* Mode DEFAULT for RMU_CTRL */
+#define RMU_CTRL_BURSTEN_DEFAULT (_RMU_CTRL_BURSTEN_DEFAULT << 1)
/* Shifted mode DEFAULT for RMU_CTRL */
/* Bit fields for RMU RSTCAUSE */
-#define _RMU_RSTCAUSE_RESETVALUE 0x00000000UL
/**< Default value for RMU_RSTCAUSE */
-#define _RMU_RSTCAUSE_MASK 0x0000FFFFUL
/**< Mask for RMU_RSTCAUSE */
-
-#define RMU_RSTCAUSE_PORST (0x1UL << 0)
/**< Power On Reset */
-#define _RMU_RSTCAUSE_PORST_SHIFT 0
/**< Shift value for RMU_PORST */
-#define _RMU_RSTCAUSE_PORST_MASK 0x1UL
/**< Bit mask for RMU_PORST */
-#define _RMU_RSTCAUSE_PORST_DEFAULT 0x00000000UL
/**< Mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_PORST_DEFAULT (_RMU_RSTCAUSE_PORST_DEFAULT <<
0) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_BODUNREGRST (0x1UL << 1)
/**< Brown Out Detector Unregulated Domain Reset */
-#define _RMU_RSTCAUSE_BODUNREGRST_SHIFT 1
/**< Shift value for RMU_BODUNREGRST */
-#define _RMU_RSTCAUSE_BODUNREGRST_MASK 0x2UL
/**< Bit mask for RMU_BODUNREGRST */
-#define _RMU_RSTCAUSE_BODUNREGRST_DEFAULT 0x00000000UL
/**< Mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_BODUNREGRST_DEFAULT
(_RMU_RSTCAUSE_BODUNREGRST_DEFAULT << 1) /**< Shifted mode DEFAULT for
RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_BODREGRST (0x1UL << 2)
/**< Brown Out Detector Regulated Domain Reset */
-#define _RMU_RSTCAUSE_BODREGRST_SHIFT 2
/**< Shift value for RMU_BODREGRST */
-#define _RMU_RSTCAUSE_BODREGRST_MASK 0x4UL
/**< Bit mask for RMU_BODREGRST */
-#define _RMU_RSTCAUSE_BODREGRST_DEFAULT 0x00000000UL
/**< Mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_BODREGRST_DEFAULT (_RMU_RSTCAUSE_BODREGRST_DEFAULT
<< 2) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_EXTRST (0x1UL << 3)
/**< External Pin Reset */
-#define _RMU_RSTCAUSE_EXTRST_SHIFT 3
/**< Shift value for RMU_EXTRST */
-#define _RMU_RSTCAUSE_EXTRST_MASK 0x8UL
/**< Bit mask for RMU_EXTRST */
-#define _RMU_RSTCAUSE_EXTRST_DEFAULT 0x00000000UL
/**< Mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_EXTRST_DEFAULT (_RMU_RSTCAUSE_EXTRST_DEFAULT <<
3) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_WDOGRST (0x1UL << 4)
/**< Watchdog Reset */
-#define _RMU_RSTCAUSE_WDOGRST_SHIFT 4
/**< Shift value for RMU_WDOGRST */
-#define _RMU_RSTCAUSE_WDOGRST_MASK 0x10UL
/**< Bit mask for RMU_WDOGRST */
-#define _RMU_RSTCAUSE_WDOGRST_DEFAULT 0x00000000UL
/**< Mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_WDOGRST_DEFAULT (_RMU_RSTCAUSE_WDOGRST_DEFAULT
<< 4) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_LOCKUPRST (0x1UL << 5)
/**< LOCKUP Reset */
-#define _RMU_RSTCAUSE_LOCKUPRST_SHIFT 5
/**< Shift value for RMU_LOCKUPRST */
-#define _RMU_RSTCAUSE_LOCKUPRST_MASK 0x20UL
/**< Bit mask for RMU_LOCKUPRST */
-#define _RMU_RSTCAUSE_LOCKUPRST_DEFAULT 0x00000000UL
/**< Mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_LOCKUPRST_DEFAULT (_RMU_RSTCAUSE_LOCKUPRST_DEFAULT
<< 5) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_SYSREQRST (0x1UL << 6)
/**< System Request Reset */
-#define _RMU_RSTCAUSE_SYSREQRST_SHIFT 6
/**< Shift value for RMU_SYSREQRST */
-#define _RMU_RSTCAUSE_SYSREQRST_MASK 0x40UL
/**< Bit mask for RMU_SYSREQRST */
-#define _RMU_RSTCAUSE_SYSREQRST_DEFAULT 0x00000000UL
/**< Mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_SYSREQRST_DEFAULT (_RMU_RSTCAUSE_SYSREQRST_DEFAULT
<< 6) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_EM4RST (0x1UL << 7)
/**< EM4 Reset */
-#define _RMU_RSTCAUSE_EM4RST_SHIFT 7
/**< Shift value for RMU_EM4RST */
-#define _RMU_RSTCAUSE_EM4RST_MASK 0x80UL
/**< Bit mask for RMU_EM4RST */
-#define _RMU_RSTCAUSE_EM4RST_DEFAULT 0x00000000UL
/**< Mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_EM4RST_DEFAULT (_RMU_RSTCAUSE_EM4RST_DEFAULT <<
7) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_EM4WURST (0x1UL << 8)
/**< EM4 Wake-up Reset */
-#define _RMU_RSTCAUSE_EM4WURST_SHIFT 8
/**< Shift value for RMU_EM4WURST */
-#define _RMU_RSTCAUSE_EM4WURST_MASK 0x100UL
/**< Bit mask for RMU_EM4WURST */
-#define _RMU_RSTCAUSE_EM4WURST_DEFAULT 0x00000000UL
/**< Mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_EM4WURST_DEFAULT (_RMU_RSTCAUSE_EM4WURST_DEFAULT
<< 8) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_BODAVDD0 (0x1UL << 9)
/**< AVDD0 Bod Reset */
-#define _RMU_RSTCAUSE_BODAVDD0_SHIFT 9
/**< Shift value for RMU_BODAVDD0 */
-#define _RMU_RSTCAUSE_BODAVDD0_MASK 0x200UL
/**< Bit mask for RMU_BODAVDD0 */
-#define _RMU_RSTCAUSE_BODAVDD0_DEFAULT 0x00000000UL
/**< Mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_BODAVDD0_DEFAULT (_RMU_RSTCAUSE_BODAVDD0_DEFAULT
<< 9) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_BODAVDD1 (0x1UL << 10)
/**< AVDD1 Bod Reset */
-#define _RMU_RSTCAUSE_BODAVDD1_SHIFT 10
/**< Shift value for RMU_BODAVDD1 */
-#define _RMU_RSTCAUSE_BODAVDD1_MASK 0x400UL
/**< Bit mask for RMU_BODAVDD1 */
-#define _RMU_RSTCAUSE_BODAVDD1_DEFAULT 0x00000000UL
/**< Mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_BODAVDD1_DEFAULT (_RMU_RSTCAUSE_BODAVDD1_DEFAULT
<< 10) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_BUBODVDDDREG (0x1UL << 11)
/**< Backup Brown Out Detector, VDD_DREG */
-#define _RMU_RSTCAUSE_BUBODVDDDREG_SHIFT 11
/**< Shift value for RMU_BUBODVDDDREG */
-#define _RMU_RSTCAUSE_BUBODVDDDREG_MASK 0x800UL
/**< Bit mask for RMU_BUBODVDDDREG */
-#define _RMU_RSTCAUSE_BUBODVDDDREG_DEFAULT 0x00000000UL
/**< Mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_BUBODVDDDREG_DEFAULT
(_RMU_RSTCAUSE_BUBODVDDDREG_DEFAULT << 11) /**< Shifted mode DEFAULT for
RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_BUBODBUVIN (0x1UL << 12)
/**< Backup Brown Out Detector, BU_VIN */
-#define _RMU_RSTCAUSE_BUBODBUVIN_SHIFT 12
/**< Shift value for RMU_BUBODBUVIN */
-#define _RMU_RSTCAUSE_BUBODBUVIN_MASK 0x1000UL
/**< Bit mask for RMU_BUBODBUVIN */
-#define _RMU_RSTCAUSE_BUBODBUVIN_DEFAULT 0x00000000UL
/**< Mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_BUBODBUVIN_DEFAULT
(_RMU_RSTCAUSE_BUBODBUVIN_DEFAULT << 12) /**< Shifted mode DEFAULT for
RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_BUBODUNREG (0x1UL << 13)
/**< Backup Brown Out Detector Unregulated Domain */
-#define _RMU_RSTCAUSE_BUBODUNREG_SHIFT 13
/**< Shift value for RMU_BUBODUNREG */
-#define _RMU_RSTCAUSE_BUBODUNREG_MASK 0x2000UL
/**< Bit mask for RMU_BUBODUNREG */
-#define _RMU_RSTCAUSE_BUBODUNREG_DEFAULT 0x00000000UL
/**< Mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_BUBODUNREG_DEFAULT
(_RMU_RSTCAUSE_BUBODUNREG_DEFAULT << 13) /**< Shifted mode DEFAULT for
RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_BUBODREG (0x1UL << 14)
/**< Backup Brown Out Detector Regulated Domain */
-#define _RMU_RSTCAUSE_BUBODREG_SHIFT 14
/**< Shift value for RMU_BUBODREG */
-#define _RMU_RSTCAUSE_BUBODREG_MASK 0x4000UL
/**< Bit mask for RMU_BUBODREG */
-#define _RMU_RSTCAUSE_BUBODREG_DEFAULT 0x00000000UL
/**< Mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_BUBODREG_DEFAULT (_RMU_RSTCAUSE_BUBODREG_DEFAULT
<< 14) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_BUMODERST (0x1UL << 15)
/**< Backup mode reset */
-#define _RMU_RSTCAUSE_BUMODERST_SHIFT 15
/**< Shift value for RMU_BUMODERST */
-#define _RMU_RSTCAUSE_BUMODERST_MASK 0x8000UL
/**< Bit mask for RMU_BUMODERST */
-#define _RMU_RSTCAUSE_BUMODERST_DEFAULT 0x00000000UL
/**< Mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_BUMODERST_DEFAULT (_RMU_RSTCAUSE_BUMODERST_DEFAULT
<< 15) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define _RMU_RSTCAUSE_RESETVALUE 0x00000000UL
/* Default value for RMU_RSTCAUSE */
+#define _RMU_RSTCAUSE_MASK 0x0000FFFFUL
/* Mask for RMU_RSTCAUSE */
+
+#define RMU_RSTCAUSE_PORST (0x1UL << 0)
/* Power On Reset */
+#define _RMU_RSTCAUSE_PORST_SHIFT 0
/* Shift value for RMU_PORST */
+#define _RMU_RSTCAUSE_PORST_MASK 0x1UL
/* Bit mask for RMU_PORST */
+#define _RMU_RSTCAUSE_PORST_DEFAULT 0x00000000UL
/* Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_PORST_DEFAULT (_RMU_RSTCAUSE_PORST_DEFAULT <<
0) /* Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_BODUNREGRST (0x1UL << 1)
/* Brown Out Detector Unregulated Domain Reset */
+#define _RMU_RSTCAUSE_BODUNREGRST_SHIFT 1
/* Shift value for RMU_BODUNREGRST */
+#define _RMU_RSTCAUSE_BODUNREGRST_MASK 0x2UL
/* Bit mask for RMU_BODUNREGRST */
+#define _RMU_RSTCAUSE_BODUNREGRST_DEFAULT 0x00000000UL
/* Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_BODUNREGRST_DEFAULT
(_RMU_RSTCAUSE_BODUNREGRST_DEFAULT << 1) /* Shifted mode DEFAULT for
RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_BODREGRST (0x1UL << 2)
/* Brown Out Detector Regulated Domain Reset */
+#define _RMU_RSTCAUSE_BODREGRST_SHIFT 2
/* Shift value for RMU_BODREGRST */
+#define _RMU_RSTCAUSE_BODREGRST_MASK 0x4UL
/* Bit mask for RMU_BODREGRST */
+#define _RMU_RSTCAUSE_BODREGRST_DEFAULT 0x00000000UL
/* Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_BODREGRST_DEFAULT (_RMU_RSTCAUSE_BODREGRST_DEFAULT
<< 2) /* Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_EXTRST (0x1UL << 3)
/* External Pin Reset */
+#define _RMU_RSTCAUSE_EXTRST_SHIFT 3
/* Shift value for RMU_EXTRST */
+#define _RMU_RSTCAUSE_EXTRST_MASK 0x8UL
/* Bit mask for RMU_EXTRST */
+#define _RMU_RSTCAUSE_EXTRST_DEFAULT 0x00000000UL
/* Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_EXTRST_DEFAULT (_RMU_RSTCAUSE_EXTRST_DEFAULT <<
3) /* Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_WDOGRST (0x1UL << 4)
/* Watchdog Reset */
+#define _RMU_RSTCAUSE_WDOGRST_SHIFT 4
/* Shift value for RMU_WDOGRST */
+#define _RMU_RSTCAUSE_WDOGRST_MASK 0x10UL
/* Bit mask for RMU_WDOGRST */
+#define _RMU_RSTCAUSE_WDOGRST_DEFAULT 0x00000000UL
/* Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_WDOGRST_DEFAULT (_RMU_RSTCAUSE_WDOGRST_DEFAULT
<< 4) /* Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_LOCKUPRST (0x1UL << 5)
/* LOCKUP Reset */
+#define _RMU_RSTCAUSE_LOCKUPRST_SHIFT 5
/* Shift value for RMU_LOCKUPRST */
+#define _RMU_RSTCAUSE_LOCKUPRST_MASK 0x20UL
/* Bit mask for RMU_LOCKUPRST */
+#define _RMU_RSTCAUSE_LOCKUPRST_DEFAULT 0x00000000UL
/* Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_LOCKUPRST_DEFAULT (_RMU_RSTCAUSE_LOCKUPRST_DEFAULT
<< 5) /* Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_SYSREQRST (0x1UL << 6)
/* System Request Reset */
+#define _RMU_RSTCAUSE_SYSREQRST_SHIFT 6
/* Shift value for RMU_SYSREQRST */
+#define _RMU_RSTCAUSE_SYSREQRST_MASK 0x40UL
/* Bit mask for RMU_SYSREQRST */
+#define _RMU_RSTCAUSE_SYSREQRST_DEFAULT 0x00000000UL
/* Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_SYSREQRST_DEFAULT (_RMU_RSTCAUSE_SYSREQRST_DEFAULT
<< 6) /* Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_EM4RST (0x1UL << 7)
/* EM4 Reset */
+#define _RMU_RSTCAUSE_EM4RST_SHIFT 7
/* Shift value for RMU_EM4RST */
+#define _RMU_RSTCAUSE_EM4RST_MASK 0x80UL
/* Bit mask for RMU_EM4RST */
+#define _RMU_RSTCAUSE_EM4RST_DEFAULT 0x00000000UL
/* Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_EM4RST_DEFAULT (_RMU_RSTCAUSE_EM4RST_DEFAULT <<
7) /* Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_EM4WURST (0x1UL << 8)
/* EM4 Wake-up Reset */
+#define _RMU_RSTCAUSE_EM4WURST_SHIFT 8
/* Shift value for RMU_EM4WURST */
+#define _RMU_RSTCAUSE_EM4WURST_MASK 0x100UL
/* Bit mask for RMU_EM4WURST */
+#define _RMU_RSTCAUSE_EM4WURST_DEFAULT 0x00000000UL
/* Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_EM4WURST_DEFAULT (_RMU_RSTCAUSE_EM4WURST_DEFAULT
<< 8) /* Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_BODAVDD0 (0x1UL << 9)
/* AVDD0 Bod Reset */
+#define _RMU_RSTCAUSE_BODAVDD0_SHIFT 9
/* Shift value for RMU_BODAVDD0 */
+#define _RMU_RSTCAUSE_BODAVDD0_MASK 0x200UL
/* Bit mask for RMU_BODAVDD0 */
+#define _RMU_RSTCAUSE_BODAVDD0_DEFAULT 0x00000000UL
/* Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_BODAVDD0_DEFAULT (_RMU_RSTCAUSE_BODAVDD0_DEFAULT
<< 9) /* Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_BODAVDD1 (0x1UL << 10)
/* AVDD1 Bod Reset */
+#define _RMU_RSTCAUSE_BODAVDD1_SHIFT 10
/* Shift value for RMU_BODAVDD1 */
+#define _RMU_RSTCAUSE_BODAVDD1_MASK 0x400UL
/* Bit mask for RMU_BODAVDD1 */
+#define _RMU_RSTCAUSE_BODAVDD1_DEFAULT 0x00000000UL
/* Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_BODAVDD1_DEFAULT (_RMU_RSTCAUSE_BODAVDD1_DEFAULT
<< 10) /* Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_BUBODVDDDREG (0x1UL << 11)
/* Backup Brown Out Detector, VDD_DREG */
+#define _RMU_RSTCAUSE_BUBODVDDDREG_SHIFT 11
/* Shift value for RMU_BUBODVDDDREG */
+#define _RMU_RSTCAUSE_BUBODVDDDREG_MASK 0x800UL
/* Bit mask for RMU_BUBODVDDDREG */
+#define _RMU_RSTCAUSE_BUBODVDDDREG_DEFAULT 0x00000000UL
/* Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_BUBODVDDDREG_DEFAULT
(_RMU_RSTCAUSE_BUBODVDDDREG_DEFAULT << 11) /* Shifted mode DEFAULT for
RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_BUBODBUVIN (0x1UL << 12)
/* Backup Brown Out Detector, BU_VIN */
+#define _RMU_RSTCAUSE_BUBODBUVIN_SHIFT 12
/* Shift value for RMU_BUBODBUVIN */
+#define _RMU_RSTCAUSE_BUBODBUVIN_MASK 0x1000UL
/* Bit mask for RMU_BUBODBUVIN */
+#define _RMU_RSTCAUSE_BUBODBUVIN_DEFAULT 0x00000000UL
/* Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_BUBODBUVIN_DEFAULT
(_RMU_RSTCAUSE_BUBODBUVIN_DEFAULT << 12) /* Shifted mode DEFAULT for
RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_BUBODUNREG (0x1UL << 13)
/* Backup Brown Out Detector Unregulated Domain */
+#define _RMU_RSTCAUSE_BUBODUNREG_SHIFT 13
/* Shift value for RMU_BUBODUNREG */
+#define _RMU_RSTCAUSE_BUBODUNREG_MASK 0x2000UL
/* Bit mask for RMU_BUBODUNREG */
+#define _RMU_RSTCAUSE_BUBODUNREG_DEFAULT 0x00000000UL
/* Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_BUBODUNREG_DEFAULT
(_RMU_RSTCAUSE_BUBODUNREG_DEFAULT << 13) /* Shifted mode DEFAULT for
RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_BUBODREG (0x1UL << 14)
/* Backup Brown Out Detector Regulated Domain */
+#define _RMU_RSTCAUSE_BUBODREG_SHIFT 14
/* Shift value for RMU_BUBODREG */
+#define _RMU_RSTCAUSE_BUBODREG_MASK 0x4000UL
/* Bit mask for RMU_BUBODREG */
+#define _RMU_RSTCAUSE_BUBODREG_DEFAULT 0x00000000UL
/* Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_BUBODREG_DEFAULT (_RMU_RSTCAUSE_BUBODREG_DEFAULT
<< 14) /* Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_BUMODERST (0x1UL << 15)
/* Backup mode reset */
+#define _RMU_RSTCAUSE_BUMODERST_SHIFT 15
/* Shift value for RMU_BUMODERST */
+#define _RMU_RSTCAUSE_BUMODERST_MASK 0x8000UL
/* Bit mask for RMU_BUMODERST */
+#define _RMU_RSTCAUSE_BUMODERST_DEFAULT 0x00000000UL
/* Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_BUMODERST_DEFAULT (_RMU_RSTCAUSE_BUMODERST_DEFAULT
<< 15) /* Shifted mode DEFAULT for RMU_RSTCAUSE */
/* Bit fields for RMU CMD */
-#define _RMU_CMD_RESETVALUE 0x00000000UL
/**< Default value for RMU_CMD */
-#define _RMU_CMD_MASK 0x00000001UL
/**< Mask for RMU_CMD */
+#define _RMU_CMD_RESETVALUE 0x00000000UL /*
Default value for RMU_CMD */
+#define _RMU_CMD_MASK 0x00000001UL /*
Mask for RMU_CMD */
-#define RMU_CMD_RCCLR (0x1UL << 0)
/**< Reset Cause Clear */
-#define _RMU_CMD_RCCLR_SHIFT 0
/**< Shift value for RMU_RCCLR */
-#define _RMU_CMD_RCCLR_MASK 0x1UL
/**< Bit mask for RMU_RCCLR */
-#define _RMU_CMD_RCCLR_DEFAULT 0x00000000UL
/**< Mode DEFAULT for RMU_CMD */
-#define RMU_CMD_RCCLR_DEFAULT (_RMU_CMD_RCCLR_DEFAULT << 0)
/**< Shifted mode DEFAULT for RMU_CMD */
+#define RMU_CMD_RCCLR (0x1UL << 0) /*
Reset Cause Clear */
+#define _RMU_CMD_RCCLR_SHIFT 0 /*
Shift value for RMU_RCCLR */
+#define _RMU_CMD_RCCLR_MASK 0x1UL /*
Bit mask for RMU_RCCLR */
+#define _RMU_CMD_RCCLR_DEFAULT 0x00000000UL /*
Mode DEFAULT for RMU_CMD */
+#define RMU_CMD_RCCLR_DEFAULT (_RMU_CMD_RCCLR_DEFAULT << 0) /*
Shifted mode DEFAULT for RMU_CMD */
#endif /* __ARCH_ARM_SRC_EFM32_HARDWARE_EFM32_RMU_H */
diff --git a/arch/arm/src/phy62xx/rom_sym_def.h
b/arch/arm/src/phy62xx/rom_sym_def.h
index 8653250e82..df4ce71baa 100644
--- a/arch/arm/src/phy62xx/rom_sym_def.h
+++ b/arch/arm/src/phy62xx/rom_sym_def.h
@@ -200,8 +200,8 @@
#define g_pLLcteQSample _symrom_g_pLLcteQSample
#define g_pmCounters _symrom_g_pmCounters
#define g_pPeriodicAdvInfo _symrom_g_pPeriodicAdvInfo
- #define ll_isIrkAllZero _symrom_ll_isIrkAllZero
- #define g_currentLocalAddrType _symrom_g_currentLocalAddrType
+ #define ll_isIrkAllZero _symrom_ll_isIrkAllZero
+ #define g_currentLocalAddrType _symrom_g_currentLocalAddrType
#define g_rfPhyClkSel _symrom_g_rfPhyClkSel
#define g_rfPhyDtmCmd _symrom_g_rfPhyDtmCmd
#define g_rfPhyDtmEvt _symrom_g_rfPhyDtmEvt
diff --git a/arch/arm64/src/a64/hardware/a64_twi.h
b/arch/arm64/src/a64/hardware/a64_twi.h
index 5c89ab09cc..091e09cbf1 100644
--- a/arch/arm64/src/a64/hardware/a64_twi.h
+++ b/arch/arm64/src/a64/hardware/a64_twi.h
@@ -36,15 +36,15 @@
/* TWI register offsets *****************************************************/
-#define A64_TWI_ADDR_OFFSET (0x00) /* 31:8 bit reserved,7-1
bit for slave addr,0 bit for GCE */
-#define A64_TWI_XADDR_OFFSET (0x04) /* 31:8 bit reserved,7-0
bit for second addr in 10bit addr */
-#define A64_TWI_DATA_OFFSET (0x08) /* 31:8 bit reserved,7-0
bit send or receive data byte */
+#define A64_TWI_ADDR_OFFSET (0x00) /* 31:8 bit reserved,7-1 bit for
slave addr,0 bit for GCE */
+#define A64_TWI_XADDR_OFFSET (0x04) /* 31:8 bit reserved,7-0 bit for
second addr in 10bit addr */
+#define A64_TWI_DATA_OFFSET (0x08) /* 31:8 bit reserved,7-0 bit send
or receive data byte */
#define A64_TWI_CNTR_OFFSET (0x0c) /* 31:8 bit reserved, INT_EN,
BUS_EN, M_STA, INT_FLAG, A_ACK */
-#define A64_TWI_STAT_OFFSET (0x10) /* 28 interrupt types +
0xF8 normal type = 29 */
-#define A64_TWI_CCR_OFFSET (0x14) /* 31:7 bit
reserved,6-3bit,CLK_M,2-0bit CLK_N */
-#define A64_TWI_SRST_OFFSET (0x18) /* 31:1 bit
reserved;0bit,write 1 to clear 0. */
-#define A64_TWI_EFR_OFFSET (0x1c) /* 31:2 bit reserved,1:0
bit data byte follow read comand */
-#define A64_TWI_LCR_OFFSET (0x20) /* 31:6 bits reserved
5:0 bit for sda&scl control*/
+#define A64_TWI_STAT_OFFSET (0x10) /* 28 interrupt types + 0xF8
normal type = 29 */
+#define A64_TWI_CCR_OFFSET (0x14) /* 31:7 bit
reserved,6-3bit,CLK_M,2-0bit CLK_N */
+#define A64_TWI_SRST_OFFSET (0x18) /* 31:1 bit reserved;0bit,write 1
to clear 0. */
+#define A64_TWI_EFR_OFFSET (0x1c) /* 31:2 bit reserved,1:0 bit data
byte follow read comand */
+#define A64_TWI_LCR_OFFSET (0x20) /* 31:6 bits reserved 5:0 bit for
sda&scl control*/
#define A64_TWI_DVFS_OFFSET (0x24) /* 31:3 bits reserved 2:0 bit for
dvfs control. only A10 support */
/* TWI register addresses ***************************************************/
@@ -93,8 +93,8 @@
/* TWI address register */
-#define TWI_GCE_EN (0x1<<0) /* general call address enable for
slave mode */
-#define TWI_ADDR_MASK (0x7f<<1) /* 7:1 bits */
+#define TWI_GCE_EN (0x1<<0) /* general call address enable for slave
mode */
+#define TWI_ADDR_MASK (0x7f<<1) /* 7:1 bits */
/* TWI extend address register */
@@ -150,21 +150,21 @@
/* 7:0 bits use only,default is 0xF8 */
-#define TWI_STAT_BUS_ERR (0x00) /* BUS ERROR */
+#define TWI_STAT_BUS_ERR (0x00) /* BUS ERROR */
/* Master mode use only */
-#define TWI_STAT_TX_STA (0x08) /* START condition transmitted */
-#define TWI_STAT_TX_RESTA (0x10) /* Repeated START condition transmitted
*/
-#define TWI_STAT_TX_AW_ACK (0x18) /* Address+Write bit transmitted, ACK
received */
-#define TWI_STAT_TX_AW_NAK (0x20) /* Address+Write bit transmitted, ACK
not received */
-#define TWI_STAT_TXD_ACK (0x28) /* data byte transmitted in master
mode,ack received */
-#define TWI_STAT_TXD_NAK (0x30) /* data byte transmitted in master mode
,ack not received */
-#define TWI_STAT_ARBLOST (0x38) /* arbitration lost in address or data
byte */
-#define TWI_STAT_TX_AR_ACK (0x40) /* Address+Read bit transmitted, ACK
received */
-#define TWI_STAT_TX_AR_NAK (0x48) /* Address+Read bit transmitted, ACK
not received */
-#define TWI_STAT_RXD_ACK (0x50) /* data byte received in master mode
,ack transmitted */
-#define TWI_STAT_RXD_NAK (0x58) /* date byte received in master
mode,not ack transmitted */
+#define TWI_STAT_TX_STA (0x08) /* START condition transmitted */
+#define TWI_STAT_TX_RESTA (0x10) /* Repeated START condition transmitted */
+#define TWI_STAT_TX_AW_ACK (0x18) /* Address+Write bit transmitted, ACK
received */
+#define TWI_STAT_TX_AW_NAK (0x20) /* Address+Write bit transmitted, ACK not
received */
+#define TWI_STAT_TXD_ACK (0x28) /* data byte transmitted in master
mode,ack received */
+#define TWI_STAT_TXD_NAK (0x30) /* data byte transmitted in master mode
,ack not received */
+#define TWI_STAT_ARBLOST (0x38) /* arbitration lost in address or data
byte */
+#define TWI_STAT_TX_AR_ACK (0x40) /* Address+Read bit transmitted, ACK
received */
+#define TWI_STAT_TX_AR_NAK (0x48) /* Address+Read bit transmitted, ACK not
received */
+#define TWI_STAT_RXD_ACK (0x50) /* data byte received in master mode ,ack
transmitted */
+#define TWI_STAT_RXD_NAK (0x58) /* date byte received in master mode,not
ack transmitted */
/* Slave mode use only */
diff --git a/arch/arm64/src/common/arm64_arch_timer.h
b/arch/arm64/src/common/arm64_arch_timer.h
index 4cdb2305a3..691e429ca2 100644
--- a/arch/arm64/src/common/arm64_arch_timer.h
+++ b/arch/arm64/src/common/arm64_arch_timer.h
@@ -36,9 +36,9 @@
#define CONFIG_ARM_TIMER_VIRTUAL_IRQ (GIC_PPI_INT_BASE + 11)
#define CONFIG_ARM_TIMER_HYP_IRQ (GIC_PPI_INT_BASE + 10)
-#define ARM_ARCH_TIMER_IRQ CONFIG_ARM_TIMER_VIRTUAL_IRQ
-#define ARM_ARCH_TIMER_PRIO IRQ_DEFAULT_PRIORITY
-#define ARM_ARCH_TIMER_FLAGS IRQ_TYPE_LEVEL
+#define ARM_ARCH_TIMER_IRQ CONFIG_ARM_TIMER_VIRTUAL_IRQ
+#define ARM_ARCH_TIMER_PRIO IRQ_DEFAULT_PRIORITY
+#define ARM_ARCH_TIMER_FLAGS IRQ_TYPE_LEVEL
/****************************************************************************
* Public Function Prototypes
diff --git a/arch/risc-v/src/esp32c3/esp32c3_bignum.h
b/arch/risc-v/src/esp32c3/esp32c3_bignum.h
index d6d269bd71..80d60430bb 100644
--- a/arch/risc-v/src/esp32c3/esp32c3_bignum.h
+++ b/arch/risc-v/src/esp32c3/esp32c3_bignum.h
@@ -43,14 +43,14 @@ extern "C"
* Pre-processor Macros
****************************************************************************/
-#define ESP32C3_ERR_MPI_FILE_IO_ERROR -0x0002 /**< An error
occurred while reading from or writing to a file. */
-#define ESP32C3_ERR_MPI_BAD_INPUT_DATA -0x0004 /**< Bad input
parameters to function. */
-#define ESP32C3_ERR_MPI_INVALID_CHARACTER -0x0006 /**< There is an
invalid character in the digit string. */
-#define ESP32C3_ERR_MPI_BUFFER_TOO_SMALL -0x0008 /**< The buffer is
too small to write to. */
-#define ESP32C3_ERR_MPI_NEGATIVE_VALUE -0x000A /**< The input
arguments are negative or result in illegal output. */
-#define ESP32C3_ERR_MPI_DIVISION_BY_ZERO -0x000C /**< The input
argument for division is zero, which is not allowed. */
-#define ESP32C3_ERR_MPI_NOT_ACCEPTABLE -0x000E /**< The input
arguments are not acceptable. */
-#define ESP32C3_ERR_MPI_ALLOC_FAILED -0x0010 /**< Memory
allocation failed. */
+#define ESP32C3_ERR_MPI_FILE_IO_ERROR -0x0002 /* An error occurred
while reading from or writing to a file. */
+#define ESP32C3_ERR_MPI_BAD_INPUT_DATA -0x0004 /* Bad input
parameters to function. */
+#define ESP32C3_ERR_MPI_INVALID_CHARACTER -0x0006 /* There is an
invalid character in the digit string. */
+#define ESP32C3_ERR_MPI_BUFFER_TOO_SMALL -0x0008 /* The buffer is too
small to write to. */
+#define ESP32C3_ERR_MPI_NEGATIVE_VALUE -0x000A /* The input
arguments are negative or result in illegal output. */
+#define ESP32C3_ERR_MPI_DIVISION_BY_ZERO -0x000C /* The input argument
for division is zero, which is not allowed. */
+#define ESP32C3_ERR_MPI_NOT_ACCEPTABLE -0x000E /* The input
arguments are not acceptable. */
+#define ESP32C3_ERR_MPI_ALLOC_FAILED -0x0010 /* Memory allocation
failed. */
#define ESP32C3_MPI_CHK(f, a) \
do \
@@ -72,7 +72,7 @@ extern "C"
/* Maximum size of MPIs allowed in bits and bytes for user-MPIs. */
#define ESP32C3_MPI_MAX_SIZE 1024
-/**< Maximum number of bits for usable MPIs. */
+/* Maximum number of bits for usable MPIs. */
#define ESP32C3_MPI_MAX_BITS (8 * ESP32C3_MPI_MAX_SIZE)
/****************************************************************************
diff --git a/arch/risc-v/src/esp32c3/esp32c3_efuse.h
b/arch/risc-v/src/esp32c3/esp32c3_efuse.h
index 91bb447b6f..f97b690a1e 100644
--- a/arch/risc-v/src/esp32c3/esp32c3_efuse.h
+++ b/arch/risc-v/src/esp32c3/esp32c3_efuse.h
@@ -46,37 +46,37 @@ extern "C"
typedef enum
{
- EFUSE_BLK0 = 0, /**< Number of eFuse BLOCK0. REPEAT_DATA
*/
+ EFUSE_BLK0 = 0, /* Number of eFuse BLOCK0. REPEAT_DATA */
- EFUSE_BLK1 = 1, /**< Number of eFuse BLOCK1.
MAC_SPI_8M_SYS */
+ EFUSE_BLK1 = 1, /* Number of eFuse BLOCK1.
MAC_SPI_8M_SYS */
- EFUSE_BLK2 = 2, /**< Number of eFuse BLOCK2.
SYS_DATA_PART1 */
- EFUSE_BLK_SYS_DATA_PART1 = 2, /**< Number of eFuse BLOCK2.
SYS_DATA_PART1 */
+ EFUSE_BLK2 = 2, /* Number of eFuse BLOCK2.
SYS_DATA_PART1 */
+ EFUSE_BLK_SYS_DATA_PART1 = 2, /* Number of eFuse BLOCK2.
SYS_DATA_PART1 */
- EFUSE_BLK3 = 3, /**< Number of eFuse BLOCK3. USER_DATA */
- EFUSE_BLK_USER_DATA = 3, /**< Number of eFuse BLOCK3. USER_DATA */
+ EFUSE_BLK3 = 3, /* Number of eFuse BLOCK3. USER_DATA */
+ EFUSE_BLK_USER_DATA = 3, /* Number of eFuse BLOCK3. USER_DATA */
- EFUSE_BLK4 = 4, /**< Number of eFuse BLOCK4. KEY0 */
- EFUSE_BLK_KEY0 = 4, /**< Number of eFuse BLOCK4. KEY0 */
+ EFUSE_BLK4 = 4, /* Number of eFuse BLOCK4. KEY0 */
+ EFUSE_BLK_KEY0 = 4, /* Number of eFuse BLOCK4. KEY0 */
- EFUSE_BLK5 = 5, /**< Number of eFuse BLOCK5. KEY1 */
- EFUSE_BLK_KEY1 = 5, /**< Number of eFuse BLOCK5. KEY1 */
+ EFUSE_BLK5 = 5, /* Number of eFuse BLOCK5. KEY1 */
+ EFUSE_BLK_KEY1 = 5, /* Number of eFuse BLOCK5. KEY1 */
- EFUSE_BLK6 = 6, /**< Number of eFuse BLOCK6. KEY2 */
- EFUSE_BLK_KEY2 = 6, /**< Number of eFuse BLOCK6. KEY2 */
+ EFUSE_BLK6 = 6, /* Number of eFuse BLOCK6. KEY2 */
+ EFUSE_BLK_KEY2 = 6, /* Number of eFuse BLOCK6. KEY2 */
- EFUSE_BLK7 = 7, /**< Number of eFuse BLOCK7. KEY3 */
- EFUSE_BLK_KEY3 = 7, /**< Number of eFuse BLOCK7. KEY3 */
+ EFUSE_BLK7 = 7, /* Number of eFuse BLOCK7. KEY3 */
+ EFUSE_BLK_KEY3 = 7, /* Number of eFuse BLOCK7. KEY3 */
- EFUSE_BLK8 = 8, /**< Number of eFuse BLOCK8. KEY4 */
- EFUSE_BLK_KEY4 = 8, /**< Number of eFuse BLOCK8. KEY4 */
+ EFUSE_BLK8 = 8, /* Number of eFuse BLOCK8. KEY4 */
+ EFUSE_BLK_KEY4 = 8, /* Number of eFuse BLOCK8. KEY4 */
- EFUSE_BLK9 = 9, /**< Number of eFuse BLOCK9. KEY5 */
- EFUSE_BLK_KEY5 = 9, /**< Number of eFuse BLOCK9. KEY5 */
+ EFUSE_BLK9 = 9, /* Number of eFuse BLOCK9. KEY5 */
+ EFUSE_BLK_KEY5 = 9, /* Number of eFuse BLOCK9. KEY5 */
EFUSE_BLK_KEY_MAX = 10,
- EFUSE_BLK10 = 10, /**< Number of eFuse BLOCK10.
SYS_DATA_PART2 */
- EFUSE_BLK_SYS_DATA_PART2 = 10, /**< Number of eFuse BLOCK10.
SYS_DATA_PART2 */
+ EFUSE_BLK10 = 10, /* Number of eFuse BLOCK10.
SYS_DATA_PART2 */
+ EFUSE_BLK_SYS_DATA_PART2 = 10, /* Number of eFuse BLOCK10.
SYS_DATA_PART2 */
EFUSE_BLK_MAX
} esp_efuse_block_t;
diff --git a/arch/risc-v/src/esp32c3/esp32c3_rsa.h
b/arch/risc-v/src/esp32c3/esp32c3_rsa.h
index cba4d767a3..51a3295c70 100644
--- a/arch/risc-v/src/esp32c3/esp32c3_rsa.h
+++ b/arch/risc-v/src/esp32c3/esp32c3_rsa.h
@@ -46,28 +46,28 @@ extern "C"
/* RSA Error codes */
-#define ESP32C3_ERR_RSA_BAD_INPUT_DATA -0x4080 /**< Bad
input parameters to function. */
-#define ESP32C3_ERR_RSA_INVALID_PADDING -0x4100 /**< Input
data contains invalid padding and is rejected. */
-#define ESP32C3_ERR_RSA_KEY_GEN_FAILED -0x4180 /**<
Something failed during generation of a key. */
-#define ESP32C3_ERR_RSA_KEY_CHECK_FAILED -0x4200 /**< Key
failed to pass the validity check of the library. */
-#define ESP32C3_ERR_RSA_PUBLIC_FAILED -0x4280 /**< The
public key operation failed. */
-#define ESP32C3_ERR_RSA_PRIVATE_FAILED -0x4300 /**< The
private key operation failed. */
-#define ESP32C3_ERR_RSA_VERIFY_FAILED -0x4380 /**< The
PKCS#1 verification failed. */
-#define ESP32C3_ERR_RSA_OUTPUT_TOO_LARGE -0x4400 /**< The
output buffer for decryption is not large enough. */
-#define ESP32C3_ERR_RSA_RNG_FAILED -0x4480 /**< The
random generator failed to generate non-zeros. */
+#define ESP32C3_ERR_RSA_BAD_INPUT_DATA -0x4080 /* Bad
input parameters to function. */
+#define ESP32C3_ERR_RSA_INVALID_PADDING -0x4100 /* Input
data contains invalid padding and is rejected. */
+#define ESP32C3_ERR_RSA_KEY_GEN_FAILED -0x4180 /*
Something failed during generation of a key. */
+#define ESP32C3_ERR_RSA_KEY_CHECK_FAILED -0x4200 /* Key
failed to pass the validity check of the library. */
+#define ESP32C3_ERR_RSA_PUBLIC_FAILED -0x4280 /* The
public key operation failed. */
+#define ESP32C3_ERR_RSA_PRIVATE_FAILED -0x4300 /* The
private key operation failed. */
+#define ESP32C3_ERR_RSA_VERIFY_FAILED -0x4380 /* The
PKCS#1 verification failed. */
+#define ESP32C3_ERR_RSA_OUTPUT_TOO_LARGE -0x4400 /* The
output buffer for decryption is not large enough. */
+#define ESP32C3_ERR_RSA_RNG_FAILED -0x4480 /* The
random generator failed to generate non-zeros. */
/* RSA constants */
-#define ESP32C3_RSA_PUBLIC 0 /**< Request private key operation. */
-#define ESP32C3_RSA_PRIVATE 1 /**< Request public key operation. */
+#define ESP32C3_RSA_PUBLIC 0 /* Request private key operation. */
+#define ESP32C3_RSA_PRIVATE 1 /* Request public key operation. */
-#define ESP32C3_RSA_PKCS_V15 0 /**< Use PKCS#1 v1.5 encoding. */
-#define ESP32C3_RSA_PKCS_V21 1 /**< Use PKCS#1 v2.1 encoding. */
+#define ESP32C3_RSA_PKCS_V15 0 /* Use PKCS#1 v1.5 encoding. */
+#define ESP32C3_RSA_PKCS_V21 1 /* Use PKCS#1 v2.1 encoding. */
-#define ESP32C3_RSA_SIGN 1 /**< Identifier for RSA signature
operations. */
-#define ESP32C3_RSA_CRYPT 2 /**< Identifier for RSA encryption and
decryption operations. */
+#define ESP32C3_RSA_SIGN 1 /* Identifier for RSA signature
operations. */
+#define ESP32C3_RSA_CRYPT 2 /* Identifier for RSA encryption and
decryption operations. */
-#define ESP32C3_RSA_SALT_LEN_ANY -1
+#define ESP32C3_RSA_SALT_LEN_ANY -1
/****************************************************************************
* Public Types
@@ -79,8 +79,8 @@ extern "C"
struct esp32c3_rsa_context_s
{
- int ver; /* Always 0 */
- size_t len; /* The size of \p N in Bytes */
+ int ver; /* Always 0 */
+ size_t len; /* The size of \p N in Bytes */
struct esp32c3_mpi_s N; /* The public modulus */
struct esp32c3_mpi_s E; /* The public exponent */
@@ -101,8 +101,8 @@ struct esp32c3_rsa_context_s
struct esp32c3_mpi_s VI; /* The cached blinding value */
struct esp32c3_mpi_s VF; /* The cached un-blinding value */
- int padding; /* Selects padding mode */
- int hash_id; /* Hash identifier */
+ int padding; /* Selects padding mode */
+ int hash_id; /* Hash identifier */
};
/****************************************************************************
diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_iomux.h
b/arch/risc-v/src/esp32c3/hardware/esp32c3_iomux.h
index bfaf1ff5f2..f3c4f29d11 100644
--- a/arch/risc-v/src/esp32c3/hardware/esp32c3_iomux.h
+++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_iomux.h
@@ -132,31 +132,31 @@
#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD)
#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL,
FUNC)
-#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_XTAL_32K_P_U
-#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_XTAL_32K_N_U
-#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_GPIO2_U
-#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_GPIO3_U
-#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_MTMS_U
-#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_MTDI_U
-#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_MTCK_U
-#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_MTDO_U
-#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_GPIO8_U
-#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_GPIO9_U
-#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_GPIO10_U
-#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_VDD_SPI_U
-#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_SPIHD_U
-#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_SPIWP_U
-#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_SPICS0_U
-#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_SPICLK_U
-#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_SPID_U
-#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_SPIQ_U
-#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_GPIO18_U
-#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_GPIO19_U
-#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_U0RXD_U
-#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U0TXD_U
+#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_XTAL_32K_P_U
+#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_XTAL_32K_N_U
+#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_GPIO2_U
+#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_GPIO3_U
+#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_MTMS_U
+#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_MTDI_U
+#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_MTCK_U
+#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_MTDO_U
+#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_GPIO8_U
+#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_GPIO9_U
+#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_GPIO10_U
+#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_VDD_SPI_U
+#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_SPIHD_U
+#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_SPIWP_U
+#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_SPICS0_U
+#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_SPICLK_U
+#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_SPID_U
+#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_SPIQ_U
+#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_GPIO18_U
+#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_GPIO19_U
+#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_U0RXD_U
+#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U0TXD_U
#define FUNC_GPIO_GPIO 1
-#define PIN_FUNC_GPIO 1
+#define PIN_FUNC_GPIO 1
#define GPIO_PAD_PULLUP(num)
do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_PULLDOWN(num)
do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_rtccntl.h
b/arch/risc-v/src/esp32c3/hardware/esp32c3_rtccntl.h
index 4ef6c8a804..f43aaa794b 100644
--- a/arch/risc-v/src/esp32c3/hardware/esp32c3_rtccntl.h
+++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_rtccntl.h
@@ -70,8 +70,8 @@
#define RTC_WDT_RESET_LENGTH_1600_NS 6
#define RTC_WDT_RESET_LENGTH_3200_NS 7
-#define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG
-#define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG
+#define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG
+#define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG
#define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0000)
diff --git a/arch/risc-v/src/hpm6750/hpm6750_serial.h
b/arch/risc-v/src/hpm6750/hpm6750_serial.h
index dd8504f724..d403ebefe6 100644
--- a/arch/risc-v/src/hpm6750/hpm6750_serial.h
+++ b/arch/risc-v/src/hpm6750/hpm6750_serial.h
@@ -31,7 +31,7 @@
#ifndef __ASSEMBLY__
-/* @brief Parity */
+/* Parity */
typedef enum parity
{
@@ -42,7 +42,7 @@ typedef enum parity
parity_always_0,
} parity_setting_t;
-/* @brief Stop bits */
+/* Stop bits */
typedef enum num_of_stop_bits
{
@@ -51,7 +51,7 @@ typedef enum num_of_stop_bits
stop_bits_2,
} num_of_stop_bits_t;
-/* @brief Word length */
+/* Word length */
typedef enum word_length
{
@@ -61,7 +61,7 @@ typedef enum word_length
word_length_8_bits,
} word_length_t;
-/* @brief UART fifo trigger levels */
+/* UART fifo trigger levels */
typedef enum uart_fifo_trg_lvl
{
@@ -76,14 +76,14 @@ typedef enum uart_fifo_trg_lvl
uart_tx_fifo_trg_lt_one_quarter = 3,
} uart_fifo_trg_lvl_t;
-/* @brief UART signals */
+/* UART signals */
typedef enum uart_signal
{
uart_signal_rts = UART_MCR_RTS_MASK,
} uart_signal_t;
-/* @brief UART signal levels */
+/* UART signal levels */
typedef enum uart_signal_level
{
@@ -91,7 +91,7 @@ typedef enum uart_signal_level
uart_signal_level_low,
} uart_signal_level_t;
-/* @brief UART modem status */
+/* UART modem status */
typedef enum uart_modem_stat
{
@@ -99,7 +99,7 @@ typedef enum uart_modem_stat
uart_modem_stat_dcts_changed = UART_MSR_DCTS_MASK,
} uart_modem_stat_t;
-/* @brief UART interrupt enable masks */
+/* UART interrupt enable masks */
typedef enum uart_intr_enable
{
@@ -112,7 +112,7 @@ typedef enum uart_intr_enable
#endif
} uart_intr_enable_t;
-/* @brief UART interrupt IDs */
+/* UART interrupt IDs */
typedef enum uart_intr_id
{
@@ -123,7 +123,7 @@ typedef enum uart_intr_id
uart_intr_id_rx_timeout = 0xc,
} uart_intr_id_t;
-/* @brief UART status */
+/* UART status */
typedef enum uart_stat
{
@@ -137,55 +137,49 @@ typedef enum uart_stat
uart_stat_rx_fifo_error = UART_LSR_ERRF_MASK,
} uart_stat_t;
-/**
- * @brief UART modem config
- */
+/* UART modem config */
typedef struct uart_modem_config
{
- bool auto_flow_ctrl_en; /**< Auto flow control enable flag */
- bool loop_back_en; /**< Loop back enable flag */
- bool set_rts_high; /**< Set signal RTS level high flag */
+ bool auto_flow_ctrl_en; /* Auto flow control enable flag */
+ bool loop_back_en; /* Loop back enable flag */
+ bool set_rts_high; /* Set signal RTS level high flag */
} uart_modem_config_t;
#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) &&
(UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1)
-/**
- * @brief UART RX Line Idle detection conditions
- */
+/* UART RX Line Idle detection conditions */
typedef enum hpm_uart_rxline_idle_cond
{
- uart_rxline_idle_cond_rxline_logic_one = 0, /**< Treat as idle if
the RX Line high duration exceeds threshold */
- uart_rxline_idle_cond_state_machine_idle = 1 /**< Treat as idle if
the RX state machine idle state duration exceeds threshold */
+ uart_rxline_idle_cond_rxline_logic_one = 0, /* Treat as idle if the
RX Line high duration exceeds threshold */
+ uart_rxline_idle_cond_state_machine_idle = 1 /* Treat as idle if the
RX state machine idle state duration exceeds threshold */
} uart_rxline_idle_cond_t;
typedef struct hpm_uart_rxline_idle_detect_config
{
- bool detect_enable; /**< RX Line Idle detection flag */
- bool detect_irq_enable; /**< Enable RX Line Idle detection
interrupt */
- uart_rxline_idle_cond_t idle_cond; /**< RX Line Idle detection condition */
- uint8_t threshold; /**< UART RX Line Idle detection
threshold, in terms of bits */
+ bool detect_enable; /* RX Line Idle detection flag */
+ bool detect_irq_enable; /* Enable RX Line Idle detection
interrupt */
+ uart_rxline_idle_cond_t idle_cond; /* RX Line Idle detection condition */
+ uint8_t threshold; /* UART RX Line Idle detection
threshold, in terms of bits */
} uart_rxline_idle_config_t;
#endif
-/**
- * @brief UART config
- */
+/* UART config */
typedef struct hpm_uart_config
{
- uint32_t src_freq_in_hz; /**< Source clock frequency in
Hz */
- uint32_t baudrate; /**< Baudrate */
- uint8_t num_of_stop_bits; /**< Number of stop bits */
- uint8_t word_length; /**< Word length */
- uint8_t parity; /**< Parity */
- uint8_t tx_fifo_level; /**< TX Fifo level */
- uint8_t rx_fifo_level; /**< RX Fifo level */
- bool dma_enable; /**< DMA Enable flag */
- bool fifo_enable; /**< Fifo Enable flag */
- uart_modem_config_t modem_config; /**< Modem config */
+ uint32_t src_freq_in_hz; /* Source clock frequency in Hz
*/
+ uint32_t baudrate; /* Baudrate */
+ uint8_t num_of_stop_bits; /* Number of stop bits */
+ uint8_t word_length; /* Word length */
+ uint8_t parity; /* Parity */
+ uint8_t tx_fifo_level; /* TX Fifo level */
+ uint8_t rx_fifo_level; /* RX Fifo level */
+ bool dma_enable; /* DMA Enable flag */
+ bool fifo_enable; /* Fifo Enable flag */
+ uart_modem_config_t modem_config; /* Modem config */
#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) &&
(UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1)
- uart_rxline_idle_config_t rxidle_config; /**< RX Idle configuration */
+ uart_rxline_idle_config_t rxidle_config; /* RX Idle configuration */
#endif
} uart_config_t;
diff --git a/arch/risc-v/src/litex/hardware/litex_uart.h
b/arch/risc-v/src/litex/hardware/litex_uart.h
index f6affba58b..aadc73dc50 100644
--- a/arch/risc-v/src/litex/hardware/litex_uart.h
+++ b/arch/risc-v/src/litex/hardware/litex_uart.h
@@ -42,7 +42,7 @@
# define LITEX_UART0_PHY_TUNING_WORD 0xf0002000L
#endif
-#define UART_EV_TX 0x1
-#define UART_EV_RX 0x2
+#define UART_EV_TX 0x1
+#define UART_EV_RX 0x2
#endif /* _ARCH_RISCV_SRC_LITEX_CHIP_LITEX_UART_H */
diff --git a/arch/x86/include/i486/irq.h b/arch/x86/include/i486/irq.h
index ffad1ece32..ce6c58bade 100644
--- a/arch/x86/include/i486/irq.h
+++ b/arch/x86/include/i486/irq.h
@@ -138,7 +138,7 @@
* change occurred.
*/
-#define TOP_PUSHA REG_IRQNO
+#define TOP_PUSHA REG_IRQNO
#define BOTTOM_PRIO (XCPTCONTEXT_REGS-REG_IRQNO)
#define BOTTOM_NOPRIO (REG_SP-REG_IRQNO)
diff --git a/arch/xtensa/include/esp32/memory_layout.h
b/arch/xtensa/include/esp32/memory_layout.h
index 5d25843af3..d0117b5e40 100644
--- a/arch/xtensa/include/esp32/memory_layout.h
+++ b/arch/xtensa/include/esp32/memory_layout.h
@@ -122,9 +122,9 @@
#endif
#ifdef CONFIG_XTENSA_IMEM_USE_SEPARATE_HEAP
-# define XTENSA_IMEM_REGION_SIZE CONFIG_XTENSA_IMEM_REGION_SIZE
+# define XTENSA_IMEM_REGION_SIZE CONFIG_XTENSA_IMEM_REGION_SIZE
#else
-# define XTENSA_IMEM_REGION_SIZE 0
+# define XTENSA_IMEM_REGION_SIZE 0
#endif
/* Internal heap starts at the end of the ROM data.
diff --git a/arch/xtensa/src/esp32/chip_macros.h
b/arch/xtensa/src/esp32/chip_macros.h
index 2616070874..2a68cedf45 100644
--- a/arch/xtensa/src/esp32/chip_macros.h
+++ b/arch/xtensa/src/esp32/chip_macros.h
@@ -87,7 +87,7 @@
#ifdef __ASSEMBLY__
#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15
- .global g_cpu_intstack_top
+ .global g_cpu_intstack_top
#endif /* CONFIG_SMP && CONFIG_ARCH_INTERRUPTSTACK > 15 */
#endif /* __ASSEMBLY__ */
diff --git a/arch/xtensa/src/esp32/hardware/esp32_dport.h
b/arch/xtensa/src/esp32/hardware/esp32_dport.h
index 330b431b8b..388860935e 100644
--- a/arch/xtensa/src/esp32/hardware/esp32_dport.h
+++ b/arch/xtensa/src/esp32/hardware/esp32_dport.h
@@ -199,13 +199,13 @@
/* DPORT_CPUPERIOD_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-#define DPORT_CPUPERIOD_SEL 0x00000003
-#define DPORT_CPUPERIOD_SEL_M
((DPORT_CPUPERIOD_SEL_V)<<(DPORT_CPUPERIOD_SEL_S))
-#define DPORT_CPUPERIOD_SEL_V 0x3
-#define DPORT_CPUPERIOD_SEL_S 0
+#define DPORT_CPUPERIOD_SEL 0x00000003
+#define DPORT_CPUPERIOD_SEL_M
((DPORT_CPUPERIOD_SEL_V)<<(DPORT_CPUPERIOD_SEL_S))
+#define DPORT_CPUPERIOD_SEL_V 0x3
+#define DPORT_CPUPERIOD_SEL_S 0
#define DPORT_CPUPERIOD_SEL_80 0
#define DPORT_CPUPERIOD_SEL_160 1
-#define DPORT_CPUPERIOD_SEL_240 2
+#define DPORT_CPUPERIOD_SEL_240 2
#define DPORT_PRO_CACHE_CTRL_REG (DR_REG_DPORT_BASE + 0x040)
diff --git a/arch/xtensa/src/esp32/hardware/esp32_tim.h
b/arch/xtensa/src/esp32/hardware/esp32_tim.h
index c09203d145..14ed263a51 100644
--- a/arch/xtensa/src/esp32/hardware/esp32_tim.h
+++ b/arch/xtensa/src/esp32/hardware/esp32_tim.h
@@ -29,23 +29,23 @@
/* Offsets relative to each timer instance memory base */
-#define TIM_CONFIG_OFFSET 0x00
-#define TIM_LOAD_LO_OFFSET 0x0018
-#define TIM_LOAD_HI_OFFSET 0x001c
-#define TIM_LOAD_OFFSET 0x0020
+#define TIM_CONFIG_OFFSET 0x00
+#define TIM_LOAD_LO_OFFSET 0x0018
+#define TIM_LOAD_HI_OFFSET 0x001c
+#define TIM_LOAD_OFFSET 0x0020
#define TIMG_ALARM_LO_OFFSET 0x0010
#define TIMG_ALARM_HI_OFFSET 0x0014
-#define TIM_UPDATE_OFFSET 0x000c
-#define TIM_LO_OFFSET 0x0004
-#define TIM_HI_OFFSET 0x0008
-#define SHIFT_32 32
-#define TIM0_CLR_OFFSET 0x00a4
-#define TIM1_CLR_OFFSET 0x0080
-#define TIM0_INT_ST_OFFSET 0x00A0
-#define TIM1_INT_ST_OFFSET 0x007c
-#define TIM0_INT_ENA_OFFSET 0x0098
-#define TIM1_INT_ENA_OFFSET 0x0074
-#define LOW_32_MASK 0xffffffff
+#define TIM_UPDATE_OFFSET 0x000c
+#define TIM_LO_OFFSET 0x0004
+#define TIM_HI_OFFSET 0x0008
+#define SHIFT_32 32
+#define TIM0_CLR_OFFSET 0x00a4
+#define TIM1_CLR_OFFSET 0x0080
+#define TIM0_INT_ST_OFFSET 0x00A0
+#define TIM1_INT_ST_OFFSET 0x007c
+#define TIM0_INT_ENA_OFFSET 0x0098
+#define TIM1_INT_ENA_OFFSET 0x0074
+#define LOW_32_MASK 0xffffffff
/* WDT defines */
@@ -101,7 +101,7 @@
/* Description: When set timer 0 time-base counter is enabled. */
-#define TIMG_T0_EN (BIT(31))
+#define TIMG_T0_EN (BIT(31))
#define TIMG_T0_EN_M (BIT(31))
#define TIMG_T0_EN_V 0x1
#define TIMG_T0_EN_S 31
@@ -112,7 +112,7 @@
* When cleared timer 0 time-base counter decrement.
*/
-#define TIMG_T0_INCREASE (BIT(30))
+#define TIMG_T0_INCREASE (BIT(30))
#define TIMG_T0_INCREASE_M (BIT(30))
#define TIMG_T0_INCREASE_V 0x1
#define TIMG_T0_INCREASE_S 30
@@ -121,7 +121,7 @@
/* Description: When set timer 0 auto-reload at alarming is enabled. */
-#define TIMG_T0_AUTORELOAD (BIT(29))
+#define TIMG_T0_AUTORELOAD (BIT(29))
#define TIMG_T0_AUTORELOAD_M (BIT(29))
#define TIMG_T0_AUTORELOAD_V 0x1
#define TIMG_T0_AUTORELOAD_S 29
@@ -130,7 +130,7 @@
/* Description: Timer 0 clock (T0_clk) prescale value. */
-#define TIMG_T0_DIVIDER 0x0000FFFF
+#define TIMG_T0_DIVIDER 0x0000FFFF
#define TIMG_T0_DIVIDER_M ((TIMG_T0_DIVIDER_V)<<(TIMG_T0_DIVIDER_S))
#define TIMG_T0_DIVIDER_V 0xFFFF
#define TIMG_T0_DIVIDER_S 13
@@ -139,7 +139,7 @@
/* Description: When set edge type interrupt will be generated during alarm */
-#define TIMG_T0_EDGE_INT_EN (BIT(12))
+#define TIMG_T0_EDGE_INT_EN (BIT(12))
#define TIMG_T0_EDGE_INT_EN_M (BIT(12))
#define TIMG_T0_EDGE_INT_EN_V 0x1
#define TIMG_T0_EDGE_INT_EN_S 12
@@ -150,7 +150,7 @@
* will be generated during alarm
*/
-#define TIMG_T0_LEVEL_INT_EN (BIT(11))
+#define TIMG_T0_LEVEL_INT_EN (BIT(11))
#define TIMG_T0_LEVEL_INT_EN_M (BIT(11))
#define TIMG_T0_LEVEL_INT_EN_V 0x1
#define TIMG_T0_LEVEL_INT_EN_S 11
@@ -159,7 +159,7 @@
/* Description: When set alarm is enabled */
-#define TIMG_T0_ALARM_EN (BIT(10))
+#define TIMG_T0_ALARM_EN (BIT(10))
#define TIMG_T0_ALARM_EN_M (BIT(10))
#define TIMG_T0_ALARM_EN_V 0x1
#define TIMG_T0_ALARM_EN_S 10
@@ -172,7 +172,7 @@
* value lower 32 bits.
*/
-#define TIMG_T0_LO 0xFFFFFFFF
+#define TIMG_T0_LO 0xFFFFFFFF
#define TIMG_T0_LO_M ((TIMG_T0_LO_V)<<(TIMG_T0_LO_S))
#define TIMG_T0_LO_V 0xFFFFFFFF
#define TIMG_T0_LO_S 0
@@ -185,7 +185,7 @@
* higher 32 bits.
*/
-#define TIMG_T0_HI 0xFFFFFFFF
+#define TIMG_T0_HI 0xFFFFFFFF
#define TIMG_T0_HI_M ((TIMG_T0_HI_V)<<(TIMG_T0_HI_S))
#define TIMG_T0_HI_V 0xFFFFFFFF
#define TIMG_T0_HI_S 0
@@ -199,7 +199,7 @@
* (timer 0 current value will be stored in registers above).
*/
-#define TIMG_T0_UPDATE 0xFFFFFFFF
+#define TIMG_T0_UPDATE 0xFFFFFFFF
#define TIMG_T0_UPDATE_M ((TIMG_T0_UPDATE_V)<<(TIMG_T0_UPDATE_S))
#define TIMG_T0_UPDATE_V 0xFFFFFFFF
#define TIMG_T0_UPDATE_S 0
@@ -212,7 +212,7 @@
* will trigger the alarm.
*/
-#define TIMG_T0_ALARM_LO 0xFFFFFFFF
+#define TIMG_T0_ALARM_LO 0xFFFFFFFF
#define TIMG_T0_ALARM_LO_M ((TIMG_T0_ALARM_LO_V)<<(TIMG_T0_ALARM_LO_S))
#define TIMG_T0_ALARM_LO_V 0xFFFFFFFF
#define TIMG_T0_ALARM_LO_S 0
@@ -225,7 +225,7 @@
* will trigger the alarm.
*/
-#define TIMG_T0_ALARM_HI 0xFFFFFFFF
+#define TIMG_T0_ALARM_HI 0xFFFFFFFF
#define TIMG_T0_ALARM_HI_M ((TIMG_T0_ALARM_HI_V)<<(TIMG_T0_ALARM_HI_S))
#define TIMG_T0_ALARM_HI_V 0xFFFFFFFF
#define TIMG_T0_ALARM_HI_S 0
@@ -238,7 +238,7 @@
* time-base counter.
*/
-#define TIMG_T0_LOAD_LO 0xFFFFFFFF
+#define TIMG_T0_LOAD_LO 0xFFFFFFFF
#define TIMG_T0_LOAD_LO_M ((TIMG_T0_LOAD_LO_V)<<(TIMG_T0_LOAD_LO_S))
#define TIMG_T0_LOAD_LO_V 0xFFFFFFFF
#define TIMG_T0_LOAD_LO_S 0
@@ -251,7 +251,7 @@
* time-base counter.
*/
-#define TIMG_T0_LOAD_HI 0xFFFFFFFF
+#define TIMG_T0_LOAD_HI 0xFFFFFFFF
#define TIMG_T0_LOAD_HI_M ((TIMG_T0_LOAD_HI_V)<<(TIMG_T0_LOAD_HI_S))
#define TIMG_T0_LOAD_HI_V 0xFFFFFFFF
#define TIMG_T0_LOAD_HI_S 0
@@ -264,7 +264,7 @@
* time-base counter reload.
*/
-#define TIMG_T0_LOAD 0xFFFFFFFF
+#define TIMG_T0_LOAD 0xFFFFFFFF
#define TIMG_T0_LOAD_M ((TIMG_T0_LOAD_V)<<(TIMG_T0_LOAD_S))
#define TIMG_T0_LOAD_V 0xFFFFFFFF
#define TIMG_T0_LOAD_S 0
@@ -275,7 +275,7 @@
/* Description: When set timer 1 time-base counter is enabled. */
-#define TIMG_T1_EN (BIT(31))
+#define TIMG_T1_EN (BIT(31))
#define TIMG_T1_EN_M (BIT(31))
#define TIMG_T1_EN_V 0x1
#define TIMG_T1_EN_S 31
@@ -286,7 +286,7 @@
* When cleared timer 1 time-base counter decrement.
*/
-#define TIMG_T1_INCREASE (BIT(30))
+#define TIMG_T1_INCREASE (BIT(30))
#define TIMG_T1_INCREASE_M (BIT(30))
#define TIMG_T1_INCREASE_V 0x1
#define TIMG_T1_INCREASE_S 30
@@ -295,7 +295,7 @@
/* Description: When set timer 1 auto-reload at alarming is enabled. */
-#define TIMG_T1_AUTORELOAD (BIT(29))
+#define TIMG_T1_AUTORELOAD (BIT(29))
#define TIMG_T1_AUTORELOAD_M (BIT(29))
#define TIMG_T1_AUTORELOAD_V 0x1
#define TIMG_T1_AUTORELOAD_S 29
@@ -304,7 +304,7 @@
/* Description: Timer 1 clock (T1_clk) prescale value. */
-#define TIMG_T1_DIVIDER 0x0000FFFF
+#define TIMG_T1_DIVIDER 0x0000FFFF
#define TIMG_T1_DIVIDER_M ((TIMG_T1_DIVIDER_V)<<(TIMG_T1_DIVIDER_S))
#define TIMG_T1_DIVIDER_V 0xFFFF
#define TIMG_T1_DIVIDER_S 13
@@ -315,7 +315,7 @@
* will be generated during alarm.
*/
-#define TIMG_T1_EDGE_INT_EN (BIT(12))
+#define TIMG_T1_EDGE_INT_EN (BIT(12))
#define TIMG_T1_EDGE_INT_EN_M (BIT(12))
#define TIMG_T1_EDGE_INT_EN_V 0x1
#define TIMG_T1_EDGE_INT_EN_S 12
@@ -326,7 +326,7 @@
* during alarm.
*/
-#define TIMG_T1_LEVEL_INT_EN (BIT(11))
+#define TIMG_T1_LEVEL_INT_EN (BIT(11))
#define TIMG_T1_LEVEL_INT_EN_M (BIT(11))
#define TIMG_T1_LEVEL_INT_EN_V 0x1
#define TIMG_T1_LEVEL_INT_EN_S 11
@@ -335,7 +335,7 @@
/* Description: When set alarm is enabled. */
-#define TIMG_T1_ALARM_EN (BIT(10))
+#define TIMG_T1_ALARM_EN (BIT(10))
#define TIMG_T1_ALARM_EN_M (BIT(10))
#define TIMG_T1_ALARM_EN_V 0x1
#define TIMG_T1_ALARM_EN_S 10
@@ -348,7 +348,7 @@
* value lower 32 bits.
*/
-#define TIMG_T1_LO 0xFFFFFFFF
+#define TIMG_T1_LO 0xFFFFFFFF
#define TIMG_T1_LO_M ((TIMG_T1_LO_V)<<(TIMG_T1_LO_S))
#define TIMG_T1_LO_V 0xFFFFFFFF
#define TIMG_T1_LO_S 0
@@ -361,7 +361,7 @@
* higher 32 bits.
*/
-#define TIMG_T1_HI 0xFFFFFFFF
+#define TIMG_T1_HI 0xFFFFFFFF
#define TIMG_T1_HI_M ((TIMG_T1_HI_V)<<(TIMG_T1_HI_S))
#define TIMG_T1_HI_V 0xFFFFFFFF
#define TIMG_T1_HI_S 0
@@ -375,7 +375,7 @@
* (timer 1 current value will be stored in registers above).
*/
-#define TIMG_T1_UPDATE 0xFFFFFFFF
+#define TIMG_T1_UPDATE 0xFFFFFFFF
#define TIMG_T1_UPDATE_M ((TIMG_T1_UPDATE_V)<<(TIMG_T1_UPDATE_S))
#define TIMG_T1_UPDATE_V 0xFFFFFFFF
#define TIMG_T1_UPDATE_S 0
@@ -388,7 +388,7 @@
* trigger the alarm
*/
-#define TIMG_T1_ALARM_LO 0xFFFFFFFF
+#define TIMG_T1_ALARM_LO 0xFFFFFFFF
#define TIMG_T1_ALARM_LO_M ((TIMG_T1_ALARM_LO_V)<<(TIMG_T1_ALARM_LO_S))
#define TIMG_T1_ALARM_LO_V 0xFFFFFFFF
#define TIMG_T1_ALARM_LO_S 0
@@ -401,7 +401,7 @@
* trigger the alarm.
*/
-#define TIMG_T1_ALARM_HI 0xFFFFFFFF
+#define TIMG_T1_ALARM_HI 0xFFFFFFFF
#define TIMG_T1_ALARM_HI_M ((TIMG_T1_ALARM_HI_V)<<(TIMG_T1_ALARM_HI_S))
#define TIMG_T1_ALARM_HI_V 0xFFFFFFFF
#define TIMG_T1_ALARM_HI_S 0
@@ -414,7 +414,7 @@
* timer 1 time-base counter.
*/
-#define TIMG_T1_LOAD_LO 0xFFFFFFFF
+#define TIMG_T1_LOAD_LO 0xFFFFFFFF
#define TIMG_T1_LOAD_LO_M ((TIMG_T1_LOAD_LO_V)<<(TIMG_T1_LOAD_LO_S))
#define TIMG_T1_LOAD_LO_V 0xFFFFFFFF
#define TIMG_T1_LOAD_LO_S 0
@@ -427,7 +427,7 @@
* time-base counter.
*/
-#define TIMG_T1_LOAD_HI 0xFFFFFFFF
+#define TIMG_T1_LOAD_HI 0xFFFFFFFF
#define TIMG_T1_LOAD_HI_M ((TIMG_T1_LOAD_HI_V)<<(TIMG_T1_LOAD_HI_S))
#define TIMG_T1_LOAD_HI_V 0xFFFFFFFF
#define TIMG_T1_LOAD_HI_S 0
@@ -440,7 +440,7 @@
* timer 1 time-base counter reload.
*/
-#define TIMG_T1_LOAD 0xFFFFFFFF
+#define TIMG_T1_LOAD 0xFFFFFFFF
#define TIMG_T1_LOAD_M ((TIMG_T1_LOAD_V)<<(TIMG_T1_LOAD_S))
#define TIMG_T1_LOAD_V 0xFFFFFFFF
#define TIMG_T1_LOAD_S 0
@@ -451,7 +451,7 @@
/* Description: When set SWDT is enabled. */
-#define TIMG_WDT_EN (BIT(31))
+#define TIMG_WDT_EN (BIT(31))
#define TIMG_WDT_EN_M (BIT(31))
#define TIMG_WDT_EN_V 0x1
#define TIMG_WDT_EN_S 31
@@ -462,7 +462,7 @@
* 0: off 1: interrupt 2: reset CPU 3: reset system
*/
-#define TIMG_WDT_STG0 0x00000003
+#define TIMG_WDT_STG0 0x00000003
#define TIMG_WDT_STG0_M ((TIMG_WDT_STG0_V)<<(TIMG_WDT_STG0_S))
#define TIMG_WDT_STG0_V 0x3
#define TIMG_WDT_STG0_S 29
diff --git a/arch/xtensa/src/esp32s2/esp32s2_efuse.h
b/arch/xtensa/src/esp32s2/esp32s2_efuse.h
index 2c927608ac..5c136a5198 100644
--- a/arch/xtensa/src/esp32s2/esp32s2_efuse.h
+++ b/arch/xtensa/src/esp32s2/esp32s2_efuse.h
@@ -46,37 +46,37 @@ extern "C"
typedef enum
{
- EFUSE_BLK0 = 0, /**< Number of eFuse BLOCK0. REPEAT_DATA
*/
+ EFUSE_BLK0 = 0, /* Number of eFuse BLOCK0. REPEAT_DATA */
- EFUSE_BLK1 = 1, /**< Number of eFuse BLOCK1.
MAC_SPI_8M_SYS */
+ EFUSE_BLK1 = 1, /* Number of eFuse BLOCK1.
MAC_SPI_8M_SYS */
- EFUSE_BLK2 = 2, /**< Number of eFuse BLOCK2.
SYS_DATA_PART1 */
- EFUSE_BLK_SYS_DATA_PART1 = 2, /**< Number of eFuse BLOCK2.
SYS_DATA_PART1 */
+ EFUSE_BLK2 = 2, /* Number of eFuse BLOCK2.
SYS_DATA_PART1 */
+ EFUSE_BLK_SYS_DATA_PART1 = 2, /* Number of eFuse BLOCK2.
SYS_DATA_PART1 */
- EFUSE_BLK3 = 3, /**< Number of eFuse BLOCK3. USER_DATA */
- EFUSE_BLK_USER_DATA = 3, /**< Number of eFuse BLOCK3. USER_DATA */
+ EFUSE_BLK3 = 3, /* Number of eFuse BLOCK3. USER_DATA */
+ EFUSE_BLK_USER_DATA = 3, /* Number of eFuse BLOCK3. USER_DATA */
- EFUSE_BLK4 = 4, /**< Number of eFuse BLOCK4. KEY0 */
- EFUSE_BLK_KEY0 = 4, /**< Number of eFuse BLOCK4. KEY0 */
+ EFUSE_BLK4 = 4, /* Number of eFuse BLOCK4. KEY0 */
+ EFUSE_BLK_KEY0 = 4, /* Number of eFuse BLOCK4. KEY0 */
- EFUSE_BLK5 = 5, /**< Number of eFuse BLOCK5. KEY1 */
- EFUSE_BLK_KEY1 = 5, /**< Number of eFuse BLOCK5. KEY1 */
+ EFUSE_BLK5 = 5, /* Number of eFuse BLOCK5. KEY1 */
+ EFUSE_BLK_KEY1 = 5, /* Number of eFuse BLOCK5. KEY1 */
- EFUSE_BLK6 = 6, /**< Number of eFuse BLOCK6. KEY2 */
- EFUSE_BLK_KEY2 = 6, /**< Number of eFuse BLOCK6. KEY2 */
+ EFUSE_BLK6 = 6, /* Number of eFuse BLOCK6. KEY2 */
+ EFUSE_BLK_KEY2 = 6, /* Number of eFuse BLOCK6. KEY2 */
- EFUSE_BLK7 = 7, /**< Number of eFuse BLOCK7. KEY3 */
- EFUSE_BLK_KEY3 = 7, /**< Number of eFuse BLOCK7. KEY3 */
+ EFUSE_BLK7 = 7, /* Number of eFuse BLOCK7. KEY3 */
+ EFUSE_BLK_KEY3 = 7, /* Number of eFuse BLOCK7. KEY3 */
- EFUSE_BLK8 = 8, /**< Number of eFuse BLOCK8. KEY4 */
- EFUSE_BLK_KEY4 = 8, /**< Number of eFuse BLOCK8. KEY4 */
+ EFUSE_BLK8 = 8, /* Number of eFuse BLOCK8. KEY4 */
+ EFUSE_BLK_KEY4 = 8, /* Number of eFuse BLOCK8. KEY4 */
- EFUSE_BLK9 = 9, /**< Number of eFuse BLOCK9. KEY5 */
- EFUSE_BLK_KEY5 = 9, /**< Number of eFuse BLOCK9. KEY5 */
+ EFUSE_BLK9 = 9, /* Number of eFuse BLOCK9. KEY5 */
+ EFUSE_BLK_KEY5 = 9, /* Number of eFuse BLOCK9. KEY5 */
EFUSE_BLK_KEY_MAX = 10,
- EFUSE_BLK10 = 10, /**< Number of eFuse BLOCK10.
SYS_DATA_PART2 */
- EFUSE_BLK_SYS_DATA_PART2 = 10, /**< Number of eFuse BLOCK10.
SYS_DATA_PART2 */
+ EFUSE_BLK10 = 10, /* Number of eFuse BLOCK10.
SYS_DATA_PART2 */
+ EFUSE_BLK_SYS_DATA_PART2 = 10, /* Number of eFuse BLOCK10.
SYS_DATA_PART2 */
EFUSE_BLK_MAX
} esp_efuse_block_t;
diff --git a/arch/xtensa/src/esp32s2/esp32s2_serial.c
b/arch/xtensa/src/esp32s2/esp32s2_serial.c
index 992d7a28b7..acabe8f9de 100644
--- a/arch/xtensa/src/esp32s2/esp32s2_serial.c
+++ b/arch/xtensa/src/esp32s2/esp32s2_serial.c
@@ -1058,7 +1058,7 @@ void xtensa_serialinit(void)
uart_register("/dev/ttyS0", &TTYS0_DEV);
-#ifdef TTYS1_DEV
+#ifdef TTYS1_DEV
uart_register("/dev/ttyS1", &TTYS1_DEV);
#endif
}
diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_gpio_sigmap.h
b/arch/xtensa/src/esp32s2/hardware/esp32s2_gpio_sigmap.h
index 95f4e671b3..0ffd4342e9 100644
--- a/arch/xtensa/src/esp32s2/hardware/esp32s2_gpio_sigmap.h
+++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_gpio_sigmap.h
@@ -323,5 +323,5 @@
#define PRO_ALONEGPIO_OUT7_IDX 242
#define CLK_I2S_MUX_IDX 251
#define SIG_GPIO_OUT_IDX 256
-#define GPIO_MAP_DATE_IDX 0x1904100
-#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_GPIO_SIGMAP_H */
+#define GPIO_MAP_DATE_IDX 0x1904100
+#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_GPIO_SIGMAP_H */
diff --git a/arch/xtensa/src/esp32s3/chip_macros.h
b/arch/xtensa/src/esp32s3/chip_macros.h
index cdba8246e2..658789489f 100644
--- a/arch/xtensa/src/esp32s3/chip_macros.h
+++ b/arch/xtensa/src/esp32s3/chip_macros.h
@@ -71,7 +71,7 @@
#ifdef __ASSEMBLY__
#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15
- .global g_cpu_intstack_top
+ .global g_cpu_intstack_top
#endif /* CONFIG_SMP && CONFIG_ARCH_INTERRUPTSTACK > 15 */
#endif /* __ASSEMBLY__ */
diff --git a/arch/xtensa/src/esp32s3/esp32s3_efuse.h
b/arch/xtensa/src/esp32s3/esp32s3_efuse.h
index 82bee52c86..ae3d0a81a0 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_efuse.h
+++ b/arch/xtensa/src/esp32s3/esp32s3_efuse.h
@@ -46,37 +46,37 @@ extern "C"
typedef enum
{
- EFUSE_BLK0 = 0, /**< Number of eFuse BLOCK0. REPEAT_DATA
*/
+ EFUSE_BLK0 = 0, /* Number of eFuse BLOCK0. REPEAT_DATA */
- EFUSE_BLK1 = 1, /**< Number of eFuse BLOCK1.
MAC_SPI_8M_SYS */
+ EFUSE_BLK1 = 1, /* Number of eFuse BLOCK1.
MAC_SPI_8M_SYS */
- EFUSE_BLK2 = 2, /**< Number of eFuse BLOCK2.
SYS_DATA_PART1 */
- EFUSE_BLK_SYS_DATA_PART1 = 2, /**< Number of eFuse BLOCK2.
SYS_DATA_PART1 */
+ EFUSE_BLK2 = 2, /* Number of eFuse BLOCK2.
SYS_DATA_PART1 */
+ EFUSE_BLK_SYS_DATA_PART1 = 2, /* Number of eFuse BLOCK2.
SYS_DATA_PART1 */
- EFUSE_BLK3 = 3, /**< Number of eFuse BLOCK3. USER_DATA */
- EFUSE_BLK_USER_DATA = 3, /**< Number of eFuse BLOCK3. USER_DATA */
+ EFUSE_BLK3 = 3, /* Number of eFuse BLOCK3. USER_DATA */
+ EFUSE_BLK_USER_DATA = 3, /* Number of eFuse BLOCK3. USER_DATA */
- EFUSE_BLK4 = 4, /**< Number of eFuse BLOCK4. KEY0 */
- EFUSE_BLK_KEY0 = 4, /**< Number of eFuse BLOCK4. KEY0 */
+ EFUSE_BLK4 = 4, /* Number of eFuse BLOCK4. KEY0 */
+ EFUSE_BLK_KEY0 = 4, /* Number of eFuse BLOCK4. KEY0 */
- EFUSE_BLK5 = 5, /**< Number of eFuse BLOCK5. KEY1 */
- EFUSE_BLK_KEY1 = 5, /**< Number of eFuse BLOCK5. KEY1 */
+ EFUSE_BLK5 = 5, /* Number of eFuse BLOCK5. KEY1 */
+ EFUSE_BLK_KEY1 = 5, /* Number of eFuse BLOCK5. KEY1 */
- EFUSE_BLK6 = 6, /**< Number of eFuse BLOCK6. KEY2 */
- EFUSE_BLK_KEY2 = 6, /**< Number of eFuse BLOCK6. KEY2 */
+ EFUSE_BLK6 = 6, /* Number of eFuse BLOCK6. KEY2 */
+ EFUSE_BLK_KEY2 = 6, /* Number of eFuse BLOCK6. KEY2 */
- EFUSE_BLK7 = 7, /**< Number of eFuse BLOCK7. KEY3 */
- EFUSE_BLK_KEY3 = 7, /**< Number of eFuse BLOCK7. KEY3 */
+ EFUSE_BLK7 = 7, /* Number of eFuse BLOCK7. KEY3 */
+ EFUSE_BLK_KEY3 = 7, /* Number of eFuse BLOCK7. KEY3 */
- EFUSE_BLK8 = 8, /**< Number of eFuse BLOCK8. KEY4 */
- EFUSE_BLK_KEY4 = 8, /**< Number of eFuse BLOCK8. KEY4 */
+ EFUSE_BLK8 = 8, /* Number of eFuse BLOCK8. KEY4 */
+ EFUSE_BLK_KEY4 = 8, /* Number of eFuse BLOCK8. KEY4 */
- EFUSE_BLK9 = 9, /**< Number of eFuse BLOCK9. KEY5 */
- EFUSE_BLK_KEY5 = 9, /**< Number of eFuse BLOCK9. KEY5 */
+ EFUSE_BLK9 = 9, /* Number of eFuse BLOCK9. KEY5 */
+ EFUSE_BLK_KEY5 = 9, /* Number of eFuse BLOCK9. KEY5 */
EFUSE_BLK_KEY_MAX = 10,
- EFUSE_BLK10 = 10, /**< Number of eFuse BLOCK10.
SYS_DATA_PART2 */
- EFUSE_BLK_SYS_DATA_PART2 = 10, /**< Number of eFuse BLOCK10.
SYS_DATA_PART2 */
+ EFUSE_BLK10 = 10, /* Number of eFuse BLOCK10.
SYS_DATA_PART2 */
+ EFUSE_BLK_SYS_DATA_PART2 = 10, /* Number of eFuse BLOCK10.
SYS_DATA_PART2 */
EFUSE_BLK_MAX
} esp_efuse_block_t;
diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_soc.h
b/arch/xtensa/src/esp32s3/hardware/esp32s3_soc.h
index 12a4d043bd..a74513e4bf 100644
--- a/arch/xtensa/src/esp32s3/hardware/esp32s3_soc.h
+++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_soc.h
@@ -448,7 +448,7 @@
#define ETS_WMAC_INUM 0
#define ETS_BT_HOST_INUM 1
#define ETS_WBB_INUM 4
-#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/
+#define ETS_TG0_T1_INUM 10 /* use edge interrupt*/
#define ETS_FRC1_INUM 22
#define ETS_T1_WDT_INUM 24
#define ETS_CACHEERR_INUM 25
diff --git a/boards/arm/cxd56xx/drivers/sensors/bmi160_scu.c
b/boards/arm/cxd56xx/drivers/sensors/bmi160_scu.c
index 8c8bce9aae..39925cb622 100644
--- a/boards/arm/cxd56xx/drivers/sensors/bmi160_scu.c
+++ b/boards/arm/cxd56xx/drivers/sensors/bmi160_scu.c
@@ -205,9 +205,9 @@
/* Register 0x7e - CMD */
-#define ACCEL_PM_SUSPEND (0X10)
+#define ACCEL_PM_SUSPEND (0X10)
#define ACCEL_PM_NORMAL (0x11)
-#define ACCEL_PM_LOWPOWER (0X12)
+#define ACCEL_PM_LOWPOWER (0X12)
#define GYRO_PM_SUSPEND (0x14)
#define GYRO_PM_NORMAL (0x15)
#define GYRO_PM_FASTSTARTUP (0x17)
diff --git a/boards/arm/cxd56xx/spresense/include/cxd56_gpioif.h
b/boards/arm/cxd56xx/spresense/include/cxd56_gpioif.h
index 818652d0a8..021d82e3c3 100644
--- a/boards/arm/cxd56xx/spresense/include/cxd56_gpioif.h
+++ b/boards/arm/cxd56xx/spresense/include/cxd56_gpioif.h
@@ -51,20 +51,20 @@ extern "C"
* Pin floating, pull up, pull down definitions
*/
-#define PIN_FLOAT (0) /**< Floating */
-#define PIN_PULLUP (1) /**< Internal Weak Pull Up */
-#define PIN_PULLDOWN (2) /**< Internal Weak Pull Down */
-#define PIN_BUSKEEPER (3) /**< Internal Bus-Keeper */
+#define PIN_FLOAT (0) /* Floating */
+#define PIN_PULLUP (1) /* Internal Weak Pull Up */
+#define PIN_PULLDOWN (2) /* Internal Weak Pull Down */
+#define PIN_BUSKEEPER (3) /* Internal Bus-Keeper */
/* GPIO Interrupt Setting
* GPIO interrupt level and edge trigger types
*/
-#define INT_HIGH_LEVEL (2) /**< High Level */
-#define INT_LOW_LEVEL (3) /**< Low Level */
-#define INT_RISING_EDGE (4) /**< Rising Edge */
-#define INT_FALLING_EDGE (5) /**< Falling Edge */
-#define INT_BOTH_EDGE (7) /**< Both Edge */
+#define INT_HIGH_LEVEL (2) /* High Level */
+#define INT_LOW_LEVEL (3) /* Low Level */
+#define INT_RISING_EDGE (4) /* Rising Edge */
+#define INT_FALLING_EDGE (5) /* Falling Edge */
+#define INT_BOTH_EDGE (7) /* Both Edge */
#ifndef __ASSEMBLY__
diff --git a/boards/arm/imxrt/imxrt1020-evk/src/imxrt1020-evk.h
b/boards/arm/imxrt/imxrt1020-evk/src/imxrt1020-evk.h
index 44e986ddf7..27f2a8de15 100644
--- a/boards/arm/imxrt/imxrt1020-evk/src/imxrt1020-evk.h
+++ b/boards/arm/imxrt/imxrt1020-evk/src/imxrt1020-evk.h
@@ -70,7 +70,7 @@
/* ETH Disambiguation *******************************************************/
#define GPIO_ENET_INT (IOMUX_ENET_INT_DEFAULT | GPIO_INTERRUPT | \
- GPIO_INT_FALLINGEDGE | GPIO_PORT1 |
GPIO_PIN22) /* AD_B1_06 */
+ GPIO_INT_FALLINGEDGE | GPIO_PORT1 | GPIO_PIN22) /*
AD_B1_06 */
#define GPIO_ENET_IRQ IMXRT_IRQ_GPIO1_12
#define GPIO_ENET_RST (GPIO_OUTPUT | IOMUX_ENET_RST_DEFAULT | \
GPIO_OUTPUT_ZERO | GPIO_PORT1 | GPIO_PIN4 ) /*
AD_B0_04, Inverted logic */
diff --git a/boards/arm/lpc43xx/lpc4337-ws/include/board.h
b/boards/arm/lpc43xx/lpc4337-ws/include/board.h
index ab249e3226..952dce9ac0 100644
--- a/boards/arm/lpc43xx/lpc4337-ws/include/board.h
+++ b/boards/arm/lpc43xx/lpc4337-ws/include/board.h
@@ -188,23 +188,23 @@
#endif
#if CONFIG_SPIFI_LIBRARY
-# define SPIFI_DEVICE_ALL 0 /**< Enables all devices in
family */
-# define SPIFI_DEVICE_S25FL016K 0 /**< Enables Spansion
S25FL016K device */
-# define SPIFI_DEVICE_S25FL032P 0 /**< Enables Spansion
S25FL032P device */
-# define SPIFI_DEVICE_S25FL064P 0 /**< Enables Spansion
S25FL064P device */
-# define SPIFI_DEVICE_S25FL129P_64K 0 /**< Enables Spansion
S25FL129P (64K block) device */
-# define SPIFI_DEVICE_S25FL129P_256K 0 /**< Enables Spansion
S25FL129P (256K block) device */
-# define SPIFI_DEVICE_S25FL164K 0 /**< Enables Spansion
S25FL164K device */
-# define SPIFI_DEVICE_S25FL256S_64K 0 /**< Enables Spansion
S25FL256S (64K block) device */
-# define SPIFI_DEVICE_S25FL256S_256K 0 /**< Enables Spansion
S25FL256S (256K block) device */
-# define SPIFI_DEVICE_S25FL512S 0 /**< Enables Spansion
S25FL512S device */
-# define SPIFI_DEVICE_MX25L1635E 0 /**< Enables Macronix
MX25L1635E device */
-# define SPIFI_DEVICE_MX25L3235E 0 /**< Enables Macronix
MX25L3235E device */
-# define SPIFI_DEVICE_MX25L8035E 0 /**< Enables Macronix
MX25L8035E device */
-# define SPIFI_DEVICE_MX25L6435E 0 /**< Enables Macronix
MX25L6435E device */
-# define SPIFI_DEVICE_W25Q32FV 0 /**< Enables Winbond
W25Q32FV device */
-# define SPIFI_DEVICE_W25Q64FV 0 /**< Enables Winbond
W25Q32V device */
-# define SPIFI_DEVICE_W25Q80BV 1 /**< Enables Winbond
W25Q80BV device */
+# define SPIFI_DEVICE_ALL 0 /* Enables all devices in
family */
+# define SPIFI_DEVICE_S25FL016K 0 /* Enables Spansion
S25FL016K device */
+# define SPIFI_DEVICE_S25FL032P 0 /* Enables Spansion
S25FL032P device */
+# define SPIFI_DEVICE_S25FL064P 0 /* Enables Spansion
S25FL064P device */
+# define SPIFI_DEVICE_S25FL129P_64K 0 /* Enables Spansion
S25FL129P (64K block) device */
+# define SPIFI_DEVICE_S25FL129P_256K 0 /* Enables Spansion
S25FL129P (256K block) device */
+# define SPIFI_DEVICE_S25FL164K 0 /* Enables Spansion
S25FL164K device */
+# define SPIFI_DEVICE_S25FL256S_64K 0 /* Enables Spansion
S25FL256S (64K block) device */
+# define SPIFI_DEVICE_S25FL256S_256K 0 /* Enables Spansion
S25FL256S (256K block) device */
+# define SPIFI_DEVICE_S25FL512S 0 /* Enables Spansion
S25FL512S device */
+# define SPIFI_DEVICE_MX25L1635E 0 /* Enables Macronix
MX25L1635E device */
+# define SPIFI_DEVICE_MX25L3235E 0 /* Enables Macronix
MX25L3235E device */
+# define SPIFI_DEVICE_MX25L8035E 0 /* Enables Macronix
MX25L8035E device */
+# define SPIFI_DEVICE_MX25L6435E 0 /* Enables Macronix
MX25L6435E device */
+# define SPIFI_DEVICE_W25Q32FV 0 /* Enables Winbond W25Q32FV
device */
+# define SPIFI_DEVICE_W25Q64FV 0 /* Enables Winbond W25Q32V
device */
+# define SPIFI_DEVICE_W25Q80BV 1 /* Enables Winbond W25Q80BV
device */
# define SPIFI_DEVICE_REQUENCY_DIVIDER 2 /* PLL1 clock divider */
#endif
diff --git a/boards/arm/lpc43xx/lpc4370-link2/include/board.h
b/boards/arm/lpc43xx/lpc4370-link2/include/board.h
index 856158a232..6882ca60d8 100644
--- a/boards/arm/lpc43xx/lpc4370-link2/include/board.h
+++ b/boards/arm/lpc43xx/lpc4370-link2/include/board.h
@@ -183,23 +183,23 @@
#endif
#if CONFIG_SPIFI_LIBRARY
-# define SPIFI_DEVICE_ALL 0 /**< Enables all devices in
family */
-# define SPIFI_DEVICE_S25FL016K 0 /**< Enables Spansion
S25FL016K device */
-# define SPIFI_DEVICE_S25FL032P 0 /**< Enables Spansion
S25FL032P device */
-# define SPIFI_DEVICE_S25FL064P 0 /**< Enables Spansion
S25FL064P device */
-# define SPIFI_DEVICE_S25FL129P_64K 0 /**< Enables Spansion
S25FL129P (64K block) device */
-# define SPIFI_DEVICE_S25FL129P_256K 0 /**< Enables Spansion
S25FL129P (256K block) device */
-# define SPIFI_DEVICE_S25FL164K 0 /**< Enables Spansion
S25FL164K device */
-# define SPIFI_DEVICE_S25FL256S_64K 0 /**< Enables Spansion
S25FL256S (64K block) device */
-# define SPIFI_DEVICE_S25FL256S_256K 0 /**< Enables Spansion
S25FL256S (256K block) device */
-# define SPIFI_DEVICE_S25FL512S 0 /**< Enables Spansion
S25FL512S device */
-# define SPIFI_DEVICE_MX25L1635E 0 /**< Enables Macronix
MX25L1635E device */
-# define SPIFI_DEVICE_MX25L3235E 0 /**< Enables Macronix
MX25L3235E device */
-# define SPIFI_DEVICE_MX25L8035E 0 /**< Enables Macronix
MX25L8035E device */
-# define SPIFI_DEVICE_MX25L6435E 0 /**< Enables Macronix
MX25L6435E device */
-# define SPIFI_DEVICE_W25Q32FV 0 /**< Enables Winbond
W25Q32FV device */
-# define SPIFI_DEVICE_W25Q64FV 0 /**< Enables Winbond
W25Q32V device */
-# define SPIFI_DEVICE_W25Q80BV 1 /**< Enables Winbond
W25Q80BV device */
+# define SPIFI_DEVICE_ALL 0 /* Enables all devices in
family */
+# define SPIFI_DEVICE_S25FL016K 0 /* Enables Spansion
S25FL016K device */
+# define SPIFI_DEVICE_S25FL032P 0 /* Enables Spansion
S25FL032P device */
+# define SPIFI_DEVICE_S25FL064P 0 /* Enables Spansion
S25FL064P device */
+# define SPIFI_DEVICE_S25FL129P_64K 0 /* Enables Spansion
S25FL129P (64K block) device */
+# define SPIFI_DEVICE_S25FL129P_256K 0 /* Enables Spansion
S25FL129P (256K block) device */
+# define SPIFI_DEVICE_S25FL164K 0 /* Enables Spansion
S25FL164K device */
+# define SPIFI_DEVICE_S25FL256S_64K 0 /* Enables Spansion
S25FL256S (64K block) device */
+# define SPIFI_DEVICE_S25FL256S_256K 0 /* Enables Spansion
S25FL256S (256K block) device */
+# define SPIFI_DEVICE_S25FL512S 0 /* Enables Spansion
S25FL512S device */
+# define SPIFI_DEVICE_MX25L1635E 0 /* Enables Macronix
MX25L1635E device */
+# define SPIFI_DEVICE_MX25L3235E 0 /* Enables Macronix
MX25L3235E device */
+# define SPIFI_DEVICE_MX25L8035E 0 /* Enables Macronix
MX25L8035E device */
+# define SPIFI_DEVICE_MX25L6435E 0 /* Enables Macronix
MX25L6435E device */
+# define SPIFI_DEVICE_W25Q32FV 0 /* Enables Winbond W25Q32FV
device */
+# define SPIFI_DEVICE_W25Q64FV 0 /* Enables Winbond W25Q32V
device */
+# define SPIFI_DEVICE_W25Q80BV 1 /* Enables Winbond W25Q80BV
device */
# define SPIFI_DEVICE_REQUENCY_DIVIDER 2 /* PLL1 clock divider */
#endif
diff --git a/boards/arm/samd5e5/metro-m4/include/board.h
b/boards/arm/samd5e5/metro-m4/include/board.h
index a239c9a860..3c4d700dec 100644
--- a/boards/arm/samd5e5/metro-m4/include/board.h
+++ b/boards/arm/samd5e5/metro-m4/include/board.h
@@ -453,8 +453,8 @@
#define BOARD_SERCOM5_PINMAP_PAD2 0 /* PAD2: (not used) */
#define BOARD_SERCOM5_PINMAP_PAD3 0 /* PAD3: (not used) */
-#define BOARD_SERCOM5_GCLKGEN 1 /* 48MHz Core
clock */
-#define BOARD_SERCOM5_SLOW_GCLKGEN 3
+#define BOARD_SERCOM5_GCLKGEN 1 /* 48MHz Core clock */
+#define BOARD_SERCOM5_SLOW_GCLKGEN 3
#define BOARD_SERCOM5_FREQUENCY BOARD_GCLK1_FREQUENCY
/* Tickless */
diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/stm32h745i_disco.h
b/boards/arm/stm32h7/stm32h745i-disco/src/stm32h745i_disco.h
index 819e1cb750..4f0c618dc1 100644
--- a/boards/arm/stm32h7/stm32h745i-disco/src/stm32h745i_disco.h
+++ b/boards/arm/stm32h7/stm32h745i-disco/src/stm32h745i_disco.h
@@ -82,9 +82,9 @@
#define GPIO_LD3 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \
GPIO_OUTPUT_CLEAR | GPIO_PORTD | GPIO_PIN3)
-#define GPIO_LED_GREEN GPIO_LD1
-#define GPIO_LED_ORANGE GPIO_LD2
-#define GPIO_LED_RED GPIO_LD3
+#define GPIO_LED_GREEN GPIO_LD1
+#define GPIO_LED_ORANGE GPIO_LD2
+#define GPIO_LED_RED GPIO_LD3
#define GPIO_OTGFS_VBUS (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \
GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9)
diff --git a/drivers/modem/alt1250/altcom_pkt.h
b/drivers/modem/alt1250/altcom_pkt.h
index 3894be9ffd..d486818d66 100644
--- a/drivers/modem/alt1250/altcom_pkt.h
+++ b/drivers/modem/alt1250/altcom_pkt.h
@@ -51,9 +51,9 @@
#define ALTCOM_RX_PKT_SIZE_MAX (ALTCOM_PAYLOAD_SIZE_MAX_V4 \
+ sizeof(struct altcom_cmdhdr_s))
-#define LTE_RESULT_OK (0) /**< Result code on success */
-#define LTE_RESULT_ERROR (1) /**< Result code on failure */
-#define LTE_RESULT_CANCEL (2) /**< Result code on cancel */
+#define LTE_RESULT_OK (0) /* Result code on success */
+#define LTE_RESULT_ERROR (1) /* Result code on failure */
+#define LTE_RESULT_CANCEL (2) /* Result code on cancel */
#define ALTCOM_CMD_POWER_ON_REPLY_SIZE (1)
diff --git a/drivers/sensors/bmi270.c b/drivers/sensors/bmi270.c
index f852b9b254..42aab04da6 100644
--- a/drivers/sensors/bmi270.c
+++ b/drivers/sensors/bmi270.c
@@ -197,7 +197,7 @@
/* Register 0x7e - CMD */
-#define CMD_SOFTRESET (0xB6)
+#define CMD_SOFTRESET (0xB6)
/****************************************************************************
* Private Types
