mlaz commented on a change in pull request #1102: Feature/stm32 pwm enabled
URL: https://github.com/apache/mynewt-core/pull/1102#discussion_r188980929
 
 

 ##########
 File path: hw/drivers/pwm/pwm_stm32/src/pwm_stm32.c
 ##########
 @@ -0,0 +1,626 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#include "pwm_stm32/pwm_stm32.h"
+
+#include <bsp.h>
+#include <hal/hal_bsp.h>
+#include <mcu/cmsis_nvic.h>
+#include <os/os.h>
+#include <pwm/pwm.h>
+#include <stm32_common/stm32_hal.h>
+
+#include <assert.h>
+#include <stdint.h>
+#include <string.h>
+
+#define STM32_PWM_CH_MAX          4
+#define STM32_PWM_CH_IDLE         0x0000
+#define STM32_PWM_CH_MODE_ENA     LL_TIM_OCMODE_PWM2
+#define STM32_PWM_CH_MODE_DIS     LL_TIM_OCMODE_ACTIVE
+
+
+typedef struct {
+    uint32_t           n_cycles;
+    user_handler_t     cycle_handler;
+    user_handler_t     seq_end_handler;
+    void              *cycle_data;
+    void              *seq_end_data;
+} stm32_pwm_dev_cfg_t;
+
+typedef struct {
+    TIM_TypeDef         *timx;
+    uint32_t             cycle;
+    uint16_t             pin[STM32_PWM_CH_MAX];
+    uint16_t             irq;
+    stm32_pwm_dev_cfg_t  cfg;
+} stm32_pwm_dev_t;
+
+static stm32_pwm_dev_t stm32_pwm_dev[PWM_CNT];
+
+static inline bool
+stm32_pwm_ch_is_active(const stm32_pwm_dev_t *pwm, int ch)
+{
+    return MCU_AFIO_PIN_NONE != pwm->pin[ch];
+}
+
+static uint32_t
+stm32_pwm_ch(int ch)
+{
+    switch (ch) {
+        case 0: return LL_TIM_CHANNEL_CH1;
+        case 1: return LL_TIM_CHANNEL_CH2;
+        case 2: return LL_TIM_CHANNEL_CH3;
+        case 3: return LL_TIM_CHANNEL_CH4;
+    }
+    assert(0);
+    return 0;
+}
+
+static void
+stm32_pwm_active_ch_set_mode(stm32_pwm_dev_t *pwm, uint32_t mode) {
+    for (int i=0; i < STM32_PWM_CH_MAX; ++i) {
+        if (stm32_pwm_ch_is_active(pwm, i)) {
+            LL_TIM_OC_SetMode(pwm->timx, stm32_pwm_ch(i), mode);
+        }
+    }
+}
+
+static void
+stm32_pwm_ch_set_compare(TIM_TypeDef *tim, int ch, uint32_t value)
+{
+    switch (ch) {
+        case 0:
+            LL_TIM_OC_SetCompareCH1(tim, value);
+            break;
+        case 1:
+            LL_TIM_OC_SetCompareCH2(tim, value);
+            break;
+        case 2:
+            LL_TIM_OC_SetCompareCH3(tim, value);
+            break;
+        case 3:
+            LL_TIM_OC_SetCompareCH4(tim, value);
+            break;
+    }
+}
+
+static void
+stm32_pwm_ch_unconfigure(const stm32_pwm_dev_t *pwm, uint32_t id)
+{
+    uint32_t ch = stm32_pwm_ch(id);
+
+    LL_TIM_CC_DisableChannel(pwm->timx, ch);
+    LL_TIM_OC_SetMode(pwm->timx, ch, 0);
+    LL_TIM_OC_SetPolarity(pwm->timx, ch, 0);
+    LL_TIM_OC_DisablePreload(pwm->timx,  ch);
+}
+
+static void
+stm32_pwm_isr(stm32_pwm_dev_t *pwm)
+{
+    uint32_t sr = pwm->timx->SR;
+    pwm->timx->SR = ~sr;
+
+    if (pwm->cfg.cycle_handler) {
+        pwm->cfg.cycle_handler(pwm->cfg.cycle_data);
+    }
+
+    if (pwm->cfg.n_cycles) {
+        if (!pwm->cycle) {
+
+            LL_TIM_DisableCounter(pwm->timx);
+            LL_TIM_SetCounter(pwm->timx, 0);
+
+            if (pwm->cfg.seq_end_handler) {
+                pwm->cfg.seq_end_handler(pwm->cfg.seq_end_data);
+            }
+        } else {
+            if (1 == pwm->cycle) {
+                /* prep output pins for shutdown */
+                stm32_pwm_active_ch_set_mode(pwm, STM32_PWM_CH_MODE_DIS);
+            }
+            --pwm->cycle;
+        }
+    }
+}
+
+static void
+stm32_pwm_isr_0(void)
+{
+    stm32_pwm_isr(&stm32_pwm_dev[0]);
+}
+
+static void
+stm32_pwm_isr_1(void)
+{
+    stm32_pwm_isr(&stm32_pwm_dev[1]);
+}
+
+static void
+stm32_pwm_isr_2(void)
+{
+    stm32_pwm_isr(&stm32_pwm_dev[2]);
+}
+
+static int
+stm32_pwm_enable(struct pwm_dev *dev)
+{
+    stm32_pwm_dev_t *pwm;
+
+    assert(dev);
 
 Review comment:
   I think this is verified in 
[pwm.c](https://github.com/apache/mynewt-core/blob/59e9cd2e3cdfb867a69f6d2122997eb8768b4ec6/hw/drivers/pwm/src/pwm.c#L37)
 

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