This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit 3483c77d359a8e08a0734e6845cd55a7a773ecf2
Author: Jerzy Kasenberg <jerzy.kasenb...@codecoup.pl>
AuthorDate: Wed Feb 7 11:14:46 2024 +0100
bsp/nucleo-h723zg: Use common startup and linker script
This removes local startup code and linker scripts
Signed-off-by: Jerzy Kasenberg <jerzy.kasenb...@codecoup.pl>
---
.rat-excludes | 1 -
LICENSE | 1 -
hw/bsp/nucleo-h723zg/boot-nucleo-h723zg.ld | 32 -
hw/bsp/nucleo-h723zg/bsp.yml | 7 +-
hw/bsp/nucleo-h723zg/nucleo-h723zg.ld | 34 -
.../src/arch/cortex_m7/startup_stm32h723xx.s | 773 ---------------------
6 files changed, 1 insertion(+), 847 deletions(-)
diff --git a/.rat-excludes b/.rat-excludes
index 41315f80f..ce3f98ca0 100644
--- a/.rat-excludes
+++ b/.rat-excludes
@@ -265,7 +265,6 @@ startup_stm32l152xc.s
# NUCLEO-H723ZG BSP - BSD License
stm32h7xx_hal_conf.h
system_stm32h7xx.c
-startup_stm32h723xx.s
# STM32U5 - BSD License
system_stm32u5xx.c
diff --git a/LICENSE b/LICENSE
index 6356c49d7..3a3706971 100644
--- a/LICENSE
+++ b/LICENSE
@@ -330,7 +330,6 @@ This product bundles parts of STM32CubeH7, which is
available under the
* hw/mcu/stm/stm32h7xx/src/clock_stm32h7xx.c
* hw/mcu/stm/stm32h7xx/src/system_stm32h7xx.c
* hw/bsp/nucleo-h723zg/include/bsp/stm32h7xx_hal_conf.h
- * hw/bsp/nucleo-h723zg/src/arch/cortex_m7/startup_stm32h723xx.s
This product bundles parts of stm32l1xx, which is available under the
"3-clause BSD" license. Bundled files are:
diff --git a/hw/bsp/nucleo-h723zg/boot-nucleo-h723zg.ld
b/hw/bsp/nucleo-h723zg/boot-nucleo-h723zg.ld
deleted file mode 100644
index 557c23972..000000000
--- a/hw/bsp/nucleo-h723zg/boot-nucleo-h723zg.ld
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-/* Linker script to configure memory regions. */
-MEMORY
-{
- ITCM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K
- DTCM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
- FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K /* Bootloader area */
- RAM (xrw) : ORIGIN = 0x24000000, LENGTH = 320K /* AXI (128) +
AXI/ITCM (192) */
- RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 32K /* SRAM1 + SRMA2 */
- RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 16K /* SRAM4 */
-}
-
-/* The bootloader does not contain an image header */
-_imghdr_size = 0x0;
diff --git a/hw/bsp/nucleo-h723zg/bsp.yml b/hw/bsp/nucleo-h723zg/bsp.yml
index f96f05bce..afdc6f194 100644
--- a/hw/bsp/nucleo-h723zg/bsp.yml
+++ b/hw/bsp/nucleo-h723zg/bsp.yml
@@ -22,12 +22,7 @@ bsp.url:
https://www.st.com/en/evaluation-tools/nucleo-h723zg.html
bsp.maker: "STMicroelectronics"
bsp.arch: cortex_m7
bsp.compiler: compiler/arm-none-eabi-m7
-bsp.linkerscript:
- - "hw/bsp/nucleo-h723zg/nucleo-h723zg.ld"
- - "@apache-mynewt-core/hw/mcu/stm/stm32h7xx/stm32h723.ld"
-bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- - "hw/bsp/nucleo-h723zg/boot-nucleo-h723zg.ld"
- - "@apache-mynewt-core/hw/mcu/stm/stm32h7xx/stm32h723.ld"
+bsp.linkerscript: autogenerated
bsp.downloadscript: "hw/scripts/download.sh"
bsp.debugscript: "hw/bsp/nucleo-h723zg/nucleo-h723zg_debug.sh"
diff --git a/hw/bsp/nucleo-h723zg/nucleo-h723zg.ld
b/hw/bsp/nucleo-h723zg/nucleo-h723zg.ld
deleted file mode 100644
index 81045cbd4..000000000
--- a/hw/bsp/nucleo-h723zg/nucleo-h723zg.ld
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-/* Linker script for STM32H723 when running from flash and using the
bootloader */
-
-/* Linker script to configure memory regions. */
-MEMORY
-{
- ITCM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K
- DTCM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
- FLASH (rx) : ORIGIN = 0x08020000, LENGTH = 384K /* Image slot 1 */
- RAM (xrw) : ORIGIN = 0x24000000, LENGTH = 320K /* AXI (128) +
AXI/ITCM (192) */
- RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 32K /* SRAM1 + SRMA2 */
- RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 16K /* SRAM4 */
-}
-
-/* This linker script is used for images and thus contains an image header */
-_imghdr_size = 0x20;
diff --git a/hw/bsp/nucleo-h723zg/src/arch/cortex_m7/startup_stm32h723xx.s
b/hw/bsp/nucleo-h723zg/src/arch/cortex_m7/startup_stm32h723xx.s
deleted file mode 100644
index b61a57358..000000000
--- a/hw/bsp/nucleo-h723zg/src/arch/cortex_m7/startup_stm32h723xx.s
+++ /dev/null
@@ -1,773 +0,0 @@
-/**
-
******************************************************************************
- * @file startup_stm32h723xx.s
- * @author MCD Application Team
- * @brief STM32H723xx Devices vector table for GCC based toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR
address
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
-
******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
-
******************************************************************************
- */
-
- .syntax unified
- .cpu cortex-m7
- .fpu softvfp
- .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
-
-/**
- * @brief This is the code that gets called when the processor first
- * starts execution following a reset event. Only the absolutely
- * necessary set is performed, after which the application
- * supplied main() routine is called.
- * @param None
- * @retval : None
-*/
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr sp, =_estack /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
-LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
-
- ldr r2, =_sbss
- b LoopFillZerobss
-
-/* Zero fill the bss segment. */
-FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
-LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
-
-/*
- * mynewt specific corebss clearing.
- */
- ldr r2, =__corebss_start__
- b LoopFillZeroCoreBss
-
-/* Zero fill the bss segment. */
-FillZeroCoreBss:
- movs r3, #0
- str r3, [r2], #4
-
-LoopFillZeroCoreBss:
- ldr r3, =__corebss_end__
- cmp r2, r3
- bcc FillZeroCoreBss
-
- ldr r0, =__HeapBase
- ldr r1, =__HeapLimit
- bl _sbrkInit
-
-/* Call the clock system initialization function.*/
- bl SystemInit
-/* Call the libc entry point.*/
- bl _start
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop,
preserving
- * the system state for examination by a debugger.
- * @param None
- * @retval None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-*******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-g_pfnVectors:
- .globl __isr_vector
-__isr_vector:
- .word _estack
- .word Reset_Handler
-
- .word NMI_Handler
- .word HardFault_Handler
- .word MemManage_Handler
- .word BusFault_Handler
- .word UsageFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word DebugMon_Handler
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
-
- /* External Interrupts */
- .word WWDG_IRQHandler /* Window WatchDog
*/
- .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line
detection */
- .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through
the EXTI line */
- .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI
line */
- .word FLASH_IRQHandler /* FLASH
*/
- .word RCC_IRQHandler /* RCC
*/
- .word EXTI0_IRQHandler /* EXTI Line0
*/
- .word EXTI1_IRQHandler /* EXTI Line1
*/
- .word EXTI2_IRQHandler /* EXTI Line2
*/
- .word EXTI3_IRQHandler /* EXTI Line3
*/
- .word EXTI4_IRQHandler /* EXTI Line4
*/
- .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0
*/
- .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1
*/
- .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2
*/
- .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3
*/
- .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4
*/
- .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5
*/
- .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6
*/
- .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s
*/
- .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0
*/
- .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0
*/
- .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1
*/
- .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1
*/
- .word EXTI9_5_IRQHandler /* External Line[9:5]s
*/
- .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt
*/
- .word TIM1_UP_IRQHandler /* TIM1 Update interrupt
*/
- .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation
interrupt */
- .word TIM1_CC_IRQHandler /* TIM1 Capture Compare
*/
- .word TIM2_IRQHandler /* TIM2
*/
- .word TIM3_IRQHandler /* TIM3
*/
- .word TIM4_IRQHandler /* TIM4
*/
- .word I2C1_EV_IRQHandler /* I2C1 Event
*/
- .word I2C1_ER_IRQHandler /* I2C1 Error
*/
- .word I2C2_EV_IRQHandler /* I2C2 Event
*/
- .word I2C2_ER_IRQHandler /* I2C2 Error
*/
- .word SPI1_IRQHandler /* SPI1
*/
- .word SPI2_IRQHandler /* SPI2
*/
- .word USART1_IRQHandler /* USART1
*/
- .word USART2_IRQHandler /* USART2
*/
- .word USART3_IRQHandler /* USART3
*/
- .word EXTI15_10_IRQHandler /* External Line[15:10]s
*/
- .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through
EXTI Line */
- .word 0 /* Reserved
*/
- .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12
*/
- .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13
*/
- .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation
and TIM14 */
- .word TIM8_CC_IRQHandler /* TIM8 Capture Compare
*/
- .word DMA1_Stream7_IRQHandler /* DMA1 Stream7
*/
- .word FMC_IRQHandler /* FMC
*/
- .word SDMMC1_IRQHandler /* SDMMC1
*/
- .word TIM5_IRQHandler /* TIM5
*/
- .word SPI3_IRQHandler /* SPI3
*/
- .word UART4_IRQHandler /* UART4
*/
- .word UART5_IRQHandler /* UART5
*/
- .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun
errors */
- .word TIM7_IRQHandler /* TIM7
*/
- .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0
*/
- .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1
*/
- .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2
*/
- .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3
*/
- .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4
*/
- .word ETH_IRQHandler /* Ethernet
*/
- .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI
line */
- .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit
interrupt*/
- .word 0 /* Reserved
*/
- .word 0 /* Reserved
*/
- .word 0 /* Reserved
*/
- .word 0 /* Reserved
*/
- .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5
*/
- .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6
*/
- .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7
*/
- .word USART6_IRQHandler /* USART6
*/
- .word I2C3_EV_IRQHandler /* I2C3 event
*/
- .word I2C3_ER_IRQHandler /* I2C3 error
*/
- .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out
*/
- .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In
*/
- .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through
EXTI */
- .word OTG_HS_IRQHandler /* USB OTG HS
*/
- .word DCMI_PSSI_IRQHandler /* DCMI, PSSI
*/
- .word 0 /* Reserved
*/
- .word RNG_IRQHandler /* Rng
*/
- .word FPU_IRQHandler /* FPU
*/
- .word UART7_IRQHandler /* UART7
*/
- .word UART8_IRQHandler /* UART8
*/
- .word SPI4_IRQHandler /* SPI4
*/
- .word SPI5_IRQHandler /* SPI5
*/
- .word SPI6_IRQHandler /* SPI6
*/
- .word SAI1_IRQHandler /* SAI1
*/
- .word LTDC_IRQHandler /* LTDC
*/
- .word LTDC_ER_IRQHandler /* LTDC error
*/
- .word DMA2D_IRQHandler /* DMA2D
*/
- .word 0 /* Reserved
*/
- .word OCTOSPI1_IRQHandler /* OCTOSPI1
*/
- .word LPTIM1_IRQHandler /* LPTIM1
*/
- .word CEC_IRQHandler /* HDMI_CEC
*/
- .word I2C4_EV_IRQHandler /* I2C4 Event
*/
- .word I2C4_ER_IRQHandler /* I2C4 Error
*/
- .word SPDIF_RX_IRQHandler /* SPDIF_RX
*/
- .word 0 /* Reserved
*/
- .word 0 /* Reserved
*/
- .word 0 /* Reserved
*/
- .word 0 /* Reserved
*/
- .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt
*/
- .word 0 /* Reserved
*/
- .word 0 /* Reserved
*/
- .word 0 /* Reserved
*/
- .word 0 /* Reserved
*/
- .word 0 /* Reserved
*/
- .word 0 /* Reserved
*/
- .word 0 /* Reserved
*/
- .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt
*/
- .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt
*/
- .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt
*/
- .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt
*/
- .word 0 /* Reserved
*/
- .word SWPMI1_IRQHandler /* Serial Wire Interface 1
global interrupt */
- .word TIM15_IRQHandler /* TIM15 global Interrupt
*/
- .word TIM16_IRQHandler /* TIM16 global Interrupt
*/
- .word TIM17_IRQHandler /* TIM17 global Interrupt
*/
- .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt
*/
- .word MDIOS_IRQHandler /* MDIOS global Interrupt
*/
- .word 0 /* Reserved
*/
- .word MDMA_IRQHandler /* MDMA global Interrupt
*/
- .word 0 /* Reserved
*/
- .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt
*/
- .word HSEM1_IRQHandler /* HSEM1 global Interrupt
*/
- .word 0 /* Reserved
*/
- .word ADC3_IRQHandler /* ADC3 global Interrupt
*/
- .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt
*/
- .word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global
Interrupt */
- .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global
Interrupt */
- .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global
Interrupt */
- .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global
Interrupt */
- .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global
Interrupt */
- .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global
Interrupt */
- .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global
Interrupt */
- .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global
Interrupt */
- .word COMP1_IRQHandler /* COMP1 global Interrupt
*/
- .word LPTIM2_IRQHandler /* LP TIM2 global interrupt
*/
- .word LPTIM3_IRQHandler /* LP TIM3 global interrupt
*/
- .word LPTIM4_IRQHandler /* LP TIM4 global interrupt
*/
- .word LPTIM5_IRQHandler /* LP TIM5 global interrupt
*/
- .word LPUART1_IRQHandler /* LP UART1 interrupt
*/
- .word 0 /* Reserved
*/
- .word CRS_IRQHandler /* Clock Recovery Global
Interrupt */
- .word ECC_IRQHandler /* ECC diagnostic Global
Interrupt */
- .word SAI4_IRQHandler /* SAI4 global interrupt
*/
- .word DTS_IRQHandler /* Digital Temperature Sensor
interrupt */
- .word 0 /* Reserved
*/
- .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up
pins */
- .word OCTOSPI2_IRQHandler /* OCTOSPI2 Interrupt */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word FMAC_IRQHandler /* FMAC Interrupt */
- .word CORDIC_IRQHandler /* CORDIC Interrupt */
- .word UART9_IRQHandler /* UART9 Interrupt */
- .word USART10_IRQHandler /* UART10 Interrupt */
- .word I2C5_EV_IRQHandler /* I2C5 Event Interrupt */
- .word I2C5_ER_IRQHandler /* I2C5 Error Interrupt */
- .word FDCAN3_IT0_IRQHandler /* FDCAN3 interrupt line 0 */
- .word FDCAN3_IT1_IRQHandler /* FDCAN3 interrupt line 1 */
- .word TIM23_IRQHandler /* TIM23 global interrupt */
- .word TIM24_IRQHandler /* TIM24 global interrupt */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak MemManage_Handler
- .thumb_set MemManage_Handler,Default_Handler
-
- .weak BusFault_Handler
- .thumb_set BusFault_Handler,Default_Handler
-
- .weak UsageFault_Handler
- .thumb_set UsageFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak DebugMon_Handler
- .thumb_set DebugMon_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak WWDG_IRQHandler
- .thumb_set WWDG_IRQHandler,Default_Handler
-
- .weak PVD_AVD_IRQHandler
- .thumb_set PVD_AVD_IRQHandler,Default_Handler
-
- .weak TAMP_STAMP_IRQHandler
- .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
-
- .weak RTC_WKUP_IRQHandler
- .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
- .weak FLASH_IRQHandler
- .thumb_set FLASH_IRQHandler,Default_Handler
-
- .weak RCC_IRQHandler
- .thumb_set RCC_IRQHandler,Default_Handler
-
- .weak EXTI0_IRQHandler
- .thumb_set EXTI0_IRQHandler,Default_Handler
-
- .weak EXTI1_IRQHandler
- .thumb_set EXTI1_IRQHandler,Default_Handler
-
- .weak EXTI2_IRQHandler
- .thumb_set EXTI2_IRQHandler,Default_Handler
-
- .weak EXTI3_IRQHandler
- .thumb_set EXTI3_IRQHandler,Default_Handler
-
- .weak EXTI4_IRQHandler
- .thumb_set EXTI4_IRQHandler,Default_Handler
-
- .weak DMA1_Stream0_IRQHandler
- .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
-
- .weak DMA1_Stream1_IRQHandler
- .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
-
- .weak DMA1_Stream2_IRQHandler
- .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
-
- .weak DMA1_Stream3_IRQHandler
- .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
-
- .weak DMA1_Stream4_IRQHandler
- .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
-
- .weak DMA1_Stream5_IRQHandler
- .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
-
- .weak DMA1_Stream6_IRQHandler
- .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
-
- .weak ADC_IRQHandler
- .thumb_set ADC_IRQHandler,Default_Handler
-
- .weak FDCAN1_IT0_IRQHandler
- .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
-
- .weak FDCAN2_IT0_IRQHandler
- .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
-
- .weak FDCAN1_IT1_IRQHandler
- .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
-
- .weak FDCAN2_IT1_IRQHandler
- .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
-
- .weak EXTI9_5_IRQHandler
- .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
- .weak TIM1_BRK_IRQHandler
- .thumb_set TIM1_BRK_IRQHandler,Default_Handler
-
- .weak TIM1_UP_IRQHandler
- .thumb_set TIM1_UP_IRQHandler,Default_Handler
-
- .weak TIM1_TRG_COM_IRQHandler
- .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
-
- .weak TIM1_CC_IRQHandler
- .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
- .thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak TIM3_IRQHandler
- .thumb_set TIM3_IRQHandler,Default_Handler
-
- .weak TIM4_IRQHandler
- .thumb_set TIM4_IRQHandler,Default_Handler
-
- .weak I2C1_EV_IRQHandler
- .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
- .weak I2C1_ER_IRQHandler
- .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
- .weak I2C2_EV_IRQHandler
- .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
- .weak I2C2_ER_IRQHandler
- .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak SPI2_IRQHandler
- .thumb_set SPI2_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
- .weak USART2_IRQHandler
- .thumb_set USART2_IRQHandler,Default_Handler
-
- .weak USART3_IRQHandler
- .thumb_set USART3_IRQHandler,Default_Handler
-
- .weak EXTI15_10_IRQHandler
- .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
- .weak RTC_Alarm_IRQHandler
- .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
- .weak TIM8_BRK_TIM12_IRQHandler
- .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
-
- .weak TIM8_UP_TIM13_IRQHandler
- .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
-
- .weak TIM8_TRG_COM_TIM14_IRQHandler
- .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
-
- .weak TIM8_CC_IRQHandler
- .thumb_set TIM8_CC_IRQHandler,Default_Handler
-
- .weak DMA1_Stream7_IRQHandler
- .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
-
- .weak FMC_IRQHandler
- .thumb_set FMC_IRQHandler,Default_Handler
-
- .weak SDMMC1_IRQHandler
- .thumb_set SDMMC1_IRQHandler,Default_Handler
-
- .weak TIM5_IRQHandler
- .thumb_set TIM5_IRQHandler,Default_Handler
-
- .weak SPI3_IRQHandler
- .thumb_set SPI3_IRQHandler,Default_Handler
-
- .weak UART4_IRQHandler
- .thumb_set UART4_IRQHandler,Default_Handler
-
- .weak UART5_IRQHandler
- .thumb_set UART5_IRQHandler,Default_Handler
-
- .weak TIM6_DAC_IRQHandler
- .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
- .weak TIM7_IRQHandler
- .thumb_set TIM7_IRQHandler,Default_Handler
-
- .weak DMA2_Stream0_IRQHandler
- .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
-
- .weak DMA2_Stream1_IRQHandler
- .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
-
- .weak DMA2_Stream2_IRQHandler
- .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
-
- .weak DMA2_Stream3_IRQHandler
- .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
-
- .weak DMA2_Stream4_IRQHandler
- .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
-
- .weak ETH_IRQHandler
- .thumb_set ETH_IRQHandler,Default_Handler
-
- .weak ETH_WKUP_IRQHandler
- .thumb_set ETH_WKUP_IRQHandler,Default_Handler
-
- .weak FDCAN_CAL_IRQHandler
- .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
-
- .weak DMA2_Stream5_IRQHandler
- .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
-
- .weak DMA2_Stream6_IRQHandler
- .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
-
- .weak DMA2_Stream7_IRQHandler
- .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
-
- .weak USART6_IRQHandler
- .thumb_set USART6_IRQHandler,Default_Handler
-
- .weak I2C3_EV_IRQHandler
- .thumb_set I2C3_EV_IRQHandler,Default_Handler
-
- .weak I2C3_ER_IRQHandler
- .thumb_set I2C3_ER_IRQHandler,Default_Handler
-
- .weak OTG_HS_EP1_OUT_IRQHandler
- .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
-
- .weak OTG_HS_EP1_IN_IRQHandler
- .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
-
- .weak OTG_HS_WKUP_IRQHandler
- .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
-
- .weak OTG_HS_IRQHandler
- .thumb_set OTG_HS_IRQHandler,Default_Handler
-
- .weak DCMI_PSSI_IRQHandler
- .thumb_set DCMI_PSSI_IRQHandler,Default_Handler
-
- .weak RNG_IRQHandler
- .thumb_set RNG_IRQHandler,Default_Handler
-
- .weak FPU_IRQHandler
- .thumb_set FPU_IRQHandler,Default_Handler
-
- .weak UART7_IRQHandler
- .thumb_set UART7_IRQHandler,Default_Handler
-
- .weak UART8_IRQHandler
- .thumb_set UART8_IRQHandler,Default_Handler
-
- .weak SPI4_IRQHandler
- .thumb_set SPI4_IRQHandler,Default_Handler
-
- .weak SPI5_IRQHandler
- .thumb_set SPI5_IRQHandler,Default_Handler
-
- .weak SPI6_IRQHandler
- .thumb_set SPI6_IRQHandler,Default_Handler
-
- .weak SAI1_IRQHandler
- .thumb_set SAI1_IRQHandler,Default_Handler
-
- .weak LTDC_IRQHandler
- .thumb_set LTDC_IRQHandler,Default_Handler
-
- .weak LTDC_ER_IRQHandler
- .thumb_set LTDC_ER_IRQHandler,Default_Handler
-
- .weak DMA2D_IRQHandler
- .thumb_set DMA2D_IRQHandler,Default_Handler
-
- .weak OCTOSPI1_IRQHandler
- .thumb_set OCTOSPI1_IRQHandler,Default_Handler
-
- .weak LPTIM1_IRQHandler
- .thumb_set LPTIM1_IRQHandler,Default_Handler
-
- .weak CEC_IRQHandler
- .thumb_set CEC_IRQHandler,Default_Handler
-
- .weak I2C4_EV_IRQHandler
- .thumb_set I2C4_EV_IRQHandler,Default_Handler
-
- .weak I2C4_ER_IRQHandler
- .thumb_set I2C4_ER_IRQHandler,Default_Handler
-
- .weak SPDIF_RX_IRQHandler
- .thumb_set SPDIF_RX_IRQHandler,Default_Handler
-
- .weak DMAMUX1_OVR_IRQHandler
- .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
-
- .weak DFSDM1_FLT0_IRQHandler
- .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
-
- .weak DFSDM1_FLT1_IRQHandler
- .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
-
- .weak DFSDM1_FLT2_IRQHandler
- .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
-
- .weak DFSDM1_FLT3_IRQHandler
- .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
-
- .weak SWPMI1_IRQHandler
- .thumb_set SWPMI1_IRQHandler,Default_Handler
-
- .weak TIM15_IRQHandler
- .thumb_set TIM15_IRQHandler,Default_Handler
-
- .weak TIM16_IRQHandler
- .thumb_set TIM16_IRQHandler,Default_Handler
-
- .weak TIM17_IRQHandler
- .thumb_set TIM17_IRQHandler,Default_Handler
-
- .weak MDIOS_WKUP_IRQHandler
- .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
-
- .weak MDIOS_IRQHandler
- .thumb_set MDIOS_IRQHandler,Default_Handler
-
- .weak MDMA_IRQHandler
- .thumb_set MDMA_IRQHandler,Default_Handler
-
- .weak SDMMC2_IRQHandler
- .thumb_set SDMMC2_IRQHandler,Default_Handler
-
- .weak HSEM1_IRQHandler
- .thumb_set HSEM1_IRQHandler,Default_Handler
-
- .weak ADC3_IRQHandler
- .thumb_set ADC3_IRQHandler,Default_Handler
-
- .weak DMAMUX2_OVR_IRQHandler
- .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
-
- .weak BDMA_Channel0_IRQHandler
- .thumb_set BDMA_Channel0_IRQHandler,Default_Handler
-
- .weak BDMA_Channel1_IRQHandler
- .thumb_set BDMA_Channel1_IRQHandler,Default_Handler
-
- .weak BDMA_Channel2_IRQHandler
- .thumb_set BDMA_Channel2_IRQHandler,Default_Handler
-
- .weak BDMA_Channel3_IRQHandler
- .thumb_set BDMA_Channel3_IRQHandler,Default_Handler
-
- .weak BDMA_Channel4_IRQHandler
- .thumb_set BDMA_Channel4_IRQHandler,Default_Handler
-
- .weak BDMA_Channel5_IRQHandler
- .thumb_set BDMA_Channel5_IRQHandler,Default_Handler
-
- .weak BDMA_Channel6_IRQHandler
- .thumb_set BDMA_Channel6_IRQHandler,Default_Handler
-
- .weak BDMA_Channel7_IRQHandler
- .thumb_set BDMA_Channel7_IRQHandler,Default_Handler
-
- .weak COMP1_IRQHandler
- .thumb_set COMP1_IRQHandler,Default_Handler
-
- .weak LPTIM2_IRQHandler
- .thumb_set LPTIM2_IRQHandler,Default_Handler
-
- .weak LPTIM3_IRQHandler
- .thumb_set LPTIM3_IRQHandler,Default_Handler
-
- .weak LPTIM4_IRQHandler
- .thumb_set LPTIM4_IRQHandler,Default_Handler
-
- .weak LPTIM5_IRQHandler
- .thumb_set LPTIM5_IRQHandler,Default_Handler
-
- .weak LPUART1_IRQHandler
- .thumb_set LPUART1_IRQHandler,Default_Handler
-
- .weak CRS_IRQHandler
- .thumb_set CRS_IRQHandler,Default_Handler
-
- .weak ECC_IRQHandler
- .thumb_set ECC_IRQHandler,Default_Handler
-
- .weak SAI4_IRQHandler
- .thumb_set SAI4_IRQHandler,Default_Handler
-
- .weak DTS_IRQHandler
- .thumb_set DTS_IRQHandler,Default_Handler
-
- .weak WAKEUP_PIN_IRQHandler
- .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
-
- .weak OCTOSPI2_IRQHandler
- .thumb_set OCTOSPI2_IRQHandler,Default_Handler
-
- .weak FMAC_IRQHandler
- .thumb_set FMAC_IRQHandler,Default_Handler
-
- .weak CORDIC_IRQHandler
- .thumb_set CORDIC_IRQHandler,Default_Handler
-
- .weak UART9_IRQHandler
- .thumb_set UART9_IRQHandler,Default_Handler
-
- .weak USART10_IRQHandler
- .thumb_set USART10_IRQHandler,Default_Handler
-
- .weak I2C5_EV_IRQHandler
- .thumb_set I2C5_EV_IRQHandler,Default_Handler
-
- .weak I2C5_ER_IRQHandler
- .thumb_set I2C5_ER_IRQHandler,Default_Handler
-
- .weak FDCAN3_IT0_IRQHandler
- .thumb_set FDCAN3_IT0_IRQHandler,Default_Handler
-
- .weak FDCAN3_IT1_IRQHandler
- .thumb_set FDCAN3_IT1_IRQHandler,Default_Handler
-
- .weak TIM23_IRQHandler
- .thumb_set TIM23_IRQHandler,Default_Handler
-
- .weak TIM24_IRQHandler
- .thumb_set TIM24_IRQHandler,Default_Handler
-
-
