This is an automated email from the ASF dual-hosted git repository. kasjer pushed a commit to branch master in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit 25c767f0379fd1e83066738250bcf5eafc7410dc Author: Jerzy Kasenberg <[email protected]> AuthorDate: Tue Apr 7 08:30:45 2026 +0200 hw/mcu: Add support for STM32H5 devices Initial support for STM32H5 device family Signed-off-by: Jerzy Kasenberg <[email protected]> --- hw/mcu/stm/stm32_common/src/hal_gpio.c | 19 +- hw/mcu/stm/stm32_common/src/hal_os_tick.c | 4 +- hw/mcu/stm/stm32_common/src/hal_uart.c | 4 +- hw/mcu/stm/stm32_common/src/stm32_driver_mod_spi.c | 14 +- hw/mcu/stm/stm32h5xx/include/mcu/cmsis_nvic.h | 33 ++ hw/mcu/stm/stm32h5xx/include/mcu/cortex_m33.h | 39 ++ hw/mcu/stm/stm32h5xx/include/mcu/mcu.h | 39 ++ hw/mcu/stm/stm32h5xx/include/mcu/mcu_vectors.h | 34 ++ hw/mcu/stm/stm32h5xx/include/mcu/stm32_hal.h | 126 +++++++ hw/mcu/stm/stm32h5xx/include/mcu/stm32h5_bsp.h | 57 +++ .../stm32h5xx/include/mcu/stm32h5xx_mynewt_hal.h | 67 ++++ .../include/mcu/vectors/stm32h503xx_vectors.h | 169 +++++++++ .../include/mcu/vectors/stm32h523xx_vectors.h | 168 +++++++++ .../include/mcu/vectors/stm32h533xx_vectors.h | 168 +++++++++ .../include/mcu/vectors/stm32h562xx_vectors.h | 166 +++++++++ .../include/mcu/vectors/stm32h563xx_vectors.h | 166 +++++++++ .../include/mcu/vectors/stm32h573xx_vectors.h | 166 +++++++++ hw/mcu/stm/stm32h5xx/pkg.yml | 71 ++++ hw/mcu/stm/stm32h5xx/src/clock_stm32h5xx.c | 193 ++++++++++ hw/mcu/stm/stm32h5xx/src/hal_flash.c | 55 +++ hw/mcu/stm/stm32h5xx/src/hal_reset_cause.c | 47 +++ hw/mcu/stm/stm32h5xx/src/hal_system_init.c | 57 +++ hw/mcu/stm/stm32h5xx/src/hal_timer_freq.c | 129 +++++++ hw/mcu/stm/stm32h5xx/src/system_stm32h5xx.c | 403 +++++++++++++++++++++ hw/mcu/stm/stm32h5xx/syscfg.yml | 288 +++++++++++++++ 25 files changed, 2663 insertions(+), 19 deletions(-) diff --git a/hw/mcu/stm/stm32_common/src/hal_gpio.c b/hw/mcu/stm/stm32_common/src/hal_gpio.c index 93378ccd3..112c5aa0b 100644 --- a/hw/mcu/stm/stm32_common/src/hal_gpio.c +++ b/hw/mcu/stm/stm32_common/src/hal_gpio.c @@ -142,7 +142,7 @@ struct ext_irqs volatile uint32_t irq2; volatile uint32_t irq3; volatile uint32_t irq4; -#if defined(STM32U5) || defined(STM32L5) +#if defined(STM32U5) || defined(STM32L5) || defined(STM32H5) volatile uint32_t irq5; volatile uint32_t irq6; volatile uint32_t irq7; @@ -231,7 +231,7 @@ ext_irq4(void) ext_irq_handler(4); } -#if defined(STM32U5) || defined(STM32L5) +#if defined(STM32U5) || defined(STM32L5) || defined(STM32H5) static void ext_irq5(void) @@ -500,7 +500,7 @@ hal_gpio_pin_to_irq(int pin) } else { irqn = EXTI4_15_IRQn; } -#elif defined(STM32U5) || defined(STM32L5) +#elif defined(STM32U5) || defined(STM32L5) || defined(STM32H5) irqn = EXTI0_IRQn + index; #else if (index <= 4) { @@ -553,7 +553,7 @@ hal_gpio_set_nvic(IRQn_Type irqn) case EXTI4_IRQn: isr = (uint32_t)&ext_irq4; break; -#if defined(STM32U5) || defined(STM32L5) +#if defined(STM32U5) || defined(STM32L5) || defined(STM32H5) case EXTI5_IRQn: isr = (uint32_t)&ext_irq5; break; @@ -971,8 +971,9 @@ hal_gpio_irq_enable(int pin) mask = GPIO_MASK(pin); __HAL_DISABLE_INTERRUPTS(ctx); -#if MYNEWT_VAL(MCU_STM32L4) || MYNEWT_VAL(MCU_STM32WB) || MYNEWT_VAL(MCU_STM32H7) || MYNEWT_VAL(MCU_STM32U5) || \ - MYNEWT_VAL(MCU_STM32G4) || MYNEWT_VAL(MCU_STM32G0) +#if MYNEWT_VAL(MCU_STM32L4) || MYNEWT_VAL(MCU_STM32WB) || \ + MYNEWT_VAL(MCU_STM32H5) || MYNEWT_VAL(MCU_STM32H7) || \ + MYNEWT_VAL(MCU_STM32G0) || MYNEWT_VAL(MCU_STM32G4) || MYNEWT_VAL(MCU_STM32U5) EXTI->IMR1 |= mask; #else EXTI->IMR |= mask; @@ -994,8 +995,10 @@ hal_gpio_irq_disable(int pin) mask = GPIO_MASK(pin); __HAL_DISABLE_INTERRUPTS(ctx); -#if MYNEWT_VAL(MCU_STM32L4) || MYNEWT_VAL(MCU_STM32WB) || MYNEWT_VAL(MCU_STM32H7) || MYNEWT_VAL(MCU_STM32U5) || \ - MYNEWT_VAL(MCU_STM32G4) || MYNEWT_VAL(MCU_STM32G0) +#if MYNEWT_VAL(MCU_STM32L4) || MYNEWT_VAL(MCU_STM32WB) || \ + MYNEWT_VAL(MCU_STM32H5) || MYNEWT_VAL(MCU_STM32H7) || \ + MYNEWT_VAL(MCU_STM32G0) || MYNEWT_VAL(MCU_STM32G4) || MYNEWT_VAL(MCU_STM32U5) + EXTI->IMR1 |= mask; #else EXTI->IMR &= ~mask; diff --git a/hw/mcu/stm/stm32_common/src/hal_os_tick.c b/hw/mcu/stm/stm32_common/src/hal_os_tick.c index a61e53b13..608c7f1f6 100644 --- a/hw/mcu/stm/stm32_common/src/hal_os_tick.c +++ b/hw/mcu/stm/stm32_common/src/hal_os_tick.c @@ -59,7 +59,7 @@ stm32_wfi_from_ram(void) #define SYNCH_PREDIV (32768 / (ASYNCH_PREDIV + 1) - 1) #define SUB_SECONDS_BITS 12 -#if defined(STM32L0) || defined(STM32F0) || defined(STM32U5) +#if defined(STM32L0) || defined(STM32F0) || defined(STM32U5) || defined(STM32H5) #define RTC_IRQ RTC_IRQn #elif defined(STM32G0) #define RTC_IRQ RTC_TAMP_IRQn @@ -406,7 +406,7 @@ os_tick_init(uint32_t os_ticks_per_sec, int prio) /* * Keep clocking debug even when CPU is sleeping, stopped or in standby. */ -#if MYNEWT_VAL(MCU_STM32F0) || MYNEWT_VAL(MCU_STM32U5) +#if MYNEWT_VAL(MCU_STM32F0) || MYNEWT_VAL(MCU_STM32U5) || MYNEWT_VAL(MCU_STM32H5) DBGMCU->CR |= (DBGMCU_CR_DBG_STOP | DBGMCU_CR_DBG_STANDBY); #elif MYNEWT_VAL(MCU_STM32H7) DBGMCU->CR |= (DBGMCU_CR_DBG_SLEEPD1 | DBGMCU_CR_DBG_STOPD1 | DBGMCU_CR_DBG_STANDBYD1); diff --git a/hw/mcu/stm/stm32_common/src/hal_uart.c b/hw/mcu/stm/stm32_common/src/hal_uart.c index cd356763c..83c52149b 100644 --- a/hw/mcu/stm/stm32_common/src/hal_uart.c +++ b/hw/mcu/stm/stm32_common/src/hal_uart.c @@ -149,8 +149,8 @@ static struct hal_uart_irq uart_irqs[3]; # define TC USART_ISR_TC # define RXDR(x) ((x)->RDR) # define TXDR(x) ((x)->TDR) -#if MYNEWT_VAL(MCU_STM32WB) || MYNEWT_VAL(MCU_STM32H7) || MYNEWT_VAL(MCU_STM32U5) || MYNEWT_VAL(MCU_STM32G4) || \ - MYNEWT_VAL(MCU_STM32G0) +#if MYNEWT_VAL(MCU_STM32WB) || MYNEWT_VAL(MCU_STM32H7) || MYNEWT_VAL(MCU_STM32U5) || MYNEWT_VAL(MCU_STM32G4) ||\ + MYNEWT_VAL(MCU_STM32G0) || MYNEWT_VAL(MCU_STM32H5) # define BAUD(x,y) UART_DIV_SAMPLING16((x), (y), UART_PRESCALER_DIV1) #else # define BAUD(x,y) UART_DIV_SAMPLING16((x), (y)) diff --git a/hw/mcu/stm/stm32_common/src/stm32_driver_mod_spi.c b/hw/mcu/stm/stm32_common/src/stm32_driver_mod_spi.c index 4e0e61936..156d44f97 100644 --- a/hw/mcu/stm/stm32_common/src/stm32_driver_mod_spi.c +++ b/hw/mcu/stm/stm32_common/src/stm32_driver_mod_spi.c @@ -54,7 +54,7 @@ HAL_StatusTypeDef HAL_SPI_QueueTransmit(SPI_HandleTypeDef *hspi, uint8_t *pData, #error "This MCU currently does not support SPI slave" #endif -#if !MYNEWT_VAL(MCU_STM32H7) && !defined(STM32U5) +#if !MYNEWT_VAL(MCU_STM32H7) && !defined(STM32U5) && !defined(STM32H5) #define RXDR DR #define TXDR DR #endif @@ -128,7 +128,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) } #endif -#if ((!MYNEWT_VAL(MCU_STM32H7) && !defined(STM32U5)) || !SPI_HAS_FIFO) +#if (!(MYNEWT_VAL(MCU_STM32H7) || defined(STM32U5) || defined(STM32H5)) || !SPI_HAS_FIFO) static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart) { @@ -179,7 +179,7 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, while ((hspi->Instance->SR & Fifo) != State) { -#if MYNEWT_VAL(MCU_STM32H7) || MYNEWT_VAL(MCU_STM32U5) +#if MYNEWT_VAL(MCU_STM32H7) || MYNEWT_VAL(MCU_STM32U5) || MYNEWT_VAL(MCU_STM32H5) if ((Fifo == SPI_SR_RXPLVL) && (State == SPI_RX_FIFO_0PACKET)) { tmpreg = *((__IO uint8_t *)&hspi->Instance->RXDR); @@ -222,7 +222,7 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) { -#if MYNEWT_VAL(MCU_STM32H7) || MYNEWT_VAL(MCU_STM32U5) +#if MYNEWT_VAL(MCU_STM32H7) || MYNEWT_VAL(MCU_STM32U5) || MYNEWT_VAL(MCU_STM32H5) /* Control if the TX fifo is empty */ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_TXC, SPI_SR_TXC, Timeout, Tickstart) != HAL_OK) { @@ -256,7 +256,7 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_ static HAL_StatusTypeDef SPI_EndTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) { -#if MYNEWT_VAL(MCU_STM32H7) || MYNEWT_VAL(MCU_STM32U5) +#if MYNEWT_VAL(MCU_STM32H7) || MYNEWT_VAL(MCU_STM32U5) || MYNEWT_VAL(MCU_STM32H5) /* Control if the TX fifo is empty */ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_TXC, SPI_SR_TXC, Timeout, Tickstart) != HAL_OK) { @@ -644,7 +644,7 @@ HAL_StatusTypeDef HAL_SPI_QueueTransmit(SPI_HandleTypeDef *hspi, uint8_t *pData, #endif /* MYNEWT: in slave mode write 1st byte to DR */ -#if MYNEWT_VAL(MCU_STM32H7) || MYNEWT_VAL(MCU_STM32U5) +#if MYNEWT_VAL(MCU_STM32H7) || MYNEWT_VAL(MCU_STM32U5) || MYNEWT_VAL(MCU_STM32H5) if ((hspi->Instance->CFG2 & SPI_CFG2_MASTER) == 0) { hspi->TxISR(hspi); } @@ -757,7 +757,7 @@ HAL_StatusTypeDef HAL_SPI_Slave_Queue_TransmitReceive(SPI_HandleTypeDef *hspi, u //__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); /* MYNEWT: in slave mode write 1st byte to DR */ -#if MYNEWT_VAL(MCU_STM32H7) || MYNEWT_VAL(MCU_STM32U5) +#if MYNEWT_VAL(MCU_STM32H7) || MYNEWT_VAL(MCU_STM32U5) || MYNEWT_VAL(MCU_STM32H5) if ((hspi->Instance->CFG2 & SPI_CFG2_MASTER) == 0) { hspi->TxISR(hspi); } diff --git a/hw/mcu/stm/stm32h5xx/include/mcu/cmsis_nvic.h b/hw/mcu/stm/stm32h5xx/include/mcu/cmsis_nvic.h new file mode 100644 index 000000000..bb28340a7 --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/include/mcu/cmsis_nvic.h @@ -0,0 +1,33 @@ +/* mbed Microcontroller Library - cmsis_nvic + * Copyright (c) 2009-2011 ARM Limited. All rights reserved. + * + * CMSIS-style functionality to support dynamic vectors + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#include <stdint.h> + +extern uint32_t __isr_vector_start[]; +extern uint32_t __isr_vector_end[]; + +/* Extract number of vectors from .interrupt section size */ +#define NVIC_NUM_VECTORS (__isr_vector_end - __isr_vector_start) +#define NVIC_USER_IRQ_OFFSET 16 + +#include <stm32h5xx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_Relocate(void); +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hw/mcu/stm/stm32h5xx/include/mcu/cortex_m33.h b/hw/mcu/stm/stm32h5xx/include/mcu/cortex_m33.h new file mode 100644 index 000000000..1a5b046dd --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/include/mcu/cortex_m33.h @@ -0,0 +1,39 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#ifndef __MCU_CORTEX_M33_H__ +#define __MCU_CORTEX_M33_H__ + +#include <stm32h5xx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +static inline void +hal_debug_break(void) +{ + __BKPT(1); +} + +#ifdef __cplusplus +} +#endif + +#endif /* __MCU_CORTEX_M33_H__ */ diff --git a/hw/mcu/stm/stm32h5xx/include/mcu/mcu.h b/hw/mcu/stm/stm32h5xx/include/mcu/mcu.h new file mode 100644 index 000000000..d992abe9b --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/include/mcu/mcu.h @@ -0,0 +1,39 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#ifndef __MCU_MCU_H_ +#define __MCU_MCU_H_ + +#include <stm32_common/mcu.h> + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(STM32H503xx) +#define STM32_SYSTEM_MEMORY 0x0BF87000 +#else +#define STM32_SYSTEM_MEMORY 0x0BF97000 +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __MCU_MCU_H_ */ diff --git a/hw/mcu/stm/stm32h5xx/include/mcu/mcu_vectors.h b/hw/mcu/stm/stm32h5xx/include/mcu/mcu_vectors.h new file mode 100644 index 000000000..95bf6b316 --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/include/mcu/mcu_vectors.h @@ -0,0 +1,34 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#if defined(STM32H573xx) +#include "vectors/stm32h573xx_vectors.h" +#elif defined(STM32H563xx) +#include "vectors/stm32h563xx_vectors.h" +#elif defined(STM32H562xx) +#include "vectors/stm32h562xx_vectors.h" +#elif defined(STM32H523xx) +#include "vectors/stm32h523xx_vectors.h" +#elif defined(STM32H533xx) +#include "vectors/stm32h533xx_vectors.h" +#elif defined(STM32H503xx) +#include "vectors/stm32h503xx_vectors.h" +#else +#error "Please select first the target STM32H5xx device used in your application (in stm32h5xx.h file)" +#endif diff --git a/hw/mcu/stm/stm32h5xx/include/mcu/stm32_hal.h b/hw/mcu/stm/stm32h5xx/include/mcu/stm32_hal.h new file mode 100644 index 000000000..4a9b44e14 --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/include/mcu/stm32_hal.h @@ -0,0 +1,126 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#ifndef STM32_HAL_H +#define STM32_HAL_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include <mcu/cortex_m33.h> + +#include <stm32h5xx_hal.h> +#include <stm32h5xx_hal_def.h> + +#include "stm32h5xx_mynewt_hal.h" + +/* hal_watchdog */ +#include <stm32h5xx_hal_iwdg.h> +#define STM32_HAL_WATCHDOG_CUSTOM_INIT(x) \ + do { \ + (x)->Init.Window = IWDG_WINDOW_DISABLE; \ + } while (0) + +/* hal_system_start */ +#define STM32_HAL_FLASH_REMAP() + +/* hal_spi */ +#include <stm32h5xx.h> +#include <stm32h5xx_hal_dma.h> +#include <stm32h5xx_hal_spi.h> +#include <stm32h5xx_hal_gpio.h> +#include <stm32h5xx_hal_gpio_ex.h> +#include <stm32h5xx_hal_rcc.h> + +struct stm32_hal_spi_cfg { + int ss_pin; /* for slave mode */ + int sck_pin; + int miso_pin; + int mosi_pin; + int irq_prio; +}; + +/* hal_i2c */ +#include <stm32h5xx_hal_i2c.h> +#include <mcu/stm32h5xx_mynewt_hal.h> + +/* hal_uart */ +#include <stm32h5xx_hal_uart.h> +#include <mcu/stm32h5_bsp.h> + +/* hal_timer */ +#include <stm32h5xx_hal_tim.h> +#include <stm32h5xx_ll_bus.h> +#include <stm32h5xx_ll_tim.h> + +#define STM32_HAL_TIMER_MAX (3) + +#define STM32_HAL_TIMER_TIM1_IRQ TIM1_CC_IRQn +#define STM32_HAL_TIMER_TIM2_IRQ TIM2_IRQn +#define STM32_HAL_TIMER_TIM6_IRQ TIM6_IRQn +#define STM32_HAL_TIMER_TIM8_IRQ TIM8_CC_IRQn +#define STM32_HAL_TIMER_TIM12_IRQ TIM12_IRQn +#define STM32_HAL_TIMER_TIM13_IRQ TIM13_IRQn +#define STM32_HAL_TIMER_TIM14_IRQ TIM14_IRQn +#define STM32_HAL_TIMER_TIM15_IRQ TIM15_IRQn +#define STM32_HAL_TIMER_TIM16_IRQ TIM16_IRQn +#define STM32_HAL_TIMER_TIM17_IRQ TIM17_IRQn + +/* hw/drivers/trng */ +#include <stm32h5xx_hal_rng.h> + +/* hw/drivers/crypto */ +#include <stm32h5xx_hal_cryp.h> +#include <stm32h5xx_hal_rcc_ex.h> + +/* hal_flash */ +#include <stm32h5xx_hal_def.h> +#include <stm32h5xx_hal_flash.h> +#include <stm32h5xx_hal_flash_ex.h> +#include <stm32h5xx_ll_icache.h> +#define STM32_HAL_FLASH_INIT() \ + do { \ + HAL_FLASH_Unlock(); \ + } while (0) +#define FLASH_PROGRAM_TYPE FLASH_TYPEPROGRAM_QUADWORD +/* Some STM32H5 devices don't have those filed */ +#ifndef FLASH_CCR_CLR_OBKERR +#define FLASH_CCR_CLR_OBKERR 0 +#endif +#ifndef FLASH_CCR_CLR_OBKWERR +#define FLASH_CCR_CLR_OBKWERR 0 +#endif +#define STM32_HAL_FLASH_CLEAR_ERRORS() \ + do { \ + __HAL_FLASH_CLEAR_FLAG(FLASH_CCR_CLR_EOP | \ + FLASH_CCR_CLR_WRPERR | \ + FLASH_CCR_CLR_PGSERR | \ + FLASH_CCR_CLR_STRBERR | \ + FLASH_CCR_CLR_INCERR | \ + FLASH_CCR_CLR_OBKERR | \ + FLASH_CCR_CLR_OBKWERR | \ + FLASH_CCR_CLR_OPTCHANGEERR); \ + } while (0) + +#ifdef __cplusplus +} +#endif + +#endif /* STM32_HAL_H */ diff --git a/hw/mcu/stm/stm32h5xx/include/mcu/stm32h5_bsp.h b/hw/mcu/stm/stm32h5xx/include/mcu/stm32h5_bsp.h new file mode 100644 index 000000000..b8de98a20 --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/include/mcu/stm32h5_bsp.h @@ -0,0 +1,57 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#ifndef __MCU_STM32H5_BSP_H_ +#define __MCU_STM32H5_BSP_H_ + +#include <hal/hal_gpio.h> +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * BSP specific UART settings. + */ +struct stm32_uart_cfg { + USART_TypeDef *suc_uart; /* UART dev registers */ + volatile uint32_t *suc_rcc_reg; /* RCC register to modify */ + uint32_t suc_rcc_dev; /* RCC device ID */ + int8_t suc_pin_tx; /* pins for IO */ + int8_t suc_pin_rx; + int8_t suc_pin_rts; + int8_t suc_pin_cts; + uint8_t suc_pin_af; /* AF selection for this */ + IRQn_Type suc_irqn; /* NVIC IRQn */ +}; + +/* + * Internal API for stm32h5xx mcu specific code. + */ +int hal_gpio_init_af(int pin, uint8_t af_type, enum hal_gpio_pull pull, uint8_t od); + +struct hal_flash; +extern struct hal_flash stm32h5_flash_dev; + +#ifdef __cplusplus +} +#endif + +#endif /* __MCU_STM32H5_BSP_H_ */ diff --git a/hw/mcu/stm/stm32h5xx/include/mcu/stm32h5xx_mynewt_hal.h b/hw/mcu/stm/stm32h5xx/include/mcu/stm32h5xx_mynewt_hal.h new file mode 100644 index 000000000..554bb8579 --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/include/mcu/stm32h5xx_mynewt_hal.h @@ -0,0 +1,67 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#ifndef __MCU_STM32H5_MYNEWT_HAL_H +#define __MCU_STM32H5_MYNEWT_HAL_H + +#include <stm32h5xx.h> +#include <stm32h5xx_hal_dma.h> +#include <stm32h5xx_hal_gpio.h> +#include <stm32h5xx_hal_i2c.h> +#include <stm32h5xx_hal_spi.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Helper functions to enable/disable interrupts. */ +#define __HAL_DISABLE_INTERRUPTS(x) \ + do { \ + x = __get_PRIMASK(); \ + __disable_irq(); \ + } while (0) + +#define __HAL_ENABLE_INTERRUPTS(x) \ + do { \ + if (!x) { \ + __enable_irq(); \ + } \ + } while (0) + +int hal_gpio_init_stm(int pin, GPIO_InitTypeDef *cfg); +int hal_gpio_deinit_stm(int pin, GPIO_InitTypeDef *cfg); + +struct stm32_hal_i2c_cfg { + I2C_TypeDef *hic_i2c; + volatile uint32_t *hic_rcc_reg; /* RCC register to modify */ + uint32_t hic_rcc_dev; /* RCC device ID */ + uint32_t (*get_pclk)(void); + uint8_t hic_pin_sda; + uint8_t hic_pin_scl; + uint8_t hic_pin_af; + uint8_t hic_10bit; + uint32_t hic_timingr; /* TIMINGR register */ + uint32_t hic_speed; /* Requested speed (used when hic_timingr is 0) */ +}; + +#ifdef __cplusplus +} +#endif + +#endif /* __MCU_STM32H5_MYNEWT_HAL_H */ diff --git a/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h503xx_vectors.h b/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h503xx_vectors.h new file mode 100644 index 000000000..93228fef6 --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h503xx_vectors.h @@ -0,0 +1,169 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +INT_VECTOR_STACK_TOP(__StackTop) +INT_VECTOR_RESET_HANDLER(Reset_Handler) +INT_VECTOR_NMI_HANDLER(NMI_Handler) +INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler) +INT_VECTOR_MEMMANAGE_HANDLER(MemManage_Handler) +INT_VECTOR_BUSFAULT_HANDLER(BusFault_Handler) +INT_VECTOR_USAGEFAULT_HANDLER(UsageFault_Handler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_SVC_HANDLER(SVC_Handler) +INT_VECTOR(DebugMon_Handler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_PENDSV_HANDLER(PendSV_Handler) +INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler) +INT_VECTOR(WWDG_IRQHandler) +INT_VECTOR(PVD_AVD_IRQHandler) +INT_VECTOR(RTC_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR(TAMP_IRQHandler) +INT_VECTOR(RAMCFG_IRQHandler) +INT_VECTOR(FLASH_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR(GTZC_IRQHandler) +INT_VECTOR(RCC_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR(EXTI0_IRQHandler) +INT_VECTOR(EXTI1_IRQHandler) +INT_VECTOR(EXTI2_IRQHandler) +INT_VECTOR(EXTI3_IRQHandler) +INT_VECTOR(EXTI4_IRQHandler) +INT_VECTOR(EXTI5_IRQHandler) +INT_VECTOR(EXTI6_IRQHandler) +INT_VECTOR(EXTI7_IRQHandler) +INT_VECTOR(EXTI8_IRQHandler) +INT_VECTOR(EXTI9_IRQHandler) +INT_VECTOR(EXTI10_IRQHandler) +INT_VECTOR(EXTI11_IRQHandler) +INT_VECTOR(EXTI12_IRQHandler) +INT_VECTOR(EXTI13_IRQHandler) +INT_VECTOR(EXTI14_IRQHandler) +INT_VECTOR(EXTI15_IRQHandler) +INT_VECTOR(GPDMA1_Channel0_IRQHandler) +INT_VECTOR(GPDMA1_Channel1_IRQHandler) +INT_VECTOR(GPDMA1_Channel2_IRQHandler) +INT_VECTOR(GPDMA1_Channel3_IRQHandler) +INT_VECTOR(GPDMA1_Channel4_IRQHandler) +INT_VECTOR(GPDMA1_Channel5_IRQHandler) +INT_VECTOR(GPDMA1_Channel6_IRQHandler) +INT_VECTOR(GPDMA1_Channel7_IRQHandler) +INT_VECTOR(IWDG_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR(ADC1_IRQHandler) +INT_VECTOR(DAC1_IRQHandler) +INT_VECTOR(FDCAN1_IT0_IRQHandler) +INT_VECTOR(FDCAN1_IT1_IRQHandler) +INT_VECTOR(TIM1_BRK_IRQHandler) +INT_VECTOR(TIM1_UP_IRQHandler) +INT_VECTOR(TIM1_TRG_COM_IRQHandler) +INT_VECTOR(TIM1_CC_IRQHandler) +INT_VECTOR(TIM2_IRQHandler) +INT_VECTOR(TIM3_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(TIM6_IRQHandler) +INT_VECTOR(TIM7_IRQHandler) +INT_VECTOR(I2C1_EV_IRQHandler) +INT_VECTOR(I2C1_ER_IRQHandler) +INT_VECTOR(I2C2_EV_IRQHandler) +INT_VECTOR(I2C2_ER_IRQHandler) +INT_VECTOR(SPI1_IRQHandler) +INT_VECTOR(SPI2_IRQHandler) +INT_VECTOR(SPI3_IRQHandler) +INT_VECTOR(USART1_IRQHandler) +INT_VECTOR(USART2_IRQHandler) +INT_VECTOR(USART3_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(LPUART1_IRQHandler) +INT_VECTOR(LPTIM1_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(LPTIM2_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(USB_DRD_FS_IRQHandler) +INT_VECTOR(CRS_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(GPDMA2_Channel0_IRQHandler) +INT_VECTOR(GPDMA2_Channel1_IRQHandler) +INT_VECTOR(GPDMA2_Channel2_IRQHandler) +INT_VECTOR(GPDMA2_Channel3_IRQHandler) +INT_VECTOR(GPDMA2_Channel4_IRQHandler) +INT_VECTOR(GPDMA2_Channel5_IRQHandler) +INT_VECTOR(GPDMA2_Channel6_IRQHandler) +INT_VECTOR(GPDMA2_Channel7_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(FPU_IRQHandler) +INT_VECTOR(ICACHE_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(DTS_IRQHandler) +INT_VECTOR(RNG_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(HASH_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(I3C1_EV_IRQHandler) +INT_VECTOR(I3C1_ER_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(I3C2_EV_IRQHandler) +INT_VECTOR(I3C2_ER_IRQHandler) +INT_VECTOR(COMP1_IRQHandler) diff --git a/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h523xx_vectors.h b/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h523xx_vectors.h new file mode 100644 index 000000000..ece06de36 --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h523xx_vectors.h @@ -0,0 +1,168 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +INT_VECTOR_STACK_TOP(__StackTop) +INT_VECTOR_RESET_HANDLER(Reset_Handler) +INT_VECTOR_NMI_HANDLER(NMI_Handler) +INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler) +INT_VECTOR_MEMMANAGE_HANDLER(MemManage_Handler) +INT_VECTOR_BUSFAULT_HANDLER(BusFault_Handler) +INT_VECTOR_USAGEFAULT_HANDLER(UsageFault_Handler) +INT_VECTOR_SECUREFAULT_HANDLER(SecureFault_Handler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_SVC_HANDLER(SVC_Handler) +INT_VECTOR(DebugMon_Handler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_PENDSV_HANDLER(PendSV_Handler) +INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler) +INT_VECTOR(WWDG_IRQHandler) +INT_VECTOR(PVD_AVD_IRQHandler) +INT_VECTOR(RTC_IRQHandler) +INT_VECTOR(RTC_S_IRQHandler) +INT_VECTOR(TAMP_IRQHandler) +INT_VECTOR(RAMCFG_IRQHandler) +INT_VECTOR(FLASH_IRQHandler) +INT_VECTOR(FLASH_S_IRQHandler) +INT_VECTOR(GTZC_IRQHandler) +INT_VECTOR(RCC_IRQHandler) +INT_VECTOR(RCC_S_IRQHandler) +INT_VECTOR(EXTI0_IRQHandler) +INT_VECTOR(EXTI1_IRQHandler) +INT_VECTOR(EXTI2_IRQHandler) +INT_VECTOR(EXTI3_IRQHandler) +INT_VECTOR(EXTI4_IRQHandler) +INT_VECTOR(EXTI5_IRQHandler) +INT_VECTOR(EXTI6_IRQHandler) +INT_VECTOR(EXTI7_IRQHandler) +INT_VECTOR(EXTI8_IRQHandler) +INT_VECTOR(EXTI9_IRQHandler) +INT_VECTOR(EXTI10_IRQHandler) +INT_VECTOR(EXTI11_IRQHandler) +INT_VECTOR(EXTI12_IRQHandler) +INT_VECTOR(EXTI13_IRQHandler) +INT_VECTOR(EXTI14_IRQHandler) +INT_VECTOR(EXTI15_IRQHandler) +INT_VECTOR(GPDMA1_Channel0_IRQHandler) +INT_VECTOR(GPDMA1_Channel1_IRQHandler) +INT_VECTOR(GPDMA1_Channel2_IRQHandler) +INT_VECTOR(GPDMA1_Channel3_IRQHandler) +INT_VECTOR(GPDMA1_Channel4_IRQHandler) +INT_VECTOR(GPDMA1_Channel5_IRQHandler) +INT_VECTOR(GPDMA1_Channel6_IRQHandler) +INT_VECTOR(GPDMA1_Channel7_IRQHandler) +INT_VECTOR(IWDG_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR(ADC1_IRQHandler) +INT_VECTOR(DAC1_IRQHandler) +INT_VECTOR(FDCAN1_IT0_IRQHandler) +INT_VECTOR(FDCAN1_IT1_IRQHandler) +INT_VECTOR(TIM1_BRK_IRQHandler) +INT_VECTOR(TIM1_UP_IRQHandler) +INT_VECTOR(TIM1_TRG_COM_IRQHandler) +INT_VECTOR(TIM1_CC_IRQHandler) +INT_VECTOR(TIM2_IRQHandler) +INT_VECTOR(TIM3_IRQHandler) +INT_VECTOR(TIM4_IRQHandler) +INT_VECTOR(TIM5_IRQHandler) +INT_VECTOR(TIM6_IRQHandler) +INT_VECTOR(TIM7_IRQHandler) +INT_VECTOR(I2C1_EV_IRQHandler) +INT_VECTOR(I2C1_ER_IRQHandler) +INT_VECTOR(I2C2_EV_IRQHandler) +INT_VECTOR(I2C2_ER_IRQHandler) +INT_VECTOR(SPI1_IRQHandler) +INT_VECTOR(SPI2_IRQHandler) +INT_VECTOR(SPI3_IRQHandler) +INT_VECTOR(USART1_IRQHandler) +INT_VECTOR(USART2_IRQHandler) +INT_VECTOR(USART3_IRQHandler) +INT_VECTOR(UART4_IRQHandler) +INT_VECTOR(UART5_IRQHandler) +INT_VECTOR(LPUART1_IRQHandler) +INT_VECTOR(LPTIM1_IRQHandler) +INT_VECTOR(TIM8_BRK_IRQHandler) +INT_VECTOR(TIM8_UP_IRQHandler) +INT_VECTOR(TIM8_TRG_COM_IRQHandler) +INT_VECTOR(TIM8_CC_IRQHandler) +INT_VECTOR(ADC2_IRQHandler) +INT_VECTOR(LPTIM2_IRQHandler) +INT_VECTOR(TIM15_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(USB_DRD_FS_IRQHandler) +INT_VECTOR(CRS_IRQHandler) +INT_VECTOR(UCPD1_IRQHandler) +INT_VECTOR(FMC_IRQHandler) +INT_VECTOR(OCTOSPI1_IRQHandler) +INT_VECTOR(SDMMC1_IRQHandler) +INT_VECTOR(I2C3_EV_IRQHandler) +INT_VECTOR(I2C3_ER_IRQHandler) +INT_VECTOR(SPI4_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(USART6_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(GPDMA2_Channel0_IRQHandler) +INT_VECTOR(GPDMA2_Channel1_IRQHandler) +INT_VECTOR(GPDMA2_Channel2_IRQHandler) +INT_VECTOR(GPDMA2_Channel3_IRQHandler) +INT_VECTOR(GPDMA2_Channel4_IRQHandler) +INT_VECTOR(GPDMA2_Channel5_IRQHandler) +INT_VECTOR(GPDMA2_Channel6_IRQHandler) +INT_VECTOR(GPDMA2_Channel7_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(FPU_IRQHandler) +INT_VECTOR(ICACHE_IRQHandler) +INT_VECTOR(DCACHE1_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(DCMI_PSSI_IRQHandler) +INT_VECTOR(FDCAN2_IT0_IRQHandler) +INT_VECTOR(FDCAN2_IT1_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(DTS_IRQHandler) +INT_VECTOR(RNG_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(HASH_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR(CEC_IRQHandler) +INT_VECTOR(TIM12_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(I3C1_EV_IRQHandler) +INT_VECTOR(I3C1_ER_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(I3C2_EV_IRQHandler) +INT_VECTOR(I3C2_ER_IRQHandler) diff --git a/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h533xx_vectors.h b/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h533xx_vectors.h new file mode 100644 index 000000000..eb10d8031 --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h533xx_vectors.h @@ -0,0 +1,168 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +INT_VECTOR_STACK_TOP(__StackTop) +INT_VECTOR_RESET_HANDLER(Reset_Handler) +INT_VECTOR_NMI_HANDLER(NMI_Handler) +INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler) +INT_VECTOR_MEMMANAGE_HANDLER(MemManage_Handler) +INT_VECTOR_BUSFAULT_HANDLER(BusFault_Handler) +INT_VECTOR_USAGEFAULT_HANDLER(UsageFault_Handler) +INT_VECTOR_SECUREFAULT_HANDLER(SecureFault_Handler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_SVC_HANDLER(SVC_Handler) +INT_VECTOR(DebugMon_Handler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_PENDSV_HANDLER(PendSV_Handler) +INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler) +INT_VECTOR(WWDG_IRQHandler) +INT_VECTOR(PVD_AVD_IRQHandler) +INT_VECTOR(RTC_IRQHandler) +INT_VECTOR(RTC_S_IRQHandler) +INT_VECTOR(TAMP_IRQHandler) +INT_VECTOR(RAMCFG_IRQHandler) +INT_VECTOR(FLASH_IRQHandler) +INT_VECTOR(FLASH_S_IRQHandler) +INT_VECTOR(GTZC_IRQHandler) +INT_VECTOR(RCC_IRQHandler) +INT_VECTOR(RCC_S_IRQHandler) +INT_VECTOR(EXTI0_IRQHandler) +INT_VECTOR(EXTI1_IRQHandler) +INT_VECTOR(EXTI2_IRQHandler) +INT_VECTOR(EXTI3_IRQHandler) +INT_VECTOR(EXTI4_IRQHandler) +INT_VECTOR(EXTI5_IRQHandler) +INT_VECTOR(EXTI6_IRQHandler) +INT_VECTOR(EXTI7_IRQHandler) +INT_VECTOR(EXTI8_IRQHandler) +INT_VECTOR(EXTI9_IRQHandler) +INT_VECTOR(EXTI10_IRQHandler) +INT_VECTOR(EXTI11_IRQHandler) +INT_VECTOR(EXTI12_IRQHandler) +INT_VECTOR(EXTI13_IRQHandler) +INT_VECTOR(EXTI14_IRQHandler) +INT_VECTOR(EXTI15_IRQHandler) +INT_VECTOR(GPDMA1_Channel0_IRQHandler) +INT_VECTOR(GPDMA1_Channel1_IRQHandler) +INT_VECTOR(GPDMA1_Channel2_IRQHandler) +INT_VECTOR(GPDMA1_Channel3_IRQHandler) +INT_VECTOR(GPDMA1_Channel4_IRQHandler) +INT_VECTOR(GPDMA1_Channel5_IRQHandler) +INT_VECTOR(GPDMA1_Channel6_IRQHandler) +INT_VECTOR(GPDMA1_Channel7_IRQHandler) +INT_VECTOR(IWDG_IRQHandler) +INT_VECTOR(SAES_IRQHandler) +INT_VECTOR(ADC1_IRQHandler) +INT_VECTOR(DAC1_IRQHandler) +INT_VECTOR(FDCAN1_IT0_IRQHandler) +INT_VECTOR(FDCAN1_IT1_IRQHandler) +INT_VECTOR(TIM1_BRK_IRQHandler) +INT_VECTOR(TIM1_UP_IRQHandler) +INT_VECTOR(TIM1_TRG_COM_IRQHandler) +INT_VECTOR(TIM1_CC_IRQHandler) +INT_VECTOR(TIM2_IRQHandler) +INT_VECTOR(TIM3_IRQHandler) +INT_VECTOR(TIM4_IRQHandler) +INT_VECTOR(TIM5_IRQHandler) +INT_VECTOR(TIM6_IRQHandler) +INT_VECTOR(TIM7_IRQHandler) +INT_VECTOR(I2C1_EV_IRQHandler) +INT_VECTOR(I2C1_ER_IRQHandler) +INT_VECTOR(I2C2_EV_IRQHandler) +INT_VECTOR(I2C2_ER_IRQHandler) +INT_VECTOR(SPI1_IRQHandler) +INT_VECTOR(SPI2_IRQHandler) +INT_VECTOR(SPI3_IRQHandler) +INT_VECTOR(USART1_IRQHandler) +INT_VECTOR(USART2_IRQHandler) +INT_VECTOR(USART3_IRQHandler) +INT_VECTOR(UART4_IRQHandler) +INT_VECTOR(UART5_IRQHandler) +INT_VECTOR(LPUART1_IRQHandler) +INT_VECTOR(LPTIM1_IRQHandler) +INT_VECTOR(TIM8_BRK_IRQHandler) +INT_VECTOR(TIM8_UP_IRQHandler) +INT_VECTOR(TIM8_TRG_COM_IRQHandler) +INT_VECTOR(TIM8_CC_IRQHandler) +INT_VECTOR(ADC2_IRQHandler) +INT_VECTOR(LPTIM2_IRQHandler) +INT_VECTOR(TIM15_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(USB_DRD_FS_IRQHandler) +INT_VECTOR(CRS_IRQHandler) +INT_VECTOR(UCPD1_IRQHandler) +INT_VECTOR(FMC_IRQHandler) +INT_VECTOR(OCTOSPI1_IRQHandler) +INT_VECTOR(SDMMC1_IRQHandler) +INT_VECTOR(I2C3_EV_IRQHandler) +INT_VECTOR(I2C3_ER_IRQHandler) +INT_VECTOR(SPI4_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(USART6_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(GPDMA2_Channel0_IRQHandler) +INT_VECTOR(GPDMA2_Channel1_IRQHandler) +INT_VECTOR(GPDMA2_Channel2_IRQHandler) +INT_VECTOR(GPDMA2_Channel3_IRQHandler) +INT_VECTOR(GPDMA2_Channel4_IRQHandler) +INT_VECTOR(GPDMA2_Channel5_IRQHandler) +INT_VECTOR(GPDMA2_Channel6_IRQHandler) +INT_VECTOR(GPDMA2_Channel7_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(FPU_IRQHandler) +INT_VECTOR(ICACHE_IRQHandler) +INT_VECTOR(DCACHE1_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(DCMI_PSSI_IRQHandler) +INT_VECTOR(FDCAN2_IT0_IRQHandler) +INT_VECTOR(FDCAN2_IT1_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(DTS_IRQHandler) +INT_VECTOR(RNG_IRQHandler) +INT_VECTOR(OTFDEC1_IRQHandler) +INT_VECTOR(AES_IRQHandler) +INT_VECTOR(HASH_IRQHandler) +INT_VECTOR(PKA_IRQHandler) +INT_VECTOR(CEC_IRQHandler) +INT_VECTOR(TIM12_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(I3C1_EV_IRQHandler) +INT_VECTOR(I3C1_ER_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(I3C2_EV_IRQHandler) +INT_VECTOR(I3C2_ER_IRQHandler) diff --git a/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h562xx_vectors.h b/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h562xx_vectors.h new file mode 100644 index 000000000..e2b206f6b --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h562xx_vectors.h @@ -0,0 +1,166 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +INT_VECTOR_STACK_TOP(__StackTop) +INT_VECTOR_RESET_HANDLER(Reset_Handler) +INT_VECTOR_NMI_HANDLER(NMI_Handler) +INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler) +INT_VECTOR_MEMMANAGE_HANDLER(MemManage_Handler) +INT_VECTOR_BUSFAULT_HANDLER(BusFault_Handler) +INT_VECTOR_USAGEFAULT_HANDLER(UsageFault_Handler) +INT_VECTOR_SECUREFAULT_HANDLER(SecureFault_Handler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_SVC_HANDLER(SVC_Handler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_PENDSV_HANDLER(PendSV_Handler) +INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler) +INT_VECTOR(WWDG_IRQHandler) +INT_VECTOR(PVD_AVD_IRQHandler) +INT_VECTOR(RTC_IRQHandler) +INT_VECTOR(RTC_S_IRQHandler) +INT_VECTOR(TAMP_IRQHandler) +INT_VECTOR(RAMCFG_IRQHandler) +INT_VECTOR(FLASH_IRQHandler) +INT_VECTOR(FLASH_S_IRQHandler) +INT_VECTOR(GTZC_IRQHandler) +INT_VECTOR(RCC_IRQHandler) +INT_VECTOR(RCC_S_IRQHandler) +INT_VECTOR(EXTI0_IRQHandler) +INT_VECTOR(EXTI1_IRQHandler) +INT_VECTOR(EXTI2_IRQHandler) +INT_VECTOR(EXTI3_IRQHandler) +INT_VECTOR(EXTI4_IRQHandler) +INT_VECTOR(EXTI5_IRQHandler) +INT_VECTOR(EXTI6_IRQHandler) +INT_VECTOR(EXTI7_IRQHandler) +INT_VECTOR(EXTI8_IRQHandler) +INT_VECTOR(EXTI9_IRQHandler) +INT_VECTOR(EXTI10_IRQHandler) +INT_VECTOR(EXTI11_IRQHandler) +INT_VECTOR(EXTI12_IRQHandler) +INT_VECTOR(EXTI13_IRQHandler) +INT_VECTOR(EXTI14_IRQHandler) +INT_VECTOR(EXTI15_IRQHandler) +INT_VECTOR(GPDMA1_Channel0_IRQHandler) +INT_VECTOR(GPDMA1_Channel1_IRQHandler) +INT_VECTOR(GPDMA1_Channel2_IRQHandler) +INT_VECTOR(GPDMA1_Channel3_IRQHandler) +INT_VECTOR(GPDMA1_Channel4_IRQHandler) +INT_VECTOR(GPDMA1_Channel5_IRQHandler) +INT_VECTOR(GPDMA1_Channel6_IRQHandler) +INT_VECTOR(GPDMA1_Channel7_IRQHandler) +INT_VECTOR(IWDG_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR(ADC1_IRQHandler) +INT_VECTOR(DAC1_IRQHandler) +INT_VECTOR(FDCAN1_IT0_IRQHandler) +INT_VECTOR(FDCAN1_IT1_IRQHandler) +INT_VECTOR(TIM1_BRK_IRQHandler) +INT_VECTOR(TIM1_UP_IRQHandler) +INT_VECTOR(TIM1_TRG_COM_IRQHandler) +INT_VECTOR(TIM1_CC_IRQHandler) +INT_VECTOR(TIM2_IRQHandler) +INT_VECTOR(TIM3_IRQHandler) +INT_VECTOR(TIM4_IRQHandler) +INT_VECTOR(TIM5_IRQHandler) +INT_VECTOR(TIM6_IRQHandler) +INT_VECTOR(TIM7_IRQHandler) +INT_VECTOR(I2C1_EV_IRQHandler) +INT_VECTOR(I2C1_ER_IRQHandler) +INT_VECTOR(I2C2_EV_IRQHandler) +INT_VECTOR(I2C2_ER_IRQHandler) +INT_VECTOR(SPI1_IRQHandler) +INT_VECTOR(SPI2_IRQHandler) +INT_VECTOR(SPI3_IRQHandler) +INT_VECTOR(USART1_IRQHandler) +INT_VECTOR(USART2_IRQHandler) +INT_VECTOR(USART3_IRQHandler) +INT_VECTOR(UART4_IRQHandler) +INT_VECTOR(UART5_IRQHandler) +INT_VECTOR(LPUART1_IRQHandler) +INT_VECTOR(LPTIM1_IRQHandler) +INT_VECTOR(TIM8_BRK_IRQHandler) +INT_VECTOR(TIM8_UP_IRQHandler) +INT_VECTOR(TIM8_TRG_COM_IRQHandler) +INT_VECTOR(TIM8_CC_IRQHandler) +INT_VECTOR(ADC2_IRQHandler) +INT_VECTOR(LPTIM2_IRQHandler) +INT_VECTOR(TIM15_IRQHandler) +INT_VECTOR(TIM16_IRQHandler) +INT_VECTOR(TIM17_IRQHandler) +INT_VECTOR(USB_DRD_FS_IRQHandler) +INT_VECTOR(CRS_IRQHandler) +INT_VECTOR(UCPD1_IRQHandler) +INT_VECTOR(FMC_IRQHandler) +INT_VECTOR(OCTOSPI1_IRQHandler) +INT_VECTOR(SDMMC1_IRQHandler) +INT_VECTOR(I2C3_EV_IRQHandler) +INT_VECTOR(I2C3_ER_IRQHandler) +INT_VECTOR(SPI4_IRQHandler) +INT_VECTOR(SPI5_IRQHandler) +INT_VECTOR(SPI6_IRQHandler) +INT_VECTOR(USART6_IRQHandler) +INT_VECTOR(USART10_IRQHandler) +INT_VECTOR(USART11_IRQHandler) +INT_VECTOR(SAI1_IRQHandler) +INT_VECTOR(SAI2_IRQHandler) +INT_VECTOR(GPDMA2_Channel0_IRQHandler) +INT_VECTOR(GPDMA2_Channel1_IRQHandler) +INT_VECTOR(GPDMA2_Channel2_IRQHandler) +INT_VECTOR(GPDMA2_Channel3_IRQHandler) +INT_VECTOR(GPDMA2_Channel4_IRQHandler) +INT_VECTOR(GPDMA2_Channel5_IRQHandler) +INT_VECTOR(GPDMA2_Channel6_IRQHandler) +INT_VECTOR(GPDMA2_Channel7_IRQHandler) +INT_VECTOR(UART7_IRQHandler) +INT_VECTOR(UART8_IRQHandler) +INT_VECTOR(UART9_IRQHandler) +INT_VECTOR(UART12_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR(FPU_IRQHandler) +INT_VECTOR(ICACHE_IRQHandler) +INT_VECTOR(DCACHE1_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(DCMI_PSSI_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(CORDIC_IRQHandler) +INT_VECTOR(FMAC_IRQHandler) +INT_VECTOR(DTS_IRQHandler) +INT_VECTOR(RNG_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(HASH_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR(CEC_IRQHandler) +INT_VECTOR(TIM12_IRQHandler) +INT_VECTOR(TIM13_IRQHandler) +INT_VECTOR(TIM14_IRQHandler) +INT_VECTOR(I3C1_EV_IRQHandler) +INT_VECTOR(I3C1_ER_IRQHandler) +INT_VECTOR(I2C4_EV_IRQHandler) +INT_VECTOR(I2C4_ER_IRQHandler) +INT_VECTOR(LPTIM3_IRQHandler) +INT_VECTOR(LPTIM4_IRQHandler) +INT_VECTOR(LPTIM5_IRQHandler) +INT_VECTOR(LPTIM6_IRQHandler) diff --git a/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h563xx_vectors.h b/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h563xx_vectors.h new file mode 100644 index 000000000..a1095059c --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h563xx_vectors.h @@ -0,0 +1,166 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +INT_VECTOR_STACK_TOP(__StackTop) +INT_VECTOR_RESET_HANDLER(Reset_Handler) +INT_VECTOR_NMI_HANDLER(NMI_Handler) +INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler) +INT_VECTOR_MEMMANAGE_HANDLER(MemManage_Handler) +INT_VECTOR_BUSFAULT_HANDLER(BusFault_Handler) +INT_VECTOR_USAGEFAULT_HANDLER(UsageFault_Handler) +INT_VECTOR_SECUREFAULT_HANDLER(SecureFault_Handler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_SVC_HANDLER(SVC_Handler) +INT_VECTOR_DEBUGMON_HANDLER(DebugMon_Handler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_PENDSV_HANDLER(PendSV_Handler) +INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler) +INT_VECTOR(WWDG_IRQHandler) +INT_VECTOR(PVD_AVD_IRQHandler) +INT_VECTOR(RTC_IRQHandler) +INT_VECTOR(RTC_S_IRQHandler) +INT_VECTOR(TAMP_IRQHandler) +INT_VECTOR(RAMCFG_IRQHandler) +INT_VECTOR(FLASH_IRQHandler) +INT_VECTOR(FLASH_S_IRQHandler) +INT_VECTOR(GTZC_IRQHandler) +INT_VECTOR(RCC_IRQHandler) +INT_VECTOR(RCC_S_IRQHandler) +INT_VECTOR(EXTI0_IRQHandler) +INT_VECTOR(EXTI1_IRQHandler) +INT_VECTOR(EXTI2_IRQHandler) +INT_VECTOR(EXTI3_IRQHandler) +INT_VECTOR(EXTI4_IRQHandler) +INT_VECTOR(EXTI5_IRQHandler) +INT_VECTOR(EXTI6_IRQHandler) +INT_VECTOR(EXTI7_IRQHandler) +INT_VECTOR(EXTI8_IRQHandler) +INT_VECTOR(EXTI9_IRQHandler) +INT_VECTOR(EXTI10_IRQHandler) +INT_VECTOR(EXTI11_IRQHandler) +INT_VECTOR(EXTI12_IRQHandler) +INT_VECTOR(EXTI13_IRQHandler) +INT_VECTOR(EXTI14_IRQHandler) +INT_VECTOR(EXTI15_IRQHandler) +INT_VECTOR(GPDMA1_Channel0_IRQHandler) +INT_VECTOR(GPDMA1_Channel1_IRQHandler) +INT_VECTOR(GPDMA1_Channel2_IRQHandler) +INT_VECTOR(GPDMA1_Channel3_IRQHandler) +INT_VECTOR(GPDMA1_Channel4_IRQHandler) +INT_VECTOR(GPDMA1_Channel5_IRQHandler) +INT_VECTOR(GPDMA1_Channel6_IRQHandler) +INT_VECTOR(GPDMA1_Channel7_IRQHandler) +INT_VECTOR(IWDG_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR(ADC1_IRQHandler) +INT_VECTOR(DAC1_IRQHandler) +INT_VECTOR(FDCAN1_IT0_IRQHandler) +INT_VECTOR(FDCAN1_IT1_IRQHandler) +INT_VECTOR(TIM1_BRK_IRQHandler) +INT_VECTOR(TIM1_UP_IRQHandler) +INT_VECTOR(TIM1_TRG_COM_IRQHandler) +INT_VECTOR(TIM1_CC_IRQHandler) +INT_VECTOR(TIM2_IRQHandler) +INT_VECTOR(TIM3_IRQHandler) +INT_VECTOR(TIM4_IRQHandler) +INT_VECTOR(TIM5_IRQHandler) +INT_VECTOR(TIM6_IRQHandler) +INT_VECTOR(TIM7_IRQHandler) +INT_VECTOR(I2C1_EV_IRQHandler) +INT_VECTOR(I2C1_ER_IRQHandler) +INT_VECTOR(I2C2_EV_IRQHandler) +INT_VECTOR(I2C2_ER_IRQHandler) +INT_VECTOR(SPI1_IRQHandler) +INT_VECTOR(SPI2_IRQHandler) +INT_VECTOR(SPI3_IRQHandler) +INT_VECTOR(USART1_IRQHandler) +INT_VECTOR(USART2_IRQHandler) +INT_VECTOR(USART3_IRQHandler) +INT_VECTOR(UART4_IRQHandler) +INT_VECTOR(UART5_IRQHandler) +INT_VECTOR(LPUART1_IRQHandler) +INT_VECTOR(LPTIM1_IRQHandler) +INT_VECTOR(TIM8_BRK_IRQHandler) +INT_VECTOR(TIM8_UP_IRQHandler) +INT_VECTOR(TIM8_TRG_COM_IRQHandler) +INT_VECTOR(TIM8_CC_IRQHandler) +INT_VECTOR(ADC2_IRQHandler) +INT_VECTOR(LPTIM2_IRQHandler) +INT_VECTOR(TIM15_IRQHandler) +INT_VECTOR(TIM16_IRQHandler) +INT_VECTOR(TIM17_IRQHandler) +INT_VECTOR(USB_DRD_FS_IRQHandler) +INT_VECTOR(CRS_IRQHandler) +INT_VECTOR(UCPD1_IRQHandler) +INT_VECTOR(FMC_IRQHandler) +INT_VECTOR(OCTOSPI1_IRQHandler) +INT_VECTOR(SDMMC1_IRQHandler) +INT_VECTOR(I2C3_EV_IRQHandler) +INT_VECTOR(I2C3_ER_IRQHandler) +INT_VECTOR(SPI4_IRQHandler) +INT_VECTOR(SPI5_IRQHandler) +INT_VECTOR(SPI6_IRQHandler) +INT_VECTOR(USART6_IRQHandler) +INT_VECTOR(USART10_IRQHandler) +INT_VECTOR(USART11_IRQHandler) +INT_VECTOR(SAI1_IRQHandler) +INT_VECTOR(SAI2_IRQHandler) +INT_VECTOR(GPDMA2_Channel0_IRQHandler) +INT_VECTOR(GPDMA2_Channel1_IRQHandler) +INT_VECTOR(GPDMA2_Channel2_IRQHandler) +INT_VECTOR(GPDMA2_Channel3_IRQHandler) +INT_VECTOR(GPDMA2_Channel4_IRQHandler) +INT_VECTOR(GPDMA2_Channel5_IRQHandler) +INT_VECTOR(GPDMA2_Channel6_IRQHandler) +INT_VECTOR(GPDMA2_Channel7_IRQHandler) +INT_VECTOR(UART7_IRQHandler) +INT_VECTOR(UART8_IRQHandler) +INT_VECTOR(UART9_IRQHandler) +INT_VECTOR(UART12_IRQHandler) +INT_VECTOR(SDMMC2_IRQHandler) +INT_VECTOR(FPU_IRQHandler) +INT_VECTOR(ICACHE_IRQHandler) +INT_VECTOR(DCACHE1_IRQHandler) +INT_VECTOR(ETH_IRQHandler) +INT_VECTOR(ETH_WKUP_IRQHandler) +INT_VECTOR(DCMI_PSSI_IRQHandler) +INT_VECTOR(FDCAN2_IT0_IRQHandler) +INT_VECTOR(FDCAN2_IT1_IRQHandler) +INT_VECTOR(CORDIC_IRQHandler) +INT_VECTOR(FMAC_IRQHandler) +INT_VECTOR(DTS_IRQHandler) +INT_VECTOR(RNG_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(HASH_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR(CEC_IRQHandler) +INT_VECTOR(TIM12_IRQHandler) +INT_VECTOR(TIM13_IRQHandler) +INT_VECTOR(TIM14_IRQHandler) +INT_VECTOR(I3C1_EV_IRQHandler) +INT_VECTOR(I3C1_ER_IRQHandler) +INT_VECTOR(I2C4_EV_IRQHandler) +INT_VECTOR(I2C4_ER_IRQHandler) +INT_VECTOR(LPTIM3_IRQHandler) +INT_VECTOR(LPTIM4_IRQHandler) +INT_VECTOR(LPTIM5_IRQHandler) +INT_VECTOR(LPTIM6_IRQHandler) diff --git a/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h573xx_vectors.h b/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h573xx_vectors.h new file mode 100644 index 000000000..d7acec3ec --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h573xx_vectors.h @@ -0,0 +1,166 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +INT_VECTOR_STACK_TOP(__StackTop) +INT_VECTOR_RESET_HANDLER(Reset_Handler) +INT_VECTOR_NMI_HANDLER(NMI_Handler) +INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler) +INT_VECTOR_MEMMANAGE_HANDLER(MemManage_Handler) +INT_VECTOR_BUSFAULT_HANDLER(BusFault_Handler) +INT_VECTOR_USAGEFAULT_HANDLER(UsageFault_Handler) +INT_VECTOR_SECUREFAULT_HANDLER(SecureFault_Handler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_SVC_HANDLER(SVC_Handler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_PENDSV_HANDLER(PendSV_Handler) +INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler) +INT_VECTOR(WWDG_IRQHandler) +INT_VECTOR(PVD_AVD_IRQHandler) +INT_VECTOR(RTC_IRQHandler) +INT_VECTOR(RTC_S_IRQHandler) +INT_VECTOR(TAMP_IRQHandler) +INT_VECTOR(RAMCFG_IRQHandler) +INT_VECTOR(FLASH_IRQHandler) +INT_VECTOR(FLASH_S_IRQHandler) +INT_VECTOR(GTZC_IRQHandler) +INT_VECTOR(RCC_IRQHandler) +INT_VECTOR(RCC_S_IRQHandler) +INT_VECTOR(EXTI0_IRQHandler) +INT_VECTOR(EXTI1_IRQHandler) +INT_VECTOR(EXTI2_IRQHandler) +INT_VECTOR(EXTI3_IRQHandler) +INT_VECTOR(EXTI4_IRQHandler) +INT_VECTOR(EXTI5_IRQHandler) +INT_VECTOR(EXTI6_IRQHandler) +INT_VECTOR(EXTI7_IRQHandler) +INT_VECTOR(EXTI8_IRQHandler) +INT_VECTOR(EXTI9_IRQHandler) +INT_VECTOR(EXTI10_IRQHandler) +INT_VECTOR(EXTI11_IRQHandler) +INT_VECTOR(EXTI12_IRQHandler) +INT_VECTOR(EXTI13_IRQHandler) +INT_VECTOR(EXTI14_IRQHandler) +INT_VECTOR(EXTI15_IRQHandler) +INT_VECTOR(GPDMA1_Channel0_IRQHandler) +INT_VECTOR(GPDMA1_Channel1_IRQHandler) +INT_VECTOR(GPDMA1_Channel2_IRQHandler) +INT_VECTOR(GPDMA1_Channel3_IRQHandler) +INT_VECTOR(GPDMA1_Channel4_IRQHandler) +INT_VECTOR(GPDMA1_Channel5_IRQHandler) +INT_VECTOR(GPDMA1_Channel6_IRQHandler) +INT_VECTOR(GPDMA1_Channel7_IRQHandler) +INT_VECTOR(IWDG_IRQHandler) +INT_VECTOR(SAES_IRQHandler) +INT_VECTOR(ADC1_IRQHandler) +INT_VECTOR(DAC1_IRQHandler) +INT_VECTOR(FDCAN1_IT0_IRQHandler) +INT_VECTOR(FDCAN1_IT1_IRQHandler) +INT_VECTOR(TIM1_BRK_IRQHandler) +INT_VECTOR(TIM1_UP_IRQHandler) +INT_VECTOR(TIM1_TRG_COM_IRQHandler) +INT_VECTOR(TIM1_CC_IRQHandler) +INT_VECTOR(TIM2_IRQHandler) +INT_VECTOR(TIM3_IRQHandler) +INT_VECTOR(TIM4_IRQHandler) +INT_VECTOR(TIM5_IRQHandler) +INT_VECTOR(TIM6_IRQHandler) +INT_VECTOR(TIM7_IRQHandler) +INT_VECTOR(I2C1_EV_IRQHandler) +INT_VECTOR(I2C1_ER_IRQHandler) +INT_VECTOR(I2C2_EV_IRQHandler) +INT_VECTOR(I2C2_ER_IRQHandler) +INT_VECTOR(SPI1_IRQHandler) +INT_VECTOR(SPI2_IRQHandler) +INT_VECTOR(SPI3_IRQHandler) +INT_VECTOR(USART1_IRQHandler) +INT_VECTOR(USART2_IRQHandler) +INT_VECTOR(USART3_IRQHandler) +INT_VECTOR(UART4_IRQHandler) +INT_VECTOR(UART5_IRQHandler) +INT_VECTOR(LPUART1_IRQHandler) +INT_VECTOR(LPTIM1_IRQHandler) +INT_VECTOR(TIM8_BRK_IRQHandler) +INT_VECTOR(TIM8_UP_IRQHandler) +INT_VECTOR(TIM8_TRG_COM_IRQHandler) +INT_VECTOR(TIM8_CC_IRQHandler) +INT_VECTOR(ADC2_IRQHandler) +INT_VECTOR(LPTIM2_IRQHandler) +INT_VECTOR(TIM15_IRQHandler) +INT_VECTOR(TIM16_IRQHandler) +INT_VECTOR(TIM17_IRQHandler) +INT_VECTOR(USB_DRD_FS_IRQHandler) +INT_VECTOR(CRS_IRQHandler) +INT_VECTOR(UCPD1_IRQHandler) +INT_VECTOR(FMC_IRQHandler) +INT_VECTOR(OCTOSPI1_IRQHandler) +INT_VECTOR(SDMMC1_IRQHandler) +INT_VECTOR(I2C3_EV_IRQHandler) +INT_VECTOR(I2C3_ER_IRQHandler) +INT_VECTOR(SPI4_IRQHandler) +INT_VECTOR(SPI5_IRQHandler) +INT_VECTOR(SPI6_IRQHandler) +INT_VECTOR(USART6_IRQHandler) +INT_VECTOR(USART10_IRQHandler) +INT_VECTOR(USART11_IRQHandler) +INT_VECTOR(SAI1_IRQHandler) +INT_VECTOR(SAI2_IRQHandler) +INT_VECTOR(GPDMA2_Channel0_IRQHandler) +INT_VECTOR(GPDMA2_Channel1_IRQHandler) +INT_VECTOR(GPDMA2_Channel2_IRQHandler) +INT_VECTOR(GPDMA2_Channel3_IRQHandler) +INT_VECTOR(GPDMA2_Channel4_IRQHandler) +INT_VECTOR(GPDMA2_Channel5_IRQHandler) +INT_VECTOR(GPDMA2_Channel6_IRQHandler) +INT_VECTOR(GPDMA2_Channel7_IRQHandler) +INT_VECTOR(UART7_IRQHandler) +INT_VECTOR(UART8_IRQHandler) +INT_VECTOR(UART9_IRQHandler) +INT_VECTOR(UART12_IRQHandler) +INT_VECTOR(SDMMC2_IRQHandler) +INT_VECTOR(FPU_IRQHandler) +INT_VECTOR(ICACHE_IRQHandler) +INT_VECTOR(DCACHE1_IRQHandler) +INT_VECTOR(ETH_IRQHandler) +INT_VECTOR(ETH_WKUP_IRQHandler) +INT_VECTOR(DCMI_PSSI_IRQHandler) +INT_VECTOR(FDCAN2_IT0_IRQHandler) +INT_VECTOR(FDCAN2_IT1_IRQHandler) +INT_VECTOR(CORDIC_IRQHandler) +INT_VECTOR(FMAC_IRQHandler) +INT_VECTOR(DTS_IRQHandler) +INT_VECTOR(RNG_IRQHandler) +INT_VECTOR(OTFDEC1_IRQHandler) +INT_VECTOR(AES_IRQHandler) +INT_VECTOR(HASH_IRQHandler) +INT_VECTOR(PKA_IRQHandler) +INT_VECTOR(CEC_IRQHandler) +INT_VECTOR(TIM12_IRQHandler) +INT_VECTOR(TIM13_IRQHandler) +INT_VECTOR(TIM14_IRQHandler) +INT_VECTOR(I3C1_EV_IRQHandler) +INT_VECTOR(I3C1_ER_IRQHandler) +INT_VECTOR(I2C4_EV_IRQHandler) +INT_VECTOR(I2C4_ER_IRQHandler) +INT_VECTOR(LPTIM3_IRQHandler) +INT_VECTOR(LPTIM4_IRQHandler) +INT_VECTOR(LPTIM5_IRQHandler) +INT_VECTOR(LPTIM6_IRQHandler) diff --git a/hw/mcu/stm/stm32h5xx/pkg.yml b/hw/mcu/stm/stm32h5xx/pkg.yml new file mode 100644 index 000000000..ea98076c0 --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/pkg.yml @@ -0,0 +1,71 @@ +# +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +pkg.name: hw/mcu/stm/stm32h5xx +pkg.description: MCU definition for STM32H5 ARM Cortex-M33 chips. +pkg.author: "Apache Mynewt <[email protected]>" +pkg.homepage: "http://mynewt.apache.org/"; +pkg.keywords: + - stm32 + - stm32h5 + +pkg.type: sdk + +pkg.cflags: + - -Wno-maybe-uninitialized + +pkg.ign_files: + - ".*template.*" + +pkg.include_dirs: + - "@stm-cmsis_device_h5/Include" + - "@stm-stm32h5xx_hal_driver/Inc" + +pkg.src_dirs: + - "@stm-cmsis_device_h5/Source/Templates/gcc" + - "@stm-stm32h5xx_hal_driver/Src" + - "src" + +pkg.ign_dirs: + - "Device" + +pkg.deps: + - "@apache-mynewt-core/hw/hal" + - "@apache-mynewt-core/hw/mcu/stm/stm32_common" + - "@apache-mynewt-core/hw/cmsis-core" + +pkg.deps.'(SPI_0_MASTER || SPI_1_MASTER || SPI_2_MASTER || SPI_3_MASTER || SPI_4_MASTER || SPI_5_MASTER) && BUS_DRIVER_PRESENT': + - "@apache-mynewt-core/hw/bus/drivers/spi_stm32" + +#pkg.deps.ETH_0: +# - "@apache-mynewt-core/hw/drivers/lwip/stm32h_eth" + +repository.stm-cmsis_device_h5: + type: github + vers: v1.6.0-commit + branch: main + user: STMicroelectronics + repo: cmsis_device_h5 + +repository.stm-stm32h5xx_hal_driver: + type: github + vers: v1.6.0-commit + branch: main + user: STMicroelectronics + repo: stm32h5xx_hal_driver diff --git a/hw/mcu/stm/stm32h5xx/src/clock_stm32h5xx.c b/hw/mcu/stm/stm32h5xx/src/clock_stm32h5xx.c new file mode 100644 index 000000000..7951e625f --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/src/clock_stm32h5xx.c @@ -0,0 +1,193 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include <os/mynewt.h> +#include <assert.h> +#include <stm32h5xx_hal.h> +#include <stm32h5xx_hal_pwr_ex.h> +#include <stm32h5xx_ll_rcc.h> +#include <stm32h5xx_ll_pwr.h> + +/* + * This allows an user to have a custom clock configuration by zeroing + * every possible clock source in the syscfg. + */ +#if MYNEWT_VAL_STM32_CLOCK_HSE || MYNEWT_VAL_STM32_CLOCK_LSE || \ + MYNEWT_VAL_STM32_CLOCK_HSI || MYNEWT_VAL_STM32_CLOCK_LSI + +/* + * HSI is turned on by default, but can be turned off and use HSE instead. + */ +_Static_assert((MYNEWT_VAL_STM32_CLOCK_HSE != 0) + (MYNEWT_VAL_STM32_CLOCK_HSI != 0) >= 1, + "At least one of HSE or HSI clock source must be enabled"); + +#define PLL_ON(n) (MYNEWT_VAL_STM32_CLOCK_##n != 0) +#define PLL_OFF(n) (MYNEWT_VAL_STM32_CLOCK_##n == 0) +#define PLL_VAL(n, val) MYNEWT_VAL_STM32_CLOCK_##n##_##val + +_Static_assert(PLL_OFF(PLL1) || IS_RCC_PLLM_VALUE(PLL_VAL(PLL1, PLLM)), + "PLLM value is invalid"); +_Static_assert(PLL_OFF(PLL1) || IS_RCC_PLLN_VALUE(PLL_VAL(PLL1, PLLN)), + "PLLN value is invalid"); +_Static_assert(PLL_OFF(PLL1) || IS_RCC_PLLP_VALUE(PLL_VAL(PLL1, PLLP)), + "PLLP value is invalid"); +_Static_assert(PLL_OFF(PLL1) || IS_RCC_PLLQ_VALUE(PLL_VAL(PLL1, PLLQ)), + "PLLQ value is invalid"); +_Static_assert(PLL_OFF(PLL1) || IS_RCC_PLLR_VALUE(PLL_VAL(PLL1, PLLR)), + "PLLR value is invalid"); + +_Static_assert(PLL_OFF(PLL2) || IS_RCC_PLLM_VALUE(PLL_VAL(PLL2, PLLM)), + "PLLM value is invalid"); +_Static_assert(PLL_OFF(PLL2) || IS_RCC_PLLN_VALUE(PLL_VAL(PLL2, PLLN)), + "PLLN value is invalid"); +_Static_assert(PLL_OFF(PLL2) || IS_RCC_PLLP_VALUE(PLL_VAL(PLL2, PLLP)), + "PLLP value is invalid"); +_Static_assert(PLL_OFF(PLL2) || IS_RCC_PLLQ_VALUE(PLL_VAL(PLL2, PLLQ)), + "PLLQ value is invalid"); +_Static_assert(PLL_OFF(PLL2) || IS_RCC_PLLR_VALUE(PLL_VAL(PLL2, PLLR)), + "PLLR value is invalid"); + +_Static_assert(PLL_OFF(PLL3) || IS_RCC_PLLM_VALUE(PLL_VAL(PLL3, PLLM)), + "PLLM value is invalid"); +_Static_assert(PLL_OFF(PLL3) || IS_RCC_PLLN_VALUE(PLL_VAL(PLL3, PLLN)), + "PLLN value is invalid"); +_Static_assert(PLL_OFF(PLL3) || IS_RCC_PLLP_VALUE(PLL_VAL(PLL3, PLLP)), + "PLLP value is invalid"); +_Static_assert(PLL_OFF(PLL3) || IS_RCC_PLLQ_VALUE(PLL_VAL(PLL3, PLLQ)), + "PLLQ value is invalid"); +_Static_assert(PLL_OFF(PLL3) || IS_RCC_PLLR_VALUE(PLL_VAL(PLL3, PLLR)), + "PLLR value is invalid"); + +_Static_assert(MYNEWT_VAL_STM32_CLOCK_SYSCLK_SOURCE != LL_RCC_SYS_CLKSOURCE_PLL1 || + PLL_ON(PLL1), + "PLL1 selected as system clock but no enabled"); + +#define BUSY_LOOP(cond) \ + while (cond) { \ + } + +void +SystemClock_Config(void) +{ + LL_PWR_SetRegulVoltageScaling(MYNEWT_VAL_STM32_CLOCK_VOLTAGESCALING_CONFIG); + BUSY_LOOP(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)); + + __HAL_FLASH_SET_LATENCY(MYNEWT_VAL_STM32_FLASH_LATENCY); + + if (MYNEWT_VAL_STM32_CLOCK_LSI) { + LL_RCC_LSI_Enable(); + } + if (MYNEWT_VAL_STM32_CLOCK_LSE_BYPASS && !LL_RCC_LSE_IsReady()) { + LL_PWR_EnableBkUpAccess(); + LL_RCC_LSE_EnableBypass(); + } + if (MYNEWT_VAL_STM32_CLOCK_LSE && !LL_RCC_LSE_IsReady()) { + LL_PWR_EnableBkUpAccess(); + LL_RCC_LSE_Enable(); + } + if (MYNEWT_VAL_STM32_CLOCK_HSE_BYPASS) { + LL_RCC_HSE_EnableBypass(); + } + if (MYNEWT_VAL_STM32_CLOCK_HSE) { + LL_RCC_HSE_Enable(); + } + + if (MYNEWT_VAL_STM32_CLOCK_HSI48) { + LL_RCC_HSI48_Enable(); + } + + LL_RCC_SetAHBPrescaler(MYNEWT_VAL_STM32_CLOCK_AHB_DIVIDER); + LL_RCC_SetAPB1Prescaler(MYNEWT_VAL_STM32_CLOCK_APB1_DIVIDER); + LL_RCC_SetAPB2Prescaler(MYNEWT_VAL_STM32_CLOCK_APB2_DIVIDER); + LL_RCC_SetAPB3Prescaler(MYNEWT_VAL_STM32_CLOCK_APB3_DIVIDER); + + if (MYNEWT_VAL_STM32_CLOCK_USBSEL) { + LL_RCC_SetUSBClockSource(MYNEWT_VAL_STM32_CLOCK_USBSEL); + } + + BUSY_LOOP(PLL_VAL(PLL1, SOURCE) == LL_RCC_PLL1SOURCE_HSE && !LL_RCC_HSE_IsReady()); + BUSY_LOOP(PLL_VAL(PLL1, SOURCE) == LL_RCC_PLL1SOURCE_HSI && !LL_RCC_HSI_IsReady()); + BUSY_LOOP(PLL_VAL(PLL1, SOURCE) == LL_RCC_PLL1SOURCE_CSI && !LL_RCC_CSI_IsReady()); + if (PLL_ON(PLL1)) { + LL_RCC_PLL1_SetSource(MYNEWT_VAL_STM32_CLOCK_PLL1_SOURCE); + LL_RCC_PLL1_SetM(MYNEWT_VAL_STM32_CLOCK_PLL1_PLLM); + LL_RCC_PLL1_SetN(MYNEWT_VAL_STM32_CLOCK_PLL1_PLLN); + LL_RCC_PLL1_SetP(MYNEWT_VAL_STM32_CLOCK_PLL1_PLLP); + LL_RCC_PLL1_SetQ(MYNEWT_VAL_STM32_CLOCK_PLL1_PLLQ); + LL_RCC_PLL1_SetR(MYNEWT_VAL_STM32_CLOCK_PLL1_PLLR); + if (MYNEWT_VAL_STM32_CLOCK_PLL1_PLLFRACN) { + LL_RCC_PLL1_SetFRACN(MYNEWT_VAL_STM32_CLOCK_PLL1_PLLFRACN); + } + LL_RCC_PLL1_SetVCOInputRange(MYNEWT_VAL_STM32_CLOCK_PLL1_RGE); + LL_RCC_PLL1_Enable(); + LL_RCC_PLL1P_Enable(); + LL_RCC_PLL1Q_Enable(); + } + + BUSY_LOOP(PLL_VAL(PLL2, SOURCE) == LL_RCC_PLL1SOURCE_HSE && !LL_RCC_HSE_IsReady()); + BUSY_LOOP(PLL_VAL(PLL2, SOURCE) == LL_RCC_PLL1SOURCE_HSI && !LL_RCC_HSI_IsReady()); + BUSY_LOOP(PLL_VAL(PLL2, SOURCE) == LL_RCC_PLL1SOURCE_CSI && !LL_RCC_CSI_IsReady()); + if (PLL_ON(PLL2)) { + LL_RCC_PLL2_SetSource(MYNEWT_VAL_STM32_CLOCK_PLL2_SOURCE); + LL_RCC_PLL2_SetM(MYNEWT_VAL_STM32_CLOCK_PLL2_PLLM); + LL_RCC_PLL2_SetN(MYNEWT_VAL_STM32_CLOCK_PLL2_PLLN); + LL_RCC_PLL2_SetP(MYNEWT_VAL_STM32_CLOCK_PLL2_PLLP); + LL_RCC_PLL2_SetQ(MYNEWT_VAL_STM32_CLOCK_PLL2_PLLQ); + LL_RCC_PLL2_SetR(MYNEWT_VAL_STM32_CLOCK_PLL2_PLLR); + if (MYNEWT_VAL_STM32_CLOCK_PLL2_PLLFRACN) { + LL_RCC_PLL2_SetFRACN(MYNEWT_VAL_STM32_CLOCK_PLL2_PLLFRACN); + } + LL_RCC_PLL2_SetVCOInputRange(MYNEWT_VAL_STM32_CLOCK_PLL2_RGE); + LL_RCC_PLL2_Enable(); + LL_RCC_PLL2P_Enable(); + LL_RCC_PLL2Q_Enable(); + } + +#if RCC_CR_PLL3ON + BUSY_LOOP(PLL_VAL(PLL3, SOURCE) == LL_RCC_PLL1SOURCE_HSE && !LL_RCC_HSE_IsReady()); + BUSY_LOOP(PLL_VAL(PLL3, SOURCE) == LL_RCC_PLL1SOURCE_HSI && !LL_RCC_HSI_IsReady()); + BUSY_LOOP(PLL_VAL(PLL3, SOURCE) == LL_RCC_PLL1SOURCE_CSI && !LL_RCC_CSI_IsReady()); + if (PLL_ON(PLL3)) { + LL_RCC_PLL3_SetSource(MYNEWT_VAL_STM32_CLOCK_PLL3_SOURCE); + LL_RCC_PLL3_SetM(MYNEWT_VAL_STM32_CLOCK_PLL3_PLLM); + LL_RCC_PLL3_SetN(MYNEWT_VAL_STM32_CLOCK_PLL3_PLLN); + LL_RCC_PLL3_SetP(MYNEWT_VAL_STM32_CLOCK_PLL3_PLLP); + LL_RCC_PLL3_SetQ(MYNEWT_VAL_STM32_CLOCK_PLL3_PLLQ); + LL_RCC_PLL3_SetR(MYNEWT_VAL_STM32_CLOCK_PLL3_PLLR); + if (MYNEWT_VAL_STM32_CLOCK_PLL3_PLLFRACN) { + LL_RCC_PLL3_SetFRACN(MYNEWT_VAL_STM32_CLOCK_PLL3_PLLFRACN); + } + LL_RCC_PLL3_SetVCOInputRange(MYNEWT_VAL_STM32_CLOCK_PLL3_RGE); + LL_RCC_PLL3_Enable(); + LL_RCC_PLL3P_Enable(); + LL_RCC_PLL3Q_Enable(); + } +#endif + BUSY_LOOP(MYNEWT_VAL_STM32_CLOCK_SYSCLK_SOURCE == LL_RCC_SYS_CLKSOURCE_HSI && + !LL_RCC_HSI_IsReady()); + BUSY_LOOP(MYNEWT_VAL_STM32_CLOCK_SYSCLK_SOURCE == LL_RCC_SYS_CLKSOURCE_HSE && + !LL_RCC_HSE_IsReady()); + BUSY_LOOP(MYNEWT_VAL_STM32_CLOCK_SYSCLK_SOURCE == LL_RCC_SYS_CLKSOURCE_CSI && + !LL_RCC_CSI_IsReady()); + BUSY_LOOP(MYNEWT_VAL_STM32_CLOCK_SYSCLK_SOURCE == LL_RCC_SYS_CLKSOURCE_PLL1 && + !LL_RCC_PLL1_IsReady()); + LL_RCC_SetSysClkSource(MYNEWT_VAL_STM32_CLOCK_SYSCLK_SOURCE); +} + +#endif diff --git a/hw/mcu/stm/stm32h5xx/src/hal_flash.c b/hw/mcu/stm/stm32h5xx/src/hal_flash.c new file mode 100644 index 000000000..2e023d966 --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/src/hal_flash.c @@ -0,0 +1,55 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include <syscfg/syscfg.h> +#include <mcu/stm32_hal.h> +#include "hal/hal_flash_int.h" + +#define STM32_FLASH_SIZE (MYNEWT_VAL_STM32_FLASH_SIZE_KB * 1024) + +int +stm32_mcu_flash_erase_sector(const struct hal_flash *dev, uint32_t sector_address) +{ + FLASH_EraseInitTypeDef eraseinit; + uint32_t PageError; + HAL_StatusTypeDef rc; + + (void)PageError; + + if (!(sector_address & (FLASH_SECTOR_SIZE - 1))) { + eraseinit.TypeErase = FLASH_TYPEERASE_SECTORS; +#ifdef FLASH_BANK_2 + if ((sector_address - dev->hf_base_addr) < (STM32_FLASH_SIZE / 2)) { + eraseinit.Banks = FLASH_BANK_1; + } else { + eraseinit.Banks = FLASH_BANK_2; + } +#else + eraseinit.Banks = FLASH_BANK_1; +#endif + eraseinit.Sector = ((sector_address - dev->hf_base_addr) / FLASH_SECTOR_SIZE) % FLASH_SECTOR_NB; + eraseinit.NbSectors = 1; + rc = HAL_FLASHEx_Erase(&eraseinit, &PageError); + if (rc == HAL_OK) { + return 0; + } + } + + return -1; +} diff --git a/hw/mcu/stm/stm32h5xx/src/hal_reset_cause.c b/hw/mcu/stm/stm32h5xx/src/hal_reset_cause.c new file mode 100644 index 000000000..4b366b39c --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/src/hal_reset_cause.c @@ -0,0 +1,47 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ +#include <hal/hal_system.h> + +#include <stm32h5xx_hal_def.h> + +enum hal_reset_reason +hal_reset_cause(void) +{ + static enum hal_reset_reason reason; + uint32_t reg; + + if (reason) { + return reason; + } + + reg = RCC->RSR; + if (reg & RCC_RSR_WWDGRSTF || reg & RCC_RSR_IWDGRSTF) { + reason = HAL_RESET_WATCHDOG; + } else if (reg & RCC_RSR_SFTRSTF) { + reason = HAL_RESET_SOFT; + } else if (reg & RCC_RSR_PINRSTF) { + reason = HAL_RESET_PIN; + } else if (reg & RCC_RSR_BORRSTF) { + reason = HAL_RESET_BROWNOUT; + } else { + reason = HAL_RESET_POR; + } + RCC->RSR |= RCC_RSR_RMVF; + return reason; +} diff --git a/hw/mcu/stm/stm32h5xx/src/hal_system_init.c b/hw/mcu/stm/stm32h5xx/src/hal_system_init.c new file mode 100644 index 000000000..2807e15d3 --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/src/hal_system_init.c @@ -0,0 +1,57 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include "os/mynewt.h" +#include "mcu/stm32_hal.h" +#include <hal/hal_system.h> + +void SystemClock_Config(void); + +void +hal_system_init(void) +{ + /* Configure System Clock */ + SystemClock_Config(); + + /* Update SystemCoreClock global variable */ + SystemCoreClockUpdate(); + + /* Relocate the vector table */ + NVIC_Relocate(); + + if (MYNEWT_VAL_STM32_FLASH_PREFETCH_ENABLE) { + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); + } else { + __HAL_FLASH_PREFETCH_BUFFER_DISABLE(); + } + + if (MYNEWT_VAL_STM32_ENABLE_ICACHE) { + HAL_ICACHE_Enable(); + } + +#ifdef DCACHE1 + if (MYNEWT_VAL_STM32_ENABLE_DCACHE) { + DCACHE_HandleTypeDef cache = { + .Instance = DCACHE1, + .Init.ReadBurstType = DCACHE_READ_BURST_WRAP, + }; + HAL_DCACHE_Init(&cache); + } +#endif +} diff --git a/hw/mcu/stm/stm32h5xx/src/hal_timer_freq.c b/hw/mcu/stm/stm32h5xx/src/hal_timer_freq.c new file mode 100644 index 000000000..42f13e0ec --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/src/hal_timer_freq.c @@ -0,0 +1,129 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include "os/mynewt.h" + +#include <assert.h> +#include <inttypes.h> +#include <stm32h5xx_hal_rcc.h> + +static uint32_t +stm32_hal_timer_abp_clk_div(uint32_t divider) +{ + switch (divider) { + case RCC_HCLK_DIV1: + return 1; + case RCC_HCLK_DIV2: + return 2; + case RCC_HCLK_DIV4: + return 4; + case RCC_HCLK_DIV8: + return 8; + case RCC_HCLK_DIV16: + return 16; + } + return 0; +} + +uint32_t +stm32_hal_timer_get_freq(void *timx) +{ + uintptr_t regs = (uintptr_t)timx; + RCC_ClkInitTypeDef clocks; + uint32_t flashLatency; + uint32_t freq = 0; + uint32_t div = 0; + + HAL_RCC_GetClockConfig(&clocks, &flashLatency); + + switch (regs) { +#ifdef TIM1 + case (uintptr_t)TIM1: +#endif +#ifdef TIM8 + case (uintptr_t)TIM8: +#endif +#ifdef TIM15 + case (uintptr_t)TIM15: +#endif +#ifdef TIM16 + case (uintptr_t)TIM16: +#endif +#ifdef TIM17 + case (uintptr_t)TIM17: +#endif + freq = HAL_RCC_GetPCLK2Freq(); + div = stm32_hal_timer_abp_clk_div(clocks.APB2CLKDivider); + break; + +#ifdef TIM2 + case (uintptr_t)TIM2: +#endif +#ifdef TIM3 + case (uintptr_t)TIM3: +#endif +#ifdef TIM4 + case (uintptr_t)TIM4: +#endif +#ifdef TIM5 + case (uintptr_t)TIM5: +#endif +#ifdef TIM6 + case (uintptr_t)TIM6: +#endif +#ifdef TIM7 + case (uintptr_t)TIM7: +#endif + +#ifdef TIM12 + case (uintptr_t)TIM12: +#endif +#ifdef TIM13 + case (uintptr_t)TIM13: +#endif +#ifdef TIM14 + case (uintptr_t)TIM14: +#endif +#ifdef TIM23 + case (uintptr_t)TIM23: +#endif +#ifdef TIM24 + case (uintptr_t)TIM24: +#endif + freq = HAL_RCC_GetPCLK1Freq(); + div = stm32_hal_timer_abp_clk_div(clocks.APB1CLKDivider); + break; + + default: + assert(0); + return 0; + } + + if (RCC_TIMPRES_ACTIVATED == READ_BIT(RCC->CFGR1, RCC_CFGR1_TIMPRE)) { + if (div > 2) { + return freq * 4; + } + return freq * div; + } + + if (div > 1) { + return freq * 2; + } + return freq; +} diff --git a/hw/mcu/stm/stm32h5xx/src/system_stm32h5xx.c b/hw/mcu/stm/stm32h5xx/src/system_stm32h5xx.c new file mode 100644 index 000000000..d4ea96004 --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/src/system_stm32h5xx.c @@ -0,0 +1,403 @@ +/** + ****************************************************************************** + * @file system_stm32h5xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32h5xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the HSI (64 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32h5xx.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | HSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 64000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 64000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB3 Prescaler | 1 + *----------------------------------------------------------------------------- + * HSI Division factor | 1 + *----------------------------------------------------------------------------- + * PLL1_SRC | No clock + *----------------------------------------------------------------------------- + * PLL1_M | Prescaler disabled + *----------------------------------------------------------------------------- + * PLL1_N | 129 + *----------------------------------------------------------------------------- + * PLL1_P | 2 + *----------------------------------------------------------------------------- + * PLL1_Q | 2 + *----------------------------------------------------------------------------- + * PLL1_R | 2 + *----------------------------------------------------------------------------- + * PLL1_FRACN | 0 + *----------------------------------------------------------------------------- + * PLL2_SRC | No clock + *----------------------------------------------------------------------------- + * PLL2_M | Prescaler disabled + *----------------------------------------------------------------------------- + * PLL2_N | 129 + *----------------------------------------------------------------------------- + * PLL2_P | 2 + *----------------------------------------------------------------------------- + * PLL2_Q | 2 + *----------------------------------------------------------------------------- + * PLL2_R | 2 + *----------------------------------------------------------------------------- + * PLL2_FRACN | 0 + *----------------------------------------------------------------------------- + * PLL3_SRC | No clock + *----------------------------------------------------------------------------- + * PLL3_M | Prescaler disabled + *----------------------------------------------------------------------------- + * PLL3_N | 129 + *----------------------------------------------------------------------------- + * PLL3_P | 2 + *----------------------------------------------------------------------------- + * PLL3_Q | 2 + *----------------------------------------------------------------------------- + * PLL3_R | 2 + *----------------------------------------------------------------------------- + * PLL3_FRACN | 0 + *----------------------------------------------------------------------------- + *============================================================================= + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup STM32H5xx_system + * @{ + */ + +/** @addtogroup STM32H5xx_System_Private_Includes + * @{ + */ + +#include "stm32h5xx.h" + +/** + * @} + */ + +/** @addtogroup STM32H5xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H5xx_System_Private_Defines + * @{ + */ + +#if !defined (HSE_VALUE) + #define HSE_VALUE (25000000UL) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (CSI_VALUE) + #define CSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* CSI_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE (64000000UL) /*!< Value of the Internal oscillator in Hz */ +#endif /* HSI_VALUE */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#if !defined(VECT_TAB_OFFSET) +#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_OFFSET */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32H5xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H5xx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 64000000U; + + const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; + const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; +/** + * @} + */ + +/** @addtogroup STM32H5xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H5xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ + +void SystemInit(void) +{ + uint32_t reg_opsr; + + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ + #endif + + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit while preserving the current HSIDIV value*/ + RCC->CR = (RCC->CR & RCC_CR_HSIDIV_Msk) | RCC_CR_HSION; + + /* Reset CFGR register */ + RCC->CFGR1 = 0U; + RCC->CFGR2 = 0U; + + /* Reset HSEON, HSECSSON, HSEBYP, HSEEXT, HSIDIV, HSIKERON, CSION, CSIKERON, HSI48 and PLLxON bits */ +#if defined(RCC_CR_PLL3ON) + RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_HSECSSON | RCC_CR_HSEBYP | RCC_CR_HSEEXT | RCC_CR_HSIKERON | \ + RCC_CR_CSION | RCC_CR_CSIKERON |RCC_CR_HSI48ON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON); +#else + RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_HSECSSON | RCC_CR_HSEBYP | RCC_CR_HSEEXT | RCC_CR_HSIKERON | \ + RCC_CR_CSION | RCC_CR_CSIKERON |RCC_CR_HSI48ON | RCC_CR_PLL1ON | RCC_CR_PLL2ON); +#endif + + /* Reset PLLxCFGR register */ + RCC->PLL1CFGR = 0U; + RCC->PLL2CFGR = 0U; +#if defined(RCC_CR_PLL3ON) + RCC->PLL3CFGR = 0U; +#endif /* RCC_CR_PLL3ON */ + + /* Reset PLL1DIVR register */ + RCC->PLL1DIVR = 0x01010280U; + /* Reset PLL1FRACR register */ + RCC->PLL1FRACR = 0x00000000U; + /* Reset PLL2DIVR register */ + RCC->PLL2DIVR = 0x01010280U; + /* Reset PLL2FRACR register */ + RCC->PLL2FRACR = 0x00000000U; +#if defined(RCC_CR_PLL3ON) + /* Reset PLL3DIVR register */ + RCC->PLL3DIVR = 0x01010280U; + /* Reset PLL3FRACR register */ + RCC->PLL3FRACR = 0x00000000U; +#endif /* RCC_CR_PLL3ON */ + + /* Reset HSEBYP bit */ + RCC->CR &= ~(RCC_CR_HSEBYP); + + /* Disable all interrupts */ + RCC->CIER = 0U; + + /* Configure the Vector Table location add offset address ------------------*/ + #ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ + #else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ + #endif /* VECT_TAB_SRAM */ + + /* Check OPSR register to verify if there is an ongoing swap or option bytes update interrupted by a reset */ + reg_opsr = FLASH->OPSR & FLASH_OPSR_CODE_OP; + if ((reg_opsr == FLASH_OPSR_CODE_OP) || (reg_opsr == (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_1))) + { + /* Check FLASH Option Control Register access */ + if ((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != 0U) + { + /* Authorizes the Option Byte registers programming */ + FLASH->OPTKEYR = 0x08192A3BU; + FLASH->OPTKEYR = 0x4C5D6E7FU; + } + /* Launch the option bytes change operation */ + FLASH->OPTCR |= FLASH_OPTCR_OPTSTART; + + /* Lock the FLASH Option Control Register access */ + FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK; + } +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*) + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(**) or CSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) CSI_VALUE is a constant defined in stm32h5xx_hal.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSI_VALUE is a constant defined in stm32h5xx_hal.h file (default value + * 64 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32h5xx_hal.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp; + float_t fracn1, pllvco; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR1 & RCC_CFGR1_SWS) + { + case 0x00UL: /* HSI used as system clock source */ + SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); + break; + + case 0x08UL: /* CSI used as system clock source */ + SystemCoreClock = CSI_VALUE; + break; + + case 0x10UL: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + + case 0x18UL: /* PLL1 used as system clock source */ + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC); + pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos); + pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN)>>RCC_PLL1CFGR_PLL1FRACEN_Pos); + fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN)>> RCC_PLL1FRACR_PLL1FRACN_Pos)); + + switch (pllsource) + { + case 0x01UL: /* HSI used as PLL clock source */ + hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; + pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + + case 0x02UL: /* CSI used as PLL clock source */ + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + + case 0x03UL: /* HSE used as PLL clock source */ + pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + + default: /* No clock sent to PLL*/ + pllvco = (float_t) 0U; + break; + } + + pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1P) >>RCC_PLL1DIVR_PLL1P_Pos) + 1U ) ; + SystemCoreClock = (uint32_t)(float_t)(pllvco/(float_t)pllp); + + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/hw/mcu/stm/stm32h5xx/syscfg.yml b/hw/mcu/stm/stm32h5xx/syscfg.yml new file mode 100644 index 000000000..c5293973e --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/syscfg.yml @@ -0,0 +1,288 @@ +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +syscfg.defs: + MCU_FLASH_MIN_WRITE_SIZE: + description: > + Specifies the required alignment for internal flash writes. + Used internally by the newt tool. + value: 16 + + MCU_STM32H5: + description: MCUs are of STM32H5xx family + value: 1 + MCU_TARGET: + description: Specifies target MCU, shall be set by BSP. + value: + restrictions: $notnull + choices: + - STM32H503 + - STM32H523 + - STM32H533 + - STM32H562 + - STM32H563 + - STM32H573 + + STM32_CLOCK_VOLTAGESCALING_CONFIG: + description: Voltage scale + value: 0 + + STM32_CLOCK_LSI: + description: Enable low-speed internal clock source + value: 1 + + STM32_CLOCK_LSE: + description: Enable low-speed external clock source (aka RTC xtal) + value: 0 + + STM32_CLOCK_LSE_BYPASS: + description: 0 for 32768 xtal; 1 for input clock + value: 0 + + STM32_CLOCK_HSE: + description: Enable high-speed external clock source + value: 0 + + STM32_CLOCK_HSE_BYPASS: + description: 0 for xtal; 1 for input clock + value: 0 + + STM32_CLOCK_HSI: + description: Enable high-speed internal clock source + value: 1 + + STM32_CLOCK_HSIDIV: + description: HSI divider LL_RCC_HSI_DIV_x where x=(1,2,4,8) + value: LL_RCC_HSI_DIV_1 + + STM32_CLOCK_HSI_CALIBRATION: + description: HSI calibration value + value: 'RCC_HSICALIBRATION_DEFAULT' + + STM32_CLOCK_HSI48: + description: Enable high-speed 48MHz internal clock source + value: 1 + + STM32_CLOCK_USBSEL: + description: > + Select USB clock source. + 0 - disabled + Other acceptable values + RCC_USBCLKSOURCE_PLL1Q, RCC_USBCLKSOURCE_PLL2Q, RCC_USBCLKSOURCE_PLL3Q, RCC_USBCLKSOURCE_HSI48 + value: RCC_USBCLKSOURCE_HSI48 + STM32_CLOCK_SYSCLK_SOURCE: + description: > + System clock selection (LL_RCC_SYS_CLKSOURCE_HSI, LL_RCC_SYS_CLKSOURCE_CSI, LL_RCC_SYS_CLKSOURCE_HSE + LL_RCC_SYS_CLKSOURCE_PLL1) + value: LL_RCC_SYS_CLKSOURCE_HSI + STM32_CLOCK_PLL_PLLM: + description: PLL config M parameter + value: 0 + + STM32_CLOCK_PLL_PLLN: + description: PLL config N parameter + value: 0 + + STM32_CLOCK_PLL_PLLP: + description: PLL config P parameter + value: 0 + + STM32_CLOCK_PLL_PLLQ: + description: PLL config Q parameter + value: 0 + + STM32_CLOCK_PLL_PLLR: + description: PLL config R parameter + value: 0 + + STM32_CLOCK_PLL1: + description: Enable PLL1 + value: 0 + + STM32_CLOCK_PLL1_SOURCE: + description: PLL1 source + value: LL_RCC_PLL1SOURCE_HSI + + STM32_CLOCK_PLL1_PLLM: + description: PLL1 config M parameter + value: 1 + + STM32_CLOCK_PLL1_PLLN: + description: PLL1 config N parameter + value: 0 + + STM32_CLOCK_PLL1_PLLFRACN: + description: PLL1FRACN parameter + value: 0 + + STM32_CLOCK_PLL1_PLLP: + description: PLL1 config P parameter + value: 0 + + STM32_CLOCK_PLL1_PLLQ: + description: PLL1 config Q parameter + value: 0 + + STM32_CLOCK_PLL1_PLLR: + description: PLL1 config R parameter + value: 0 + + STM32_CLOCK_PLL1_RGE: + description: PLL input frequency range + value: RCC_PLL1_VCIRANGE_0 + + STM32_CLOCK_PLL2: + description: Enable PLL2 + value: 0 + + STM32_CLOCK_PLL2_SOURCE: + description: PLL2 source + value: LL_RCC_PLL2SOURCE_HSI + + STM32_CLOCK_PLL2_PLLM: + description: PLL2 config M parameter + value: 1 + + STM32_CLOCK_PLL2_PLLN: + description: PLL2 config N parameter + value: 0 + + STM32_CLOCK_PLL2_PLLFRACN: + description: PLL2FRACN parameter + value: 0 + + STM32_CLOCK_PLL2_PLLP: + description: PLL2 config P parameter + value: 0 + + STM32_CLOCK_PLL2_PLLQ: + description: PLL2 config Q parameter + value: 0 + + STM32_CLOCK_PLL2_PLLR: + description: PLL2 config R parameter + value: 0 + + STM32_CLOCK_PLL2_RGE: + description: PLL input frequency range + value: 0 + + STM32_CLOCK_PLL3: + description: Enable PLL3 + value: 0 + + STM32_CLOCK_PLL3_SOURCE: + description: PLL3 source + value: LL_RCC_PLL3SOURCE_HSI + + STM32_CLOCK_PLL3_PLLM: + description: PLL3 config M parameter + value: 1 + + STM32_CLOCK_PLL3_PLLN: + description: PLL3 config N parameter + value: 0 + + STM32_CLOCK_PLL3_PLLFRACN: + description: PLL3FRACN parameter + value: 0 + + STM32_CLOCK_PLL3_PLLP: + description: PLL3 config P parameter + value: 0 + + STM32_CLOCK_PLL3_PLLQ: + description: PLL3 config Q parameter + value: 0 + + STM32_CLOCK_PLL3_PLLR: + description: PLL3 config R parameter + value: 0 + + STM32_CLOCK_PLL3_RGE: + description: PLL input frequency range + value: 0 + + STM32_CLOCK_AHB_DIVIDER: + description: AHB prescaler + value: 0 + + STM32_CLOCK_APB1_DIVIDER: + description: APB low-speed prescaler + value: 0 + + STM32_CLOCK_APB2_DIVIDER: + description: APB high-speed prescaler + value: 0 + + STM32_CLOCK_APB3_DIVIDER: + description: APB low-speed prescaler + value: 0 + + STM32_CLOCK_APB4_DIVIDER: + description: APB high-speed prescaler + value: 0 + + STM32_FLASH_LATENCY: + description: Number of wait-states + value: 0 + + STM32_ENABLE_ICACHE: + description: Enable instruction caching + value: 1 + + STM32_ENABLE_DCACHE: + description: Enable instruction caching + value: 1 + + STM32_FLASH_PREFETCH_ENABLE: + description: Enable pre-fetch of instructions (when latency > 0) + value: 1 + + STM32_HAL_SPI_HAS_FIFO: + description: This MCU has a SPI with FIFO + value: 1 + + STM32_HAL_I2C_HAS_CLOCKSPEED: + description: This MCU's I2C has no clock speed register (has TIMINGR) + value: 0 + + STM32_HAL_UART_HAS_SR: + description: This MCU's UART uses ISR register (not SR) for status. + value: 0 + + MCU_FLASH_ERASED_VAL: + description: Value read from erased flash. + value: 0xff + +syscfg.vals: + MCU_RAM_START: 0x20000000 + +syscfg.vals.'MCU_TARGET=="STM32H503"': + MCU_RAM_SIZE: 0x8000 +syscfg.vals.'MCU_TARGET=="STM32H523"': + MCU_RAM_SIZE: 0x2B000 +syscfg.vals.'MCU_TARGET=="STM32H533"': + MCU_RAM_SIZE: 0x2B000 +syscfg.vals.'MCU_TARGET=="STM32H562"': + MCU_RAM_SIZE: 0xA0000 +syscfg.vals.'MCU_TARGET=="STM32H563"': + MCU_RAM_SIZE: 0xA0000 + +syscfg.vals.STM32_CLOCK_HSI48: + STM32_CLOCK_USBSEL: RCC_USBCLKSOURCE_HSI48
