mid merge with dev branch, uart still needs work
Project: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/repo Commit: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/commit/0ef64aa7 Tree: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/tree/0ef64aa7 Diff: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/diff/0ef64aa7 Branch: refs/heads/develop Commit: 0ef64aa7f477d0804d68bb0253ad444be35b9d34 Parents: 8d6b13e Author: julian <[email protected]> Authored: Tue Oct 18 18:08:09 2016 +0100 Committer: julian <[email protected]> Committed: Mon Nov 21 11:07:25 2016 +0000 ---------------------------------------------------------------------- compiler/mips/pkg.yml | 2 +- compiler/sim-mips/pkg.yml | 1 + hw/bsp/ci40/bsp.yml | 54 +++ hw/bsp/ci40/include/bsp/bsp.h | 2 +- hw/bsp/ci40/pkg.yml | 4 - hw/bsp/ci40/src/os_bsp.c | 76 +-- .../uart/uart_hal/src/uart_hal_BACKUP_19438.c | 143 ++++++ .../uart/uart_hal/src/uart_hal_BASE_19438.c | 143 ++++++ .../uart/uart_hal/src/uart_hal_LOCAL_19438.c | 143 ++++++ .../uart/uart_hal/src/uart_hal_REMOTE_19438.c | 143 ++++++ hw/mcu/mips/danube/src/hal_uart.c | 6 + hw/mcu/mips/danube/src/hal_watchdog.c | 39 ++ kernel/os/include/os/arch/mips/os/os_arch.h | 80 ++++ kernel/os/include/os/arch/sim-mips/os/os_arch.h | 74 +++ kernel/os/src/arch/mips/asm/ctx.S | 197 ++++++++ kernel/os/src/arch/mips/asm/excpt_isr.S | 100 ++++ kernel/os/src/arch/mips/os_arch_mips.c | 185 ++++++++ kernel/os/src/arch/mips/os_fault.c | 123 +++++ kernel/os/src/arch/sim-mips/os_arch_sim.c | 463 +++++++++++++++++++ .../os/src/arch/sim-mips/os_arch_stack_frame.s | 65 +++ kernel/os/src/arch/sim-mips/os_fault.c | 34 ++ libs/os/include/os/arch/mips/os/os_arch.h | 80 ---- libs/os/include/os/arch/sim-mips/os/os_arch.h | 74 --- libs/os/src/arch/mips/asm/ctx.S | 197 -------- libs/os/src/arch/mips/asm/excpt_isr.S | 100 ---- libs/os/src/arch/mips/os_arch_mips.c | 185 -------- libs/os/src/arch/mips/os_fault.c | 123 ----- libs/os/src/arch/sim-mips/os_arch_sim.c | 463 ------------------- libs/os/src/arch/sim-mips/os_arch_stack_frame.s | 65 --- libs/os/src/arch/sim-mips/os_fault.c | 34 -- 30 files changed, 2017 insertions(+), 1381 deletions(-) ---------------------------------------------------------------------- http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0ef64aa7/compiler/mips/pkg.yml ---------------------------------------------------------------------- diff --git a/compiler/mips/pkg.yml b/compiler/mips/pkg.yml index 2b72664..0fd6d89 100644 --- a/compiler/mips/pkg.yml +++ b/compiler/mips/pkg.yml @@ -23,6 +23,6 @@ pkg.description: Compiler definition for mips-elf gcc compiler. pkg.author: "Apache Mynewt <[email protected]>" pkg.homepage: "http://mynewt.apache.org/"; pkg.keywords: - - sim + - mips - compiler - gcc http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0ef64aa7/compiler/sim-mips/pkg.yml ---------------------------------------------------------------------- diff --git a/compiler/sim-mips/pkg.yml b/compiler/sim-mips/pkg.yml index 0a8753c..752529e 100644 --- a/compiler/sim-mips/pkg.yml +++ b/compiler/sim-mips/pkg.yml @@ -23,6 +23,7 @@ pkg.description: Compiler definition for Linux user mips gcc compiler. pkg.author: "Apache Mynewt <[email protected]>" pkg.homepage: "http://mynewt.apache.org/"; pkg.keywords: + - mips - sim - compiler - gcc http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0ef64aa7/hw/bsp/ci40/bsp.yml ---------------------------------------------------------------------- diff --git a/hw/bsp/ci40/bsp.yml b/hw/bsp/ci40/bsp.yml new file mode 100644 index 0000000..e45db11 --- /dev/null +++ b/hw/bsp/ci40/bsp.yml @@ -0,0 +1,54 @@ +# +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +bsp.arch: mips +bsp.compiler: compiler/mips +bsp.linkerscript: "uhi32.ld" + +bsp.flash_map: + areas: + # System areas. + FLASH_AREA_BOOTLOADER: + device: 0 + offset: 0x00000000 + size: 0kB + FLASH_AREA_IMAGE_0: + device: 0 + offset: 0x00000000 + size: 0kB + FLASH_AREA_IMAGE_1: + device: 0 + offset: 0x00000000 + size: 0kB + FLASH_AREA_IMAGE_SCRATCH: + device: 0 + offset: 0x00000000 + size: 0kB + + # User areas. + FLASH_AREA_REBOOT_LOG: + user_id: 0 + device: 0 + offset: 0x00000000 + size: 0kB + FLASH_AREA_NFFS: + user_id: 1 + device: 0 + offset: 0x00000000 + size: 0kB \ No newline at end of file http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0ef64aa7/hw/bsp/ci40/include/bsp/bsp.h ---------------------------------------------------------------------- diff --git a/hw/bsp/ci40/include/bsp/bsp.h b/hw/bsp/ci40/include/bsp/bsp.h index f317e1e..3f9e5a9 100644 --- a/hw/bsp/ci40/include/bsp/bsp.h +++ b/hw/bsp/ci40/include/bsp/bsp.h @@ -44,7 +44,7 @@ extern uint8_t _ccram_start; /* UART */ #define UART_CNT 2 -#define CONSOLE_UART 1 +#define CONSOLE_UART "uart1" #define NFFS_AREA_MAX (8) http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0ef64aa7/hw/bsp/ci40/pkg.yml ---------------------------------------------------------------------- diff --git a/hw/bsp/ci40/pkg.yml b/hw/bsp/ci40/pkg.yml index 167b7f1..eba5614 100644 --- a/hw/bsp/ci40/pkg.yml +++ b/hw/bsp/ci40/pkg.yml @@ -28,10 +28,6 @@ pkg.keywords: - danube - mips -pkg.arch: mips -pkg.compiler: compiler/mips -pkg.linkerscript: "uhi32.ld" pkg.cflags: pkg.deps: - hw/mcu/mips/danube - - libs/baselibc http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0ef64aa7/hw/bsp/ci40/src/os_bsp.c ---------------------------------------------------------------------- diff --git a/hw/bsp/ci40/src/os_bsp.c b/hw/bsp/ci40/src/os_bsp.c index c7e40a0..35e4b5a 100644 --- a/hw/bsp/ci40/src/os_bsp.c +++ b/hw/bsp/ci40/src/os_bsp.c @@ -17,65 +17,33 @@ * under the License. */ -/* - * XXXX for now have this here. - */ -#include <hal/flash_map.h> -#include <hal/hal_bsp.h> +#include "hal/hal_bsp.h" +#include "syscfg/syscfg.h" +#include "uart/uart.h" +#include "uart_hal/uart_hal.h" -static struct flash_area bsp_flash_areas[] = { - [FLASH_AREA_BOOTLOADER] = { - .fa_flash_id = 0, /* internal flash */ - .fa_off = 0x08000000, /* beginning */ - .fa_size = (32 * 1024) - }, - /* 2 * 16K and 1*64K sectors here */ - [FLASH_AREA_IMAGE_0] = { - .fa_flash_id = 0, - .fa_off = 0x08020000, - .fa_size = (384 * 1024) - }, - [FLASH_AREA_IMAGE_1] = { - .fa_flash_id = 0, - .fa_off = 0x08080000, - .fa_size = (384 * 1024) - }, - [FLASH_AREA_IMAGE_SCRATCH] = { - .fa_flash_id = 0, - .fa_off = 0x080e0000, - .fa_size = (128 * 1024) - }, - [FLASH_AREA_NFFS] = { - .fa_flash_id = 0, - .fa_off = 0x08008000, - .fa_size = (32 * 1024) - } -}; +#include <assert.h> -void _close(int fd); +#if MYNEWT_VAL(UART_0) +static struct uart_dev os_bsp_uart0; +#endif -/* - * Returns the flash map slot where the currently active image is located. - * If executing from internal flash from fixed location, that slot would - * be easy to find. - * If images are in external flash, and copied to RAM for execution, then - * this routine would have to figure out which one of those slots is being - * used. - */ -int -bsp_imgr_current_slot(void) -{ - return FLASH_AREA_IMAGE_0; -} +#if MYNEWT_VAL(UART_1) +static struct uart_dev os_bsp_uart1; +#endif + +void _close(int fd); void bsp_init(void) { - /* - * XXX this reference is here to keep this function in. - */ - _sbrk(0); - //_close(0); - flash_area_init(bsp_flash_areas, - sizeof(bsp_flash_areas) / sizeof(bsp_flash_areas[0])); + #if MYNEWT_VAL(UART_0) + assert(os_dev_create((struct os_dev *) &os_bsp_uart0, "uart0", + OS_DEV_INIT_PRIMARY, 0, uart_hal_init, 0) == 0); + #endif + + #if MYNEWT_VAL(UART_1) + assert(os_dev_create((struct os_dev *) &os_bsp_uart1, "uart1", + OS_DEV_INIT_PRIMARY, 0, uart_hal_init, 0) == 0); + #endif } http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0ef64aa7/hw/drivers/uart/uart_hal/src/uart_hal_BACKUP_19438.c ---------------------------------------------------------------------- diff --git a/hw/drivers/uart/uart_hal/src/uart_hal_BACKUP_19438.c b/hw/drivers/uart/uart_hal/src/uart_hal_BACKUP_19438.c new file mode 100644 index 0000000..940990a --- /dev/null +++ b/hw/drivers/uart/uart_hal/src/uart_hal_BACKUP_19438.c @@ -0,0 +1,143 @@ +/** + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include <ctype.h> +#include <assert.h> +#include <string.h> + +#include <os/os.h> +#include <os/os_dev.h> +#include <hal/hal_uart.h> + +#include <uart/uart.h> + +#include "uart_hal/uart_hal.h" + +struct uart_hal_priv { + int unit; +}; + +static void +uart_hal_start_tx(struct uart_dev *dev) +{ + struct uart_hal_priv *priv; + + priv = dev->ud_priv; + assert(priv); + + hal_uart_start_tx(priv->unit); +} + +static void +uart_hal_start_rx(struct uart_dev *dev) +{ + struct uart_hal_priv *priv; + + priv = dev->ud_priv; + + hal_uart_start_rx(priv->unit); +} + +static void +uart_hal_blocking_tx(struct uart_dev *dev, uint8_t byte) +{ + struct uart_hal_priv *priv; + + priv = dev->ud_priv; + + hal_uart_blocking_tx(priv->unit, byte); +} + +static int +uart_hal_open(struct os_dev *odev, uint32_t wait, void *arg) +{ + struct uart_hal_priv *priv; + struct uart_conf *uc; + int rc; + + priv = ((struct uart_dev *)odev)->ud_priv; + + uc = (struct uart_conf *)arg; + if (!uc) { + return OS_EINVAL; + } + if (odev->od_flags & OS_DEV_F_STATUS_OPEN) { + return OS_EBUSY; + } + hal_uart_init_cbs(priv->unit, uc->uc_tx_char, uc->uc_tx_done, + uc->uc_rx_char, uc->uc_cb_arg); + + rc = hal_uart_config(priv->unit, uc->uc_speed, uc->uc_databits, + uc->uc_stopbits, uc->uc_parity, uc->uc_flow_ctl); + if (rc) { + return OS_EINVAL; + } + return OS_OK; +} + +static int +uart_hal_close(struct os_dev *odev) +{ + struct uart_hal_priv *priv; + int rc; + + priv = ((struct uart_dev *)odev)->ud_priv; + + rc = hal_uart_close(priv->unit); + if (rc) { + return OS_EINVAL; + } + return OS_OK; +} + +/* + * Arg points to BSP specific UART configuration. + */ +int +uart_hal_init(struct os_dev *odev, void *arg) +{ + struct uart_dev *dev; + struct uart_hal_priv *priv; + char ch; + + priv = os_malloc(sizeof(struct uart_hal_priv)); + if (!priv) { + return OS_ENOMEM; + } + priv->unit = -1; + + ch = odev->od_name[strlen(odev->od_name) - 1]; + if (!isdigit((int)ch)) { + return OS_EINVAL; + } + priv->unit = ch - '0'; + + dev = (struct uart_dev *)odev; + + OS_DEV_SETHANDLERS(odev, uart_hal_open, uart_hal_close); + + dev->ud_funcs.uf_start_tx = uart_hal_start_tx; + dev->ud_funcs.uf_start_rx = uart_hal_start_rx; + dev->ud_funcs.uf_blocking_tx = uart_hal_blocking_tx; + dev->ud_priv = priv; + + hal_uart_init(priv->unit, arg); + + return OS_OK; +} http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0ef64aa7/hw/drivers/uart/uart_hal/src/uart_hal_BASE_19438.c ---------------------------------------------------------------------- diff --git a/hw/drivers/uart/uart_hal/src/uart_hal_BASE_19438.c b/hw/drivers/uart/uart_hal/src/uart_hal_BASE_19438.c new file mode 100644 index 0000000..5617f6b --- /dev/null +++ b/hw/drivers/uart/uart_hal/src/uart_hal_BASE_19438.c @@ -0,0 +1,143 @@ +/** + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include <ctype.h> +#include <assert.h> +#include <string.h> + +#include <os/os.h> +#include <os/os_dev.h> +#include <hal/hal_uart.h> + +#include <uart/uart.h> + +#include "uart_hal/uart_hal.h" + +struct uart_hal_priv { + int unit; +}; + +static void +uart_hal_start_tx(struct uart_dev *dev) +{ + struct uart_hal_priv *priv; + + priv = dev->ud_priv; + assert(priv); + + hal_uart_start_tx(priv->unit); +} + +static void +uart_hal_start_rx(struct uart_dev *dev) +{ + struct uart_hal_priv *priv; + + priv = dev->ud_priv; + + hal_uart_start_rx(priv->unit); +} + +static void +uart_hal_blocking_tx(struct uart_dev *dev, uint8_t byte) +{ + struct uart_hal_priv *priv; + + priv = dev->ud_priv; + + hal_uart_blocking_tx(priv->unit, byte); +} + +static int +uart_hal_open(struct os_dev *odev, uint32_t wait, void *arg) +{ + struct uart_hal_priv *priv; + struct uart_conf *uc; + int rc; + + priv = ((struct uart_dev *)odev)->ud_priv; + + uc = (struct uart_conf *)arg; + if (!uc) { + return OS_EINVAL; + } + if (odev->od_flags & OS_DEV_F_STATUS_OPEN) { + return OS_EBUSY; + } + hal_uart_init_cbs(priv->unit, uc->uc_tx_char, uc->uc_tx_done, + uc->uc_rx_char, uc->uc_cb_arg); + + rc = hal_uart_config(priv->unit, uc->uc_speed, uc->uc_databits, + uc->uc_stopbits, uc->uc_parity, uc->uc_flow_ctl); + if (rc) { + return OS_EINVAL; + } + return OS_OK; +} + +static int +uart_hal_close(struct os_dev *odev) +{ + struct uart_hal_priv *priv; + int rc; + + priv = ((struct uart_dev *)odev)->ud_priv; + + rc = hal_uart_close(priv->unit); + if (rc) { + return OS_EINVAL; + } + return OS_OK; +} + +/* + * Arg points to BSP specific UART configuration. + */ +int +uart_hal_init(struct os_dev *odev, void *arg) +{ + struct uart_dev *dev; + struct uart_hal_priv *priv; + char ch; + + priv = os_malloc(sizeof(struct uart_hal_priv)); + if (!priv) { + return OS_ENOMEM; + } + priv->unit = -1; + + ch = odev->od_name[strlen(odev->od_name) - 1]; + if (!isdigit(ch)) { + return OS_EINVAL; + } + priv->unit = ch - '0'; + + dev = (struct uart_dev *)odev; + + OS_DEV_SETHANDLERS(odev, uart_hal_open, uart_hal_close); + + dev->ud_funcs.uf_start_tx = uart_hal_start_tx; + dev->ud_funcs.uf_start_rx = uart_hal_start_rx; + dev->ud_funcs.uf_blocking_tx = uart_hal_blocking_tx; + dev->ud_priv = priv; + + hal_uart_init(priv->unit, arg); + + return OS_OK; +} http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0ef64aa7/hw/drivers/uart/uart_hal/src/uart_hal_LOCAL_19438.c ---------------------------------------------------------------------- diff --git a/hw/drivers/uart/uart_hal/src/uart_hal_LOCAL_19438.c b/hw/drivers/uart/uart_hal/src/uart_hal_LOCAL_19438.c new file mode 100644 index 0000000..c99e613 --- /dev/null +++ b/hw/drivers/uart/uart_hal/src/uart_hal_LOCAL_19438.c @@ -0,0 +1,143 @@ +/** + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include <ctype.h> +#include <assert.h> +#include <string.h> + +#include <os/os.h> +#include <os/os_dev.h> +#include <hal/hal_uart.h> + +#include <uart/uart.h> + +#include "uart_hal/uart_hal.h" + +struct uart_hal_priv { + int unit; +}; + +static void +uart_hal_start_tx(struct uart_dev *dev) +{ + struct uart_hal_priv *priv; + + priv = dev->ud_priv; + assert(priv); + + hal_uart_start_tx(priv->unit); +} + +static void +uart_hal_start_rx(struct uart_dev *dev) +{ + struct uart_hal_priv *priv; + + priv = dev->ud_priv; + + hal_uart_start_rx(priv->unit); +} + +static void +uart_hal_blocking_tx(struct uart_dev *dev, uint8_t byte) +{ + struct uart_hal_priv *priv; + + priv = dev->ud_priv; + + hal_uart_blocking_tx(priv->unit, byte); +} + +static int +uart_hal_open(struct os_dev *odev, uint32_t wait, void *arg) +{ + struct uart_hal_priv *priv; + struct uart_conf *uc; + int rc; + + priv = ((struct uart_dev *)odev)->ud_priv; + + uc = (struct uart_conf *)arg; + if (!uc) { + return OS_EINVAL; + } + if (odev->od_flags & OS_DEV_F_STATUS_OPEN) { + return OS_EBUSY; + } + hal_uart_init_cbs(priv->unit, uc->uc_tx_char, uc->uc_tx_done, + uc->uc_rx_char, uc->uc_cb_arg); + + rc = hal_uart_config(priv->unit, uc->uc_speed, uc->uc_databits, + uc->uc_stopbits, uc->uc_parity, uc->uc_flow_ctl); + if (rc) { + return OS_EINVAL; + } + return OS_OK; +} + +static int +uart_hal_close(struct os_dev *odev) +{ + struct uart_hal_priv *priv; + int rc; + + priv = ((struct uart_dev *)odev)->ud_priv; + + rc = hal_uart_close(priv->unit); + if (rc) { + return OS_EINVAL; + } + return OS_OK; +} + +/* + * Arg points to BSP specific UART configuration. + */ +int +uart_hal_init(struct os_dev *odev, void *arg) +{ + struct uart_dev *dev; + struct uart_hal_priv *priv; + char ch; + + priv = os_malloc(sizeof(struct uart_hal_priv)); + if (!priv) { + return OS_ENOMEM; + } + priv->unit = -1; + + ch = odev->od_name[strlen(odev->od_name) - 1]; + if (!isdigit((int) ch)) { + return OS_EINVAL; + } + priv->unit = ch - '0'; + + dev = (struct uart_dev *)odev; + + OS_DEV_SETHANDLERS(odev, uart_hal_open, uart_hal_close); + + dev->ud_funcs.uf_start_tx = uart_hal_start_tx; + dev->ud_funcs.uf_start_rx = uart_hal_start_rx; + dev->ud_funcs.uf_blocking_tx = uart_hal_blocking_tx; + dev->ud_priv = priv; + + hal_uart_init(priv->unit, arg); + + return OS_OK; +} http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0ef64aa7/hw/drivers/uart/uart_hal/src/uart_hal_REMOTE_19438.c ---------------------------------------------------------------------- diff --git a/hw/drivers/uart/uart_hal/src/uart_hal_REMOTE_19438.c b/hw/drivers/uart/uart_hal/src/uart_hal_REMOTE_19438.c new file mode 100644 index 0000000..940990a --- /dev/null +++ b/hw/drivers/uart/uart_hal/src/uart_hal_REMOTE_19438.c @@ -0,0 +1,143 @@ +/** + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include <ctype.h> +#include <assert.h> +#include <string.h> + +#include <os/os.h> +#include <os/os_dev.h> +#include <hal/hal_uart.h> + +#include <uart/uart.h> + +#include "uart_hal/uart_hal.h" + +struct uart_hal_priv { + int unit; +}; + +static void +uart_hal_start_tx(struct uart_dev *dev) +{ + struct uart_hal_priv *priv; + + priv = dev->ud_priv; + assert(priv); + + hal_uart_start_tx(priv->unit); +} + +static void +uart_hal_start_rx(struct uart_dev *dev) +{ + struct uart_hal_priv *priv; + + priv = dev->ud_priv; + + hal_uart_start_rx(priv->unit); +} + +static void +uart_hal_blocking_tx(struct uart_dev *dev, uint8_t byte) +{ + struct uart_hal_priv *priv; + + priv = dev->ud_priv; + + hal_uart_blocking_tx(priv->unit, byte); +} + +static int +uart_hal_open(struct os_dev *odev, uint32_t wait, void *arg) +{ + struct uart_hal_priv *priv; + struct uart_conf *uc; + int rc; + + priv = ((struct uart_dev *)odev)->ud_priv; + + uc = (struct uart_conf *)arg; + if (!uc) { + return OS_EINVAL; + } + if (odev->od_flags & OS_DEV_F_STATUS_OPEN) { + return OS_EBUSY; + } + hal_uart_init_cbs(priv->unit, uc->uc_tx_char, uc->uc_tx_done, + uc->uc_rx_char, uc->uc_cb_arg); + + rc = hal_uart_config(priv->unit, uc->uc_speed, uc->uc_databits, + uc->uc_stopbits, uc->uc_parity, uc->uc_flow_ctl); + if (rc) { + return OS_EINVAL; + } + return OS_OK; +} + +static int +uart_hal_close(struct os_dev *odev) +{ + struct uart_hal_priv *priv; + int rc; + + priv = ((struct uart_dev *)odev)->ud_priv; + + rc = hal_uart_close(priv->unit); + if (rc) { + return OS_EINVAL; + } + return OS_OK; +} + +/* + * Arg points to BSP specific UART configuration. + */ +int +uart_hal_init(struct os_dev *odev, void *arg) +{ + struct uart_dev *dev; + struct uart_hal_priv *priv; + char ch; + + priv = os_malloc(sizeof(struct uart_hal_priv)); + if (!priv) { + return OS_ENOMEM; + } + priv->unit = -1; + + ch = odev->od_name[strlen(odev->od_name) - 1]; + if (!isdigit((int)ch)) { + return OS_EINVAL; + } + priv->unit = ch - '0'; + + dev = (struct uart_dev *)odev; + + OS_DEV_SETHANDLERS(odev, uart_hal_open, uart_hal_close); + + dev->ud_funcs.uf_start_tx = uart_hal_start_tx; + dev->ud_funcs.uf_start_rx = uart_hal_start_rx; + dev->ud_funcs.uf_blocking_tx = uart_hal_blocking_tx; + dev->ud_priv = priv; + + hal_uart_init(priv->unit, arg); + + return OS_OK; +} http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0ef64aa7/hw/mcu/mips/danube/src/hal_uart.c ---------------------------------------------------------------------- diff --git a/hw/mcu/mips/danube/src/hal_uart.c b/hw/mcu/mips/danube/src/hal_uart.c index 0b40ec0..7509fed 100644 --- a/hw/mcu/mips/danube/src/hal_uart.c +++ b/hw/mcu/mips/danube/src/hal_uart.c @@ -209,6 +209,12 @@ hal_uart_blocking_tx(int port, uint8_t data) } int +hal_uart_init(int port, void *arg) +{ + return 0; +} + +int hal_uart_config(int port, int32_t baudrate, uint8_t databits, uint8_t stopbits, enum hal_uart_parity parity, enum hal_uart_flow_ctl flow_ctl) { http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0ef64aa7/hw/mcu/mips/danube/src/hal_watchdog.c ---------------------------------------------------------------------- diff --git a/hw/mcu/mips/danube/src/hal_watchdog.c b/hw/mcu/mips/danube/src/hal_watchdog.c new file mode 100644 index 0000000..392b967 --- /dev/null +++ b/hw/mcu/mips/danube/src/hal_watchdog.c @@ -0,0 +1,39 @@ +/** + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include "hal/hal_watchdog.h" + +#include <assert.h> + +int +hal_watchdog_init(uint32_t expire_msecs) +{ + return (0); +} + +void +hal_watchdog_enable(void) +{ +} + +void +hal_watchdog_tickle(void) +{ +} + http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0ef64aa7/kernel/os/include/os/arch/mips/os/os_arch.h ---------------------------------------------------------------------- diff --git a/kernel/os/include/os/arch/mips/os/os_arch.h b/kernel/os/include/os/arch/mips/os/os_arch.h new file mode 100644 index 0000000..33afcee --- /dev/null +++ b/kernel/os/include/os/arch/mips/os/os_arch.h @@ -0,0 +1,80 @@ +/** + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#ifndef _OS_ARCH_MIPS_H +#define _OS_ARCH_MIPS_H + +#include <stdint.h> +#include <mips/cpu.h> +#include <mips/m32c0.h> + +#include "mcu/mips.h" + +struct os_task; + +/* Run in priviliged or unprivileged Thread mode */ +/* only priv currently supported */ +#define OS_RUN_PRIV (0) +#define OS_RUN_UNPRIV (1) + +/* CPU status register */ +typedef uint32_t os_sr_t; +/* Stack type, aligned to a 32-bit word. */ +#define OS_STACK_PATTERN (0xdeadbeef) + +typedef uint32_t os_stack_t; +#define OS_ALIGNMENT (4) +#define OS_STACK_ALIGNMENT (8) + +/* + * Stack sizes for common OS tasks + */ +#define OS_SANITY_STACK_SIZE (64) +#define OS_IDLE_STACK_SIZE (64) + +#define OS_STACK_ALIGN(__nmemb) \ + (OS_ALIGN((__nmemb), OS_STACK_ALIGNMENT)) + +/* Enter a critical section, save processor state, and block interrupts */ +#define OS_ENTER_CRITICAL(__os_sr) do {__os_sr = _mips_intdisable();} while(0) + +/* Exit a critical section, restore processor state and unblock interrupts */ +#define OS_EXIT_CRITICAL(__os_sr) _mips_intrestore(__os_sr) +#define OS_IS_CRITICAL() ((mips_getsr() & 1) == 0) +#define OS_ASSERT_CRITICAL() assert(OS_IS_CRITICAL()) + +os_stack_t *os_arch_task_stack_init(struct os_task *, os_stack_t *, int); +void timer_handler(void); +void os_arch_ctx_sw(struct os_task *); +os_sr_t os_arch_save_sr(void); +void os_arch_restore_sr(os_sr_t); +int os_arch_in_critical(void); +void os_arch_init(void); +uint32_t os_arch_start(void); +os_error_t os_arch_os_init(void); +os_error_t os_arch_os_start(void); +void os_set_env(os_stack_t *); +void os_arch_init_task_stack(os_stack_t *sf); +void os_default_irq_asm(void); + +/* External function prototypes supplied by BSP */ +void os_bsp_systick_init(uint32_t os_ticks_per_sec, int prio); +void os_bsp_ctx_sw(void); + +#endif /* _OS_ARCH_ARM_H */ http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0ef64aa7/kernel/os/include/os/arch/sim-mips/os/os_arch.h ---------------------------------------------------------------------- diff --git a/kernel/os/include/os/arch/sim-mips/os/os_arch.h b/kernel/os/include/os/arch/sim-mips/os/os_arch.h new file mode 100644 index 0000000..d9570c8 --- /dev/null +++ b/kernel/os/include/os/arch/sim-mips/os/os_arch.h @@ -0,0 +1,74 @@ +/** + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#ifndef _OS_ARCH_SIM_H +#define _OS_ARCH_SIM_H + +#include <mcu/mcu_sim.h> + +struct os_task; + +/* CPU status register */ +typedef unsigned int os_sr_t; +/* Stack type, aligned to a 32-bit word. */ +#define OS_STACK_PATTERN (0xdeadbeef) + +typedef unsigned int os_stack_t; +#define OS_ALIGNMENT (4) +#define OS_STACK_ALIGNMENT (16) + +/* + * Stack sizes for common OS tasks + */ +#define OS_SANITY_STACK_SIZE (1024) +#define OS_IDLE_STACK_SIZE (1024) + +/* + * The 'sim' architecture-specific code does not have as much control on + * stack usage as the real embedded architectures. + * + * For e.g. the space occupied by the signal handler frame on the task + * stack is entirely dependent on the host OS. + * + * Deal with this by scaling the stack size by a factor of 16. The scaling + * factor can be arbitrarily large because the stacks are allocated from + * BSS and thus don't add to either the executable size or resident + * memory. + */ +#define OS_STACK_ALIGN(__nmemb) \ + (OS_ALIGN(((__nmemb) * 16), OS_STACK_ALIGNMENT)) + +/* Enter a critical section, save processor state, and block interrupts */ +#define OS_ENTER_CRITICAL(__os_sr) (__os_sr = os_arch_save_sr()) +/* Exit a critical section, restore processor state and unblock interrupts */ +#define OS_EXIT_CRITICAL(__os_sr) (os_arch_restore_sr(__os_sr)) +#define OS_ASSERT_CRITICAL() (assert(os_arch_in_critical())) + +void _Die(char *file, int line); + +os_stack_t *os_arch_task_stack_init(struct os_task *, os_stack_t *, int); +void os_arch_ctx_sw(struct os_task *); +os_sr_t os_arch_save_sr(void); +void os_arch_restore_sr(os_sr_t sr); +int os_arch_in_critical(void); +os_error_t os_arch_os_init(void); +void os_arch_os_stop(void); +os_error_t os_arch_os_start(void); + +#endif /* _OS_ARCH_SIM_H */ http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0ef64aa7/kernel/os/src/arch/mips/asm/ctx.S ---------------------------------------------------------------------- diff --git a/kernel/os/src/arch/mips/asm/ctx.S b/kernel/os/src/arch/mips/asm/ctx.S new file mode 100644 index 0000000..a851f90 --- /dev/null +++ b/kernel/os/src/arch/mips/asm/ctx.S @@ -0,0 +1,197 @@ +/* + * Copyright 2016, Imagination Technologies Limited and/or its + * affiliated group companies. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. +*/ + +#include <mips/regdef.h> +#include <mips/asm.h> +#include <mips/cpu.h> +#include <mips/hal.h> + +# note that k0 is not saved when using these macros. +# The cause register is saved but not resored. + +# saves to location k0 +.macro _gpctx_save + REG_S $1, CTX_REG(1) (k0) + REG_S $2, CTX_REG(2) (k0) + REG_S $3, CTX_REG(3) (k0) + REG_S $4, CTX_REG(4) (k0) + REG_S $5, CTX_REG(5) (k0) + REG_S $6, CTX_REG(6) (k0) + REG_S $7, CTX_REG(7) (k0) + REG_S $8, CTX_REG(8) (k0) + REG_S $9, CTX_REG(9) (k0) + REG_S $10, CTX_REG(10) (k0) + REG_S $11, CTX_REG(11) (k0) + REG_S $12, CTX_REG(12) (k0) + REG_S $13, CTX_REG(13) (k0) + REG_S $14, CTX_REG(14) (k0) + REG_S $15, CTX_REG(15) (k0) + REG_S $16, CTX_REG(16) (k0) + REG_S $17, CTX_REG(17)(k0) + REG_S $18, CTX_REG(18)(k0) + REG_S $19, CTX_REG(19)(k0) + REG_S $20, CTX_REG(20)(k0) + REG_S $21, CTX_REG(21)(k0) + REG_S $22, CTX_REG(22)(k0) + REG_S $23, CTX_REG(23)(k0) + REG_S $24, CTX_REG(24)(k0) + REG_S $25, CTX_REG(25)(k0) + # k0 not saved + REG_S $27, CTX_REG(27)(k0) + REG_S $28, CTX_REG(28)(k0) + REG_S $29, CTX_REG(29)(k0) + REG_S $30, CTX_REG(30)(k0) + REG_S $31, CTX_REG(31)(k0) + PTR_S $0, CTX_LINK(k0) # Clear the link field + +#if (__mips_isa_rev < 6) + mfhi $9 + mflo $10 + REG_S $9, CTX_HI0(k0) + REG_S $10, CTX_LO0(k0) +#endif + + # cp0 + REG_S ra, CTX_EPC(k0) + PTR_MFC0 $9, C0_BADVADDR + REG_S $9, CTX_BADVADDR(k0) + mfc0 $9, C0_SR + sw $9, CTX_STATUS(k0) + mfc0 $9, C0_CR + sw $9, CTX_CAUSE(k0) + + move $11, $0 + move $12, $0 + mfc0 $9, C0_CONFIG3 + ext $10, $9, CFG3_BP_SHIFT, 1 + beqz $10, 1f + mfc0 $11, C0_BADPINSTR +1: + ext $9, $9, CFG3_BI_SHIFT, 1 + beqz $9, 1f + mfc0 $12, C0_BADINSTR +1: + sw $11, CTX_BADPINSTR(k0) + sw $12, CTX_BADINSTR(k0) +.endm + +# restores from location a0 + +.macro _gpctx_load +#if (__mips_isa_rev < 6) + REG_L $9, CTX_HI0(a0) + REG_L $10, CTX_LO0(a0) + mthi $9 + mtlo $10 +#endif + + REG_L $1, CTX_REG(1)(a0) + REG_L $2, CTX_REG(2)(a0) + REG_L $3, CTX_REG(3)(a0) + # a0 is loaded last + REG_L $5, CTX_REG(5)(a0) + REG_L $6, CTX_REG(6)(a0) + REG_L $7, CTX_REG(7)(a0) + REG_L $8, CTX_REG(8)(a0) + REG_L $9, CTX_REG(9)(a0) + REG_L $10, CTX_REG(10)(a0) + REG_L $11, CTX_REG(11)(a0) + REG_L $12, CTX_REG(12)(a0) + REG_L $13, CTX_REG(13)(a0) + REG_L $14, CTX_REG(14)(a0) + REG_L $15, CTX_REG(15)(a0) + REG_L $16, CTX_REG(16)(a0) + REG_L $17, CTX_REG(17)(a0) + REG_L $18, CTX_REG(18)(a0) + REG_L $19, CTX_REG(19)(a0) + REG_L $20, CTX_REG(20)(a0) + REG_L $21, CTX_REG(21)(a0) + REG_L $22, CTX_REG(22)(a0) + REG_L $23, CTX_REG(23)(a0) + REG_L $24, CTX_REG(24)(a0) + REG_L $25, CTX_REG(25)(a0) + # restore k0 after interrupts have been disabled + REG_L $27, CTX_REG(27)(a0) + REG_L $28, CTX_REG(28)(a0) + # restore sp after interrupts have been disabled + REG_L $30, CTX_REG(30)(a0) + REG_L $31, CTX_REG(31)(a0) + + di + REG_L k0, CTX_EPC(a0) + PTR_MTC0 k0, C0_EPC + lw k0, CTX_STATUS(a0) + # STATUS here will have EXL set + mtc0 k0, C0_SR + ehb + + # restore k0 and sp as these may be overwritten by nested interrupts + REG_L $26, CTX_REG(26)(a0) + REG_L $29, CTX_REG(29)(a0) + # restore a0 last + REG_L $4, CTX_REG(4)(a0) +.endm + +.text +.global get_global_pointer +.ent get_global_pointer +get_global_pointer: + .set noat + move v0, gp + jr ra +.end + +.text +.global _mips_isr_sw0 +.ent _mips_isr_sw0 +_mips_isr_sw0: + # context switch + .set noat + # save k0 + REG_S $26, (CTX_REG(25) - CTX_SIZE) (sp) + addi k0, sp, -((((CTX_SIZE - 1) / 8) + 1) * 8) + _gpctx_save # save the context + .set at + lw t0, g_current_task # get current task + beqz t0, 1f + sw k0, 0(t0) # update stored sp +1: + lw t1, g_os_run_list # get new task + sw t1, g_current_task # g_current_task = g_os_run_list + mfc0 k0, C0_CR + andi k0, k0, 0xfeff # clear interrupt in cause register + lui k1, 0x0080 # make sure IV is set + or k0, k0, k1 + mtc0 k0, C0_CR + lw a0, 0(t1) + .set noat + _gpctx_load # updates actual sp + eret +.end http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0ef64aa7/kernel/os/src/arch/mips/asm/excpt_isr.S ---------------------------------------------------------------------- diff --git a/kernel/os/src/arch/mips/asm/excpt_isr.S b/kernel/os/src/arch/mips/asm/excpt_isr.S new file mode 100644 index 0000000..dded29c --- /dev/null +++ b/kernel/os/src/arch/mips/asm/excpt_isr.S @@ -0,0 +1,100 @@ +/* + * Copyright 2016, Imagination Technologies Limited and/or its + * affiliated group companies. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. +*/ + +# Keep each function in a separate named section +#define _FUNCTION_SECTIONS_ + +#include <mips/regdef.h> +#include <mips/asm.h> +#include <mips/cpu.h> + +#define VEC_SPACE (SZPTR * 8) + +LEAF(__isr_vec) + .set push + .set noat +AENT(__isr_vec_sw0) + j _mips_isr_sw0 +.org VEC_SPACE +AENT(__isr_vec_sw1) + j _mips_isr_sw1 +.org 2 * VEC_SPACE +AENT(__isr_vec_hw0) + j _mips_isr_hw0 +.org 3 * VEC_SPACE +AENT(__isr_vec_hw1) +.weak _mips_isr_hw1 + j _mips_isr_hw1 +.org 4 * VEC_SPACE +AENT(__isr_vec_hw2) + j _mips_isr_hw2 +.org 5 * VEC_SPACE +AENT(__isr_vec_hw3) + j _mips_isr_hw3 +.org 6 * VEC_SPACE +AENT(__isr_vec_hw4) + j _mips_isr_hw4 +.org 7 * VEC_SPACE +AENT(__isr_vec_hw5) + j _mips_isr_hw5 +.org 8 * VEC_SPACE +AENT(__isr_vec_fallback) + j _mips_interrupt + .set pop +END(__isr_vec) + +/* XXX: these are all pointelss, if there was a way to detect if a symbol is + defined elsewhere it could be fixed .ifdef does not seem to work for this */ + +.text +.weak _mips_isr_sw1 +_mips_isr_sw1: + j _mips_interrupt +.weak _mips_isr_hw0 +_mips_isr_hw0: + j _mips_interrupt +.weak _mips_isr_hw1 +_mips_isr_hw1: + j _mips_interrupt +.weak _mips_isr_hw2 +_mips_isr_hw2: + j _mips_interrupt +.weak _mips_isr_hw3 +_mips_isr_hw3: + j _mips_interrupt +.weak _mips_isr_hw4 +_mips_isr_hw4: + j _mips_interrupt +.weak _mips_isr_hw5 +_mips_isr_hw5: + j _mips_interrupt +.weak _mips_interrupt +_mips_interrupt: + j _mips_interrupt /* inf loop */ http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0ef64aa7/kernel/os/src/arch/mips/os_arch_mips.c ---------------------------------------------------------------------- diff --git a/kernel/os/src/arch/mips/os_arch_mips.c b/kernel/os/src/arch/mips/os_arch_mips.c new file mode 100644 index 0000000..7ac01a9 --- /dev/null +++ b/kernel/os/src/arch/mips/os_arch_mips.c @@ -0,0 +1,185 @@ +/** + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include "os/os.h" +#include "os/os_arch.h" +#include <hal/hal_bsp.h> +#include <hal/hal_os_tick.h> + +#include "os_priv.h" + +#include <mips/hal.h> +#include <mips/uhi_syscalls.h> + +#include <string.h> + +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void SysTick_Handler(void); + +/* XXX: determine how to deal with running un-privileged */ +/* only priv currently supported */ +uint32_t os_flags = OS_RUN_PRIV; + +extern struct os_task g_idle_task; + +/* core timer interrupt */ +void __attribute__((interrupt, keep_interrupts_masked)) +_mips_isr_hw5(void) +{ + mips_setcompare(mips_getcompare() + 273000); + timer_handler(); +} + +static int +os_in_isr(void) +{ + /* check the EXL bit */ + return (mips_getsr() & (1 << 1)) ? 1 : 0; +} + +void +timer_handler(void) +{ + os_time_advance(1); +} + +void +os_arch_ctx_sw(struct os_task *t) +{ + if ((os_sched_get_current_task() != 0) && (t != 0)) { + os_sched_ctx_sw_hook(t); + } + + /* trigger sw interrupt */ + mips_biscr(1 << 8); +} + +os_sr_t +os_arch_save_sr(void) +{ + os_sr_t sr; + OS_ENTER_CRITICAL(sr); + return sr; +} + +void +os_arch_restore_sr(os_sr_t isr_ctx) +{ + OS_EXIT_CRITICAL(isr_ctx); +} + +int +os_arch_in_critical(void) +{ + return OS_IS_CRITICAL(); +} + +reg_t get_global_pointer(void); + +/* assumes stack_top will be 8 aligned */ + +os_stack_t * +os_arch_task_stack_init(struct os_task *t, os_stack_t *stack_top, int size) +{ + os_stack_t *s = stack_top - ((((sizeof(struct gpctx) - 1) / + OS_STACK_ALIGNMENT) + 1) * 2); + + struct gpctx ctx = { + .r = { + [3] = (reg_t)t->t_arg, + [27] = get_global_pointer(), + [28] = (reg_t)(stack_top - 4) + }, + .status = mips_getsr(), + .cause = mips_getcr(), + .epc = (reg_t)t->t_func + }; + + /* copy struct onto the stack */ + memcpy(s, &ctx, sizeof(struct gpctx)); + + return (s); +} + +void +os_arch_init(void) +{ + mips_bissr((1 << 15) | (1 << 8)); + os_init_idle_task(); +} + +os_error_t +os_arch_os_init(void) +{ + os_error_t err; + + err = OS_ERR_IN_ISR; + if (os_in_isr() == 0) { + err = OS_OK; + + /* Call bsp related OS initializations */ + bsp_init(); + + /* should be in kernel mode here */ + os_arch_init(); + } + return err; +} + +uint32_t +os_arch_start(void) +{ + struct os_task *t; + + /* Get the highest priority ready to run to set the current task */ + t = os_sched_next_task(); + + /* set the core timer compare register */ + /* XXX: take this magic number (for a 1ms tick from a 546MHz clock) and put + ** it in bsp or mcu somewhere + */ + mips_setcompare(mips_getcount() + 273000); + + /* global interrupt enable */ + mips_bissr(1); + + /* Mark the OS as started, right before we run our first task */ + g_os_started = 1; + + /* Perform context switch to first task */ + os_arch_ctx_sw(t); + + return (uint32_t)(t->t_arg); +} + +os_error_t +os_arch_os_start(void) +{ + os_error_t err; + + err = OS_ERR_IN_ISR; + if (os_in_isr() == 0) { + err = OS_OK; + /* should be in kernel mode here */ + os_arch_start(); + } + + return err; +} http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0ef64aa7/kernel/os/src/arch/mips/os_fault.c ---------------------------------------------------------------------- diff --git a/kernel/os/src/arch/mips/os_fault.c b/kernel/os/src/arch/mips/os_fault.c new file mode 100644 index 0000000..8d89f54 --- /dev/null +++ b/kernel/os/src/arch/mips/os_fault.c @@ -0,0 +1,123 @@ +/** + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include <console/console.h> +#include <hal/hal_system.h> +#ifdef COREDUMP_PRESENT +#include <coredump/coredump.h> +#endif +#include "os/os.h" + +#include <stdint.h> +#include <unistd.h> + +struct exception_frame { + uint32_t r0; + uint32_t r1; + uint32_t r2; + uint32_t r3; + uint32_t r12; + uint32_t lr; + uint32_t pc; + uint32_t psr; +}; + +struct trap_frame { + struct exception_frame *ef; + uint32_t r4; + uint32_t r5; + uint32_t r6; + uint32_t r7; + uint32_t r8; + uint32_t r9; + uint32_t r10; + uint32_t r11; + uint32_t lr; /* this LR holds EXC_RETURN */ +}; + +struct coredump_regs { + uint32_t r0; + uint32_t r1; + uint32_t r2; + uint32_t r3; + uint32_t r4; + uint32_t r5; + uint32_t r6; + uint32_t r7; + uint32_t r8; + uint32_t r9; + uint32_t r10; + uint32_t r11; + uint32_t r12; + uint32_t sp; + uint32_t lr; + uint32_t pc; + uint32_t psr; +}; + +void __assert_func(const char *file, int line, const char *func, const char *e); + +#ifdef COREDUMP_PRESENT +static void +trap_to_coredump(struct trap_frame *tf, struct coredump_regs *regs) +{ +} +#endif + +void +__assert_func(const char *file, int line, const char *func, const char *e) +{ + int sr; + + OS_ENTER_CRITICAL(sr); + (void)sr; + console_blocking_mode(); + console_printf("Assert %s; failed in %s:%d\n", e ? e : "", file, line); + if (system_debugger_connected()) { + /* + * If debugger is attached, breakpoint before the trap. + */ + } + system_reset(); +} + +void +os_default_irq(struct trap_frame *tf) +{ +#ifdef COREDUMP_PRESENT + struct coredump_regs regs; +#endif + + console_blocking_mode(); + console_printf("Unhandled interrupt, exception sp 0x%08lx\n", + (uint32_t)tf->ef); + console_printf(" r0:0x%08lx r1:0x%08lx r2:0x%08lx r3:0x%08lx\n", + tf->ef->r0, tf->ef->r1, tf->ef->r2, tf->ef->r3); + console_printf(" r4:0x%08lx r5:0x%08lx r6:0x%08lx r7:0x%08lx\n", + tf->r4, tf->r5, tf->r6, tf->r7); + console_printf(" r8:0x%08lx r9:0x%08lx r10:0x%08lx r11:0x%08lx\n", + tf->r8, tf->r9, tf->r10, tf->r11); + console_printf("r12:0x%08lx lr:0x%08lx pc:0x%08lx psr:0x%08lx\n", + tf->ef->r12, tf->ef->lr, tf->ef->pc, tf->ef->psr); +#ifdef COREDUMP_PRESENT + trap_to_coredump(tf, ®s); + coredump_dump(®s, sizeof(regs)); +#endif + system_reset(); +} http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0ef64aa7/kernel/os/src/arch/sim-mips/os_arch_sim.c ---------------------------------------------------------------------- diff --git a/kernel/os/src/arch/sim-mips/os_arch_sim.c b/kernel/os/src/arch/sim-mips/os_arch_sim.c new file mode 100644 index 0000000..9a96737 --- /dev/null +++ b/kernel/os/src/arch/sim-mips/os_arch_sim.c @@ -0,0 +1,463 @@ +/** + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include "os/os.h" +#include "os_priv.h" + +#ifdef __APPLE__ +#define _XOPEN_SOURCE +#endif + +#include <string.h> +#include <stdio.h> +#include <unistd.h> +#include <setjmp.h> +#include <signal.h> +#include <sys/time.h> +#include <assert.h> +#include <util/util.h> + +struct stack_frame { + int sf_mainsp; /* stack on which main() is executing */ + sigjmp_buf sf_jb; + struct os_task *sf_task; +}; + +/* + * Assert that 'sf_mainsp' and 'sf_jb' are at the specific offsets where + * os_arch_frame_init() expects them to be. + */ +CTASSERT(offsetof(struct stack_frame, sf_mainsp) == 0); +CTASSERT(offsetof(struct stack_frame, sf_jb) == 8); + +extern void os_arch_frame_init(struct stack_frame *sf); + +#define sim_setjmp(__jb) sigsetjmp(__jb, 0) +#define sim_longjmp(__jb, __ret) siglongjmp(__jb, __ret) + +#define OS_USEC_PER_TICK (1000000 / OS_TICKS_PER_SEC) + +static pid_t mypid; +static sigset_t allsigs, nosigs; +static void timer_handler(int sig); + +static bool suspended; /* process is blocked in sigsuspend() */ +static sigset_t suspsigs; /* signals delivered in sigsuspend() */ + +/* + * Called from 'os_arch_frame_init()' when setjmp returns indirectly via + * longjmp. The return value of setjmp is passed to this function as 'rc'. + */ +void +os_arch_task_start(struct stack_frame *sf, int rc) +{ + struct os_task *task; + + /* + * Interrupts are disabled when a task starts executing. This happens in + * two different ways: + * - via os_arch_os_start() for the first task. + * - via os_sched() for all other tasks. + * + * Enable interrupts before starting the task. + */ + OS_EXIT_CRITICAL(0); + + task = sf->sf_task; + task->t_func(task->t_arg); + + /* This should never return */ + assert(0); +} + +os_stack_t * +os_arch_task_stack_init(struct os_task *t, os_stack_t *stack_top, int size) +{ + struct stack_frame *sf; + + sf = (struct stack_frame *) ((uint8_t *) stack_top - sizeof(*sf)); + sf->sf_task = t; + + os_arch_frame_init(sf); + + return ((os_stack_t *)sf); +} + +void +os_arch_ctx_sw(struct os_task *next_t) +{ + /* + * gdb will stop execution of the program on most signals (e.g. SIGUSR1) + * whereas it passes SIGURG to the process without any special settings. + */ + kill(mypid, SIGURG); +} + +static void +ctxsw_handler(int sig) +{ + struct os_task *t, *next_t; + struct stack_frame *sf; + int rc; + + OS_ASSERT_CRITICAL(); + + /* + * Just record that this handler was called when the process was blocked. + * The handler will be called after sigsuspend() returns in the correct + * order. + */ + if (suspended) { + sigaddset(&suspsigs, sig); + return; + } + + t = os_sched_get_current_task(); + next_t = os_sched_next_task(); + if (t == next_t) { + /* + * Context switch not needed - just return. + */ + return; + } + + if (t) { + sf = (struct stack_frame *) t->t_stackptr; + + rc = sim_setjmp(sf->sf_jb); + if (rc != 0) { + OS_ASSERT_CRITICAL(); + return; + } + } + + os_sched_ctx_sw_hook(next_t); + + os_sched_set_current_task(next_t); + + sf = (struct stack_frame *) next_t->t_stackptr; + sim_longjmp(sf->sf_jb, 1); +} + +/* + * Disable signals and enter a critical section. + * + * Returns 1 if signals were already blocked and 0 otherwise. + */ +os_sr_t +os_arch_save_sr(void) +{ + int error; + sigset_t omask; + + error = sigprocmask(SIG_BLOCK, &allsigs, &omask); + assert(error == 0); + + /* + * If any one of the signals in 'allsigs' is present in 'omask' then + * we are already inside a critical section. + */ + return (sigismember(&omask, SIGALRM)); +} + +void +os_arch_restore_sr(os_sr_t osr) +{ + int error; + + OS_ASSERT_CRITICAL(); + assert(osr == 0 || osr == 1); + + if (osr == 1) { + /* Exiting a nested critical section */ + return; + } + + error = sigprocmask(SIG_UNBLOCK, &allsigs, NULL); + assert(error == 0); +} + +int +os_arch_in_critical(void) +{ + int error; + sigset_t omask; + + error = sigprocmask(SIG_SETMASK, NULL, &omask); + assert(error == 0); + + /* + * If any one of the signals in 'allsigs' is present in 'omask' then + * we are already inside a critical section. + */ + return (sigismember(&omask, SIGALRM)); +} + +static struct { + int num; + void (*handler)(int sig); +} signals[] = { + { SIGALRM, timer_handler }, + { SIGURG, ctxsw_handler }, +}; + +#define NUMSIGS (sizeof(signals)/sizeof(signals[0])) + +void +os_tick_idle(os_time_t ticks) +{ + int i, rc, sig; + struct itimerval it; + void (*handler)(int sig); + + OS_ASSERT_CRITICAL(); + + if (ticks > 0) { + /* + * Enter tickless regime and set the timer to fire after 'ticks' + * worth of time has elapsed. + */ + it.it_value.tv_sec = ticks / OS_TICKS_PER_SEC; + it.it_value.tv_usec = (ticks % OS_TICKS_PER_SEC) * OS_USEC_PER_TICK; + it.it_interval.tv_sec = 0; + it.it_interval.tv_usec = OS_USEC_PER_TICK; + rc = setitimer(ITIMER_REAL, &it, NULL); + assert(rc == 0); + } + + suspended = true; + sigemptyset(&suspsigs); + sigsuspend(&nosigs); /* Wait for a signal to wake us up */ + suspended = false; + + /* + * Call handlers for signals delivered to the process during sigsuspend(). + * The SIGALRM handler is called before any other handlers to ensure that + * OS time is always correct. + */ + if (sigismember(&suspsigs, SIGALRM)) { + timer_handler(SIGALRM); + } + for (i = 0; i < NUMSIGS; i++) { + sig = signals[i].num; + handler = signals[i].handler; + if (sig != SIGALRM && sigismember(&suspsigs, sig)) { + handler(sig); + } + } + + if (ticks > 0) { + /* + * Enable the periodic timer interrupt. + */ + it.it_value.tv_sec = 0; + it.it_value.tv_usec = OS_USEC_PER_TICK; + it.it_interval.tv_sec = 0; + it.it_interval.tv_usec = OS_USEC_PER_TICK; + rc = setitimer(ITIMER_REAL, &it, NULL); + assert(rc == 0); + } +} + +static void +signals_init(void) +{ + int i, error; + struct sigaction sa; + + sigemptyset(&nosigs); + sigemptyset(&allsigs); + for (i = 0; i < NUMSIGS; i++) { + sigaddset(&allsigs, signals[i].num); + } + + for (i = 0; i < NUMSIGS; i++) { + memset(&sa, 0, sizeof sa); + sa.sa_handler = signals[i].handler; + sa.sa_mask = allsigs; + sa.sa_flags = SA_RESTART; + error = sigaction(signals[i].num, &sa, NULL); + assert(error == 0); + } + + /* + * We use SIGALRM as a proxy for 'allsigs' to check if we are inside + * a critical section (for e.g. see os_arch_in_critical()). Make sure + * that SIGALRM is indeed present in 'allsigs'. + */ + assert(sigismember(&allsigs, SIGALRM)); +} + +static void +signals_cleanup(void) +{ + int i, error; + struct sigaction sa; + + for (i = 0; i < NUMSIGS; i++) { + memset(&sa, 0, sizeof sa); + sa.sa_handler = SIG_DFL; + error = sigaction(signals[i].num, &sa, NULL); + assert(error == 0); + } +} + +static void +timer_handler(int sig) +{ + struct timeval time_now, time_diff; + int ticks; + + static struct timeval time_last; + static int time_inited; + + OS_ASSERT_CRITICAL(); + + /* + * Just record that this handler was called when the process was blocked. + * The handler will be called after sigsuspend() returns in the proper + * order. + */ + if (suspended) { + sigaddset(&suspsigs, sig); + return; + } + + if (!time_inited) { + gettimeofday(&time_last, NULL); + time_inited = 1; + } + + gettimeofday(&time_now, NULL); + if (timercmp(&time_now, &time_last, <)) { + /* + * System time going backwards. + */ + time_last = time_now; + } else { + timersub(&time_now, &time_last, &time_diff); + + ticks = time_diff.tv_sec * OS_TICKS_PER_SEC; + ticks += time_diff.tv_usec / OS_USEC_PER_TICK; + + /* + * Update 'time_last' but account for the remainder usecs that did not + * contribute towards whole 'ticks'. + */ + time_diff.tv_sec = 0; + time_diff.tv_usec %= OS_USEC_PER_TICK; + timersub(&time_now, &time_diff, &time_last); + + os_time_advance(ticks); + } +} + +static void +start_timer(void) +{ + struct itimerval it; + int rc; + + memset(&it, 0, sizeof(it)); + it.it_value.tv_sec = 0; + it.it_value.tv_usec = OS_USEC_PER_TICK; + it.it_interval.tv_sec = 0; + it.it_interval.tv_usec = OS_USEC_PER_TICK; + + rc = setitimer(ITIMER_REAL, &it, NULL); + assert(rc == 0); +} + +static void +stop_timer(void) +{ + struct itimerval it; + int rc; + + memset(&it, 0, sizeof(it)); + + rc = setitimer(ITIMER_REAL, &it, NULL); + assert(rc == 0); +} + +os_error_t +os_arch_os_init(void) +{ + mypid = getpid(); + g_current_task = NULL; + + TAILQ_INIT(&g_os_task_list); + TAILQ_INIT(&g_os_run_list); + TAILQ_INIT(&g_os_sleep_list); + + /* + * Setup all interrupt handlers. + * + * This must be done early because task initialization uses critical + * sections which function correctly only when 'allsigs' is initialized. + */ + signals_init(); + + os_init_idle_task(); + os_sanity_task_init(1); + + os_bsp_init(); + + return OS_OK; +} + +os_error_t +os_arch_os_start(void) +{ + struct stack_frame *sf; + struct os_task *t; + os_sr_t sr; + + /* + * Disable interrupts before enabling any interrupt sources. Pending + * interrupts will be recognized when the first task starts executing. + */ + OS_ENTER_CRITICAL(sr); + assert(sr == 0); + + /* Enable the interrupt sources */ + start_timer(); + + t = os_sched_next_task(); + os_sched_set_current_task(t); + + g_os_started = 1; + + sf = (struct stack_frame *) t->t_stackptr; + sim_longjmp(sf->sf_jb, 1); + + return 0; +} + +/** + * Stops the tick timer and clears the "started" flag. This function is only + * implemented for sim. + */ +void +os_arch_os_stop(void) +{ + stop_timer(); + signals_cleanup(); + g_os_started = 0; +} http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0ef64aa7/kernel/os/src/arch/sim-mips/os_arch_stack_frame.s ---------------------------------------------------------------------- diff --git a/kernel/os/src/arch/sim-mips/os_arch_stack_frame.s b/kernel/os/src/arch/sim-mips/os_arch_stack_frame.s new file mode 100644 index 0000000..e4ef39c --- /dev/null +++ b/kernel/os/src/arch/sim-mips/os_arch_stack_frame.s @@ -0,0 +1,65 @@ +/** + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#define sigsetjmp __sigsetjmp + + .text + .p2align 4, 0x90 /* align on 16-byte boundary and fill with NOPs */ + + .globl os_arch_frame_init + .globl _os_arch_frame_init + /* + * void os_arch_frame_init(struct stack_frame *sf) + */ + +os_arch_frame_init: + /* ABI stack frame */ + addi $sp, $sp, -24 /* 8 bytes for register save, 16 for args */ + sw $ra, 0x20($sp) /* push ra to stack */ + sw $s0, 0x16($sp) /* push s0 to the stack */ + + /* save and update sp to sf */ + move $s0, $a0 /* move sf to s0 */ + sw $sp, 0x0($s0) /* sf->mainsp = stack pointer */ + /* fairly sure sf will be 8 byte alligned anyway, but no harm in and vs move */ + and $sp, $s0, 0xfffffff1 /* stack pointer = sf 8 byte aligned */ + + /* call setjmp */ + addi $a0, $s0, 0x08 /* populate the arguments for sigsetjmp */ + move $a1, $zero + jal sigsetjmp /* sigsetjmp(sf->sf_jb, 0) */ + nop + + /* branch if starting task */ + bne $v0, $zero, os_arch_frame_init_start + nop + + /* back to main stack and return */ + lw $sp, 0x0($s0) /* back to main stack */ + lw $ra, 0x20($sp) /* pop ra from stack */ + lw $s0, 0x16($sp) /* pop s0 from the stack */ + addi $sp, $sp, 24 + jr $ra /* return */ + nop + +os_arch_frame_init_start: + move $a0, $s0 /* populate arguments for task */ + move $a1, $v0 + j os_arch_task_start /* jump to task, never to return */ + nop http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0ef64aa7/kernel/os/src/arch/sim-mips/os_fault.c ---------------------------------------------------------------------- diff --git a/kernel/os/src/arch/sim-mips/os_fault.c b/kernel/os/src/arch/sim-mips/os_fault.c new file mode 100644 index 0000000..15c40fe --- /dev/null +++ b/kernel/os/src/arch/sim-mips/os_fault.c @@ -0,0 +1,34 @@ +/** + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ +#include <stdio.h> +#include <string.h> +#include <unistd.h> + +#include "os/os.h" +#include "os_priv.h" + +void +__assert_func(const char *file, int line, const char *func, const char *e) +{ + char msg[256]; + + snprintf(msg, sizeof(msg), "assert at %s:%d\n", file, line); + write(1, msg, strlen(msg)); + _exit(1); +} http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0ef64aa7/libs/os/include/os/arch/mips/os/os_arch.h ---------------------------------------------------------------------- diff --git a/libs/os/include/os/arch/mips/os/os_arch.h b/libs/os/include/os/arch/mips/os/os_arch.h deleted file mode 100644 index 33afcee..0000000 --- a/libs/os/include/os/arch/mips/os/os_arch.h +++ /dev/null @@ -1,80 +0,0 @@ -/** - * Licensed to the Apache Software Foundation (ASF) under one - * or more contributor license agreements. See the NOTICE file - * distributed with this work for additional information - * regarding copyright ownership. The ASF licenses this file - * to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance - * with the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, - * software distributed under the License is distributed on an - * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY - * KIND, either express or implied. See the License for the - * specific language governing permissions and limitations - * under the License. - */ - -#ifndef _OS_ARCH_MIPS_H -#define _OS_ARCH_MIPS_H - -#include <stdint.h> -#include <mips/cpu.h> -#include <mips/m32c0.h> - -#include "mcu/mips.h" - -struct os_task; - -/* Run in priviliged or unprivileged Thread mode */ -/* only priv currently supported */ -#define OS_RUN_PRIV (0) -#define OS_RUN_UNPRIV (1) - -/* CPU status register */ -typedef uint32_t os_sr_t; -/* Stack type, aligned to a 32-bit word. */ -#define OS_STACK_PATTERN (0xdeadbeef) - -typedef uint32_t os_stack_t; -#define OS_ALIGNMENT (4) -#define OS_STACK_ALIGNMENT (8) - -/* - * Stack sizes for common OS tasks - */ -#define OS_SANITY_STACK_SIZE (64) -#define OS_IDLE_STACK_SIZE (64) - -#define OS_STACK_ALIGN(__nmemb) \ - (OS_ALIGN((__nmemb), OS_STACK_ALIGNMENT)) - -/* Enter a critical section, save processor state, and block interrupts */ -#define OS_ENTER_CRITICAL(__os_sr) do {__os_sr = _mips_intdisable();} while(0) - -/* Exit a critical section, restore processor state and unblock interrupts */ -#define OS_EXIT_CRITICAL(__os_sr) _mips_intrestore(__os_sr) -#define OS_IS_CRITICAL() ((mips_getsr() & 1) == 0) -#define OS_ASSERT_CRITICAL() assert(OS_IS_CRITICAL()) - -os_stack_t *os_arch_task_stack_init(struct os_task *, os_stack_t *, int); -void timer_handler(void); -void os_arch_ctx_sw(struct os_task *); -os_sr_t os_arch_save_sr(void); -void os_arch_restore_sr(os_sr_t); -int os_arch_in_critical(void); -void os_arch_init(void); -uint32_t os_arch_start(void); -os_error_t os_arch_os_init(void); -os_error_t os_arch_os_start(void); -void os_set_env(os_stack_t *); -void os_arch_init_task_stack(os_stack_t *sf); -void os_default_irq_asm(void); - -/* External function prototypes supplied by BSP */ -void os_bsp_systick_init(uint32_t os_ticks_per_sec, int prio); -void os_bsp_ctx_sw(void); - -#endif /* _OS_ARCH_ARM_H */ http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0ef64aa7/libs/os/include/os/arch/sim-mips/os/os_arch.h ---------------------------------------------------------------------- diff --git a/libs/os/include/os/arch/sim-mips/os/os_arch.h b/libs/os/include/os/arch/sim-mips/os/os_arch.h deleted file mode 100644 index d9570c8..0000000 --- a/libs/os/include/os/arch/sim-mips/os/os_arch.h +++ /dev/null @@ -1,74 +0,0 @@ -/** - * Licensed to the Apache Software Foundation (ASF) under one - * or more contributor license agreements. See the NOTICE file - * distributed with this work for additional information - * regarding copyright ownership. The ASF licenses this file - * to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance - * with the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, - * software distributed under the License is distributed on an - * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY - * KIND, either express or implied. See the License for the - * specific language governing permissions and limitations - * under the License. - */ - -#ifndef _OS_ARCH_SIM_H -#define _OS_ARCH_SIM_H - -#include <mcu/mcu_sim.h> - -struct os_task; - -/* CPU status register */ -typedef unsigned int os_sr_t; -/* Stack type, aligned to a 32-bit word. */ -#define OS_STACK_PATTERN (0xdeadbeef) - -typedef unsigned int os_stack_t; -#define OS_ALIGNMENT (4) -#define OS_STACK_ALIGNMENT (16) - -/* - * Stack sizes for common OS tasks - */ -#define OS_SANITY_STACK_SIZE (1024) -#define OS_IDLE_STACK_SIZE (1024) - -/* - * The 'sim' architecture-specific code does not have as much control on - * stack usage as the real embedded architectures. - * - * For e.g. the space occupied by the signal handler frame on the task - * stack is entirely dependent on the host OS. - * - * Deal with this by scaling the stack size by a factor of 16. The scaling - * factor can be arbitrarily large because the stacks are allocated from - * BSS and thus don't add to either the executable size or resident - * memory. - */ -#define OS_STACK_ALIGN(__nmemb) \ - (OS_ALIGN(((__nmemb) * 16), OS_STACK_ALIGNMENT)) - -/* Enter a critical section, save processor state, and block interrupts */ -#define OS_ENTER_CRITICAL(__os_sr) (__os_sr = os_arch_save_sr()) -/* Exit a critical section, restore processor state and unblock interrupts */ -#define OS_EXIT_CRITICAL(__os_sr) (os_arch_restore_sr(__os_sr)) -#define OS_ASSERT_CRITICAL() (assert(os_arch_in_critical())) - -void _Die(char *file, int line); - -os_stack_t *os_arch_task_stack_init(struct os_task *, os_stack_t *, int); -void os_arch_ctx_sw(struct os_task *); -os_sr_t os_arch_save_sr(void); -void os_arch_restore_sr(os_sr_t sr); -int os_arch_in_critical(void); -os_error_t os_arch_os_init(void); -void os_arch_os_stop(void); -os_error_t os_arch_os_start(void); - -#endif /* _OS_ARCH_SIM_H */ http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0ef64aa7/libs/os/src/arch/mips/asm/ctx.S ---------------------------------------------------------------------- diff --git a/libs/os/src/arch/mips/asm/ctx.S b/libs/os/src/arch/mips/asm/ctx.S deleted file mode 100644 index a851f90..0000000 --- a/libs/os/src/arch/mips/asm/ctx.S +++ /dev/null @@ -1,197 +0,0 @@ -/* - * Copyright 2016, Imagination Technologies Limited and/or its - * affiliated group companies. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. -*/ - -#include <mips/regdef.h> -#include <mips/asm.h> -#include <mips/cpu.h> -#include <mips/hal.h> - -# note that k0 is not saved when using these macros. -# The cause register is saved but not resored. - -# saves to location k0 -.macro _gpctx_save - REG_S $1, CTX_REG(1) (k0) - REG_S $2, CTX_REG(2) (k0) - REG_S $3, CTX_REG(3) (k0) - REG_S $4, CTX_REG(4) (k0) - REG_S $5, CTX_REG(5) (k0) - REG_S $6, CTX_REG(6) (k0) - REG_S $7, CTX_REG(7) (k0) - REG_S $8, CTX_REG(8) (k0) - REG_S $9, CTX_REG(9) (k0) - REG_S $10, CTX_REG(10) (k0) - REG_S $11, CTX_REG(11) (k0) - REG_S $12, CTX_REG(12) (k0) - REG_S $13, CTX_REG(13) (k0) - REG_S $14, CTX_REG(14) (k0) - REG_S $15, CTX_REG(15) (k0) - REG_S $16, CTX_REG(16) (k0) - REG_S $17, CTX_REG(17)(k0) - REG_S $18, CTX_REG(18)(k0) - REG_S $19, CTX_REG(19)(k0) - REG_S $20, CTX_REG(20)(k0) - REG_S $21, CTX_REG(21)(k0) - REG_S $22, CTX_REG(22)(k0) - REG_S $23, CTX_REG(23)(k0) - REG_S $24, CTX_REG(24)(k0) - REG_S $25, CTX_REG(25)(k0) - # k0 not saved - REG_S $27, CTX_REG(27)(k0) - REG_S $28, CTX_REG(28)(k0) - REG_S $29, CTX_REG(29)(k0) - REG_S $30, CTX_REG(30)(k0) - REG_S $31, CTX_REG(31)(k0) - PTR_S $0, CTX_LINK(k0) # Clear the link field - -#if (__mips_isa_rev < 6) - mfhi $9 - mflo $10 - REG_S $9, CTX_HI0(k0) - REG_S $10, CTX_LO0(k0) -#endif - - # cp0 - REG_S ra, CTX_EPC(k0) - PTR_MFC0 $9, C0_BADVADDR - REG_S $9, CTX_BADVADDR(k0) - mfc0 $9, C0_SR - sw $9, CTX_STATUS(k0) - mfc0 $9, C0_CR - sw $9, CTX_CAUSE(k0) - - move $11, $0 - move $12, $0 - mfc0 $9, C0_CONFIG3 - ext $10, $9, CFG3_BP_SHIFT, 1 - beqz $10, 1f - mfc0 $11, C0_BADPINSTR -1: - ext $9, $9, CFG3_BI_SHIFT, 1 - beqz $9, 1f - mfc0 $12, C0_BADINSTR -1: - sw $11, CTX_BADPINSTR(k0) - sw $12, CTX_BADINSTR(k0) -.endm - -# restores from location a0 - -.macro _gpctx_load -#if (__mips_isa_rev < 6) - REG_L $9, CTX_HI0(a0) - REG_L $10, CTX_LO0(a0) - mthi $9 - mtlo $10 -#endif - - REG_L $1, CTX_REG(1)(a0) - REG_L $2, CTX_REG(2)(a0) - REG_L $3, CTX_REG(3)(a0) - # a0 is loaded last - REG_L $5, CTX_REG(5)(a0) - REG_L $6, CTX_REG(6)(a0) - REG_L $7, CTX_REG(7)(a0) - REG_L $8, CTX_REG(8)(a0) - REG_L $9, CTX_REG(9)(a0) - REG_L $10, CTX_REG(10)(a0) - REG_L $11, CTX_REG(11)(a0) - REG_L $12, CTX_REG(12)(a0) - REG_L $13, CTX_REG(13)(a0) - REG_L $14, CTX_REG(14)(a0) - REG_L $15, CTX_REG(15)(a0) - REG_L $16, CTX_REG(16)(a0) - REG_L $17, CTX_REG(17)(a0) - REG_L $18, CTX_REG(18)(a0) - REG_L $19, CTX_REG(19)(a0) - REG_L $20, CTX_REG(20)(a0) - REG_L $21, CTX_REG(21)(a0) - REG_L $22, CTX_REG(22)(a0) - REG_L $23, CTX_REG(23)(a0) - REG_L $24, CTX_REG(24)(a0) - REG_L $25, CTX_REG(25)(a0) - # restore k0 after interrupts have been disabled - REG_L $27, CTX_REG(27)(a0) - REG_L $28, CTX_REG(28)(a0) - # restore sp after interrupts have been disabled - REG_L $30, CTX_REG(30)(a0) - REG_L $31, CTX_REG(31)(a0) - - di - REG_L k0, CTX_EPC(a0) - PTR_MTC0 k0, C0_EPC - lw k0, CTX_STATUS(a0) - # STATUS here will have EXL set - mtc0 k0, C0_SR - ehb - - # restore k0 and sp as these may be overwritten by nested interrupts - REG_L $26, CTX_REG(26)(a0) - REG_L $29, CTX_REG(29)(a0) - # restore a0 last - REG_L $4, CTX_REG(4)(a0) -.endm - -.text -.global get_global_pointer -.ent get_global_pointer -get_global_pointer: - .set noat - move v0, gp - jr ra -.end - -.text -.global _mips_isr_sw0 -.ent _mips_isr_sw0 -_mips_isr_sw0: - # context switch - .set noat - # save k0 - REG_S $26, (CTX_REG(25) - CTX_SIZE) (sp) - addi k0, sp, -((((CTX_SIZE - 1) / 8) + 1) * 8) - _gpctx_save # save the context - .set at - lw t0, g_current_task # get current task - beqz t0, 1f - sw k0, 0(t0) # update stored sp -1: - lw t1, g_os_run_list # get new task - sw t1, g_current_task # g_current_task = g_os_run_list - mfc0 k0, C0_CR - andi k0, k0, 0xfeff # clear interrupt in cause register - lui k1, 0x0080 # make sure IV is set - or k0, k0, k1 - mtc0 k0, C0_CR - lw a0, 0(t1) - .set noat - _gpctx_load # updates actual sp - eret -.end http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0ef64aa7/libs/os/src/arch/mips/asm/excpt_isr.S ---------------------------------------------------------------------- diff --git a/libs/os/src/arch/mips/asm/excpt_isr.S b/libs/os/src/arch/mips/asm/excpt_isr.S deleted file mode 100644 index dded29c..0000000 --- a/libs/os/src/arch/mips/asm/excpt_isr.S +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright 2016, Imagination Technologies Limited and/or its - * affiliated group companies. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. -*/ - -# Keep each function in a separate named section -#define _FUNCTION_SECTIONS_ - -#include <mips/regdef.h> -#include <mips/asm.h> -#include <mips/cpu.h> - -#define VEC_SPACE (SZPTR * 8) - -LEAF(__isr_vec) - .set push - .set noat -AENT(__isr_vec_sw0) - j _mips_isr_sw0 -.org VEC_SPACE -AENT(__isr_vec_sw1) - j _mips_isr_sw1 -.org 2 * VEC_SPACE -AENT(__isr_vec_hw0) - j _mips_isr_hw0 -.org 3 * VEC_SPACE -AENT(__isr_vec_hw1) -.weak _mips_isr_hw1 - j _mips_isr_hw1 -.org 4 * VEC_SPACE -AENT(__isr_vec_hw2) - j _mips_isr_hw2 -.org 5 * VEC_SPACE -AENT(__isr_vec_hw3) - j _mips_isr_hw3 -.org 6 * VEC_SPACE -AENT(__isr_vec_hw4) - j _mips_isr_hw4 -.org 7 * VEC_SPACE -AENT(__isr_vec_hw5) - j _mips_isr_hw5 -.org 8 * VEC_SPACE -AENT(__isr_vec_fallback) - j _mips_interrupt - .set pop -END(__isr_vec) - -/* XXX: these are all pointelss, if there was a way to detect if a symbol is - defined elsewhere it could be fixed .ifdef does not seem to work for this */ - -.text -.weak _mips_isr_sw1 -_mips_isr_sw1: - j _mips_interrupt -.weak _mips_isr_hw0 -_mips_isr_hw0: - j _mips_interrupt -.weak _mips_isr_hw1 -_mips_isr_hw1: - j _mips_interrupt -.weak _mips_isr_hw2 -_mips_isr_hw2: - j _mips_interrupt -.weak _mips_isr_hw3 -_mips_isr_hw3: - j _mips_interrupt -.weak _mips_isr_hw4 -_mips_isr_hw4: - j _mips_interrupt -.weak _mips_isr_hw5 -_mips_isr_hw5: - j _mips_interrupt -.weak _mips_interrupt -_mips_interrupt: - j _mips_interrupt /* inf loop */ http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0ef64aa7/libs/os/src/arch/mips/os_arch_mips.c ---------------------------------------------------------------------- diff --git a/libs/os/src/arch/mips/os_arch_mips.c b/libs/os/src/arch/mips/os_arch_mips.c deleted file mode 100644 index 7ac01a9..0000000 --- a/libs/os/src/arch/mips/os_arch_mips.c +++ /dev/null @@ -1,185 +0,0 @@ -/** - * Licensed to the Apache Software Foundation (ASF) under one - * or more contributor license agreements. See the NOTICE file - * distributed with this work for additional information - * regarding copyright ownership. The ASF licenses this file - * to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance - * with the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, - * software distributed under the License is distributed on an - * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY - * KIND, either express or implied. See the License for the - * specific language governing permissions and limitations - * under the License. - */ - -#include "os/os.h" -#include "os/os_arch.h" -#include <hal/hal_bsp.h> -#include <hal/hal_os_tick.h> - -#include "os_priv.h" - -#include <mips/hal.h> -#include <mips/uhi_syscalls.h> - -#include <string.h> - -extern void SVC_Handler(void); -extern void PendSV_Handler(void); -extern void SysTick_Handler(void); - -/* XXX: determine how to deal with running un-privileged */ -/* only priv currently supported */ -uint32_t os_flags = OS_RUN_PRIV; - -extern struct os_task g_idle_task; - -/* core timer interrupt */ -void __attribute__((interrupt, keep_interrupts_masked)) -_mips_isr_hw5(void) -{ - mips_setcompare(mips_getcompare() + 273000); - timer_handler(); -} - -static int -os_in_isr(void) -{ - /* check the EXL bit */ - return (mips_getsr() & (1 << 1)) ? 1 : 0; -} - -void -timer_handler(void) -{ - os_time_advance(1); -} - -void -os_arch_ctx_sw(struct os_task *t) -{ - if ((os_sched_get_current_task() != 0) && (t != 0)) { - os_sched_ctx_sw_hook(t); - } - - /* trigger sw interrupt */ - mips_biscr(1 << 8); -} - -os_sr_t -os_arch_save_sr(void) -{ - os_sr_t sr; - OS_ENTER_CRITICAL(sr); - return sr; -} - -void -os_arch_restore_sr(os_sr_t isr_ctx) -{ - OS_EXIT_CRITICAL(isr_ctx); -} - -int -os_arch_in_critical(void) -{ - return OS_IS_CRITICAL(); -} - -reg_t get_global_pointer(void); - -/* assumes stack_top will be 8 aligned */ - -os_stack_t * -os_arch_task_stack_init(struct os_task *t, os_stack_t *stack_top, int size) -{ - os_stack_t *s = stack_top - ((((sizeof(struct gpctx) - 1) / - OS_STACK_ALIGNMENT) + 1) * 2); - - struct gpctx ctx = { - .r = { - [3] = (reg_t)t->t_arg, - [27] = get_global_pointer(), - [28] = (reg_t)(stack_top - 4) - }, - .status = mips_getsr(), - .cause = mips_getcr(), - .epc = (reg_t)t->t_func - }; - - /* copy struct onto the stack */ - memcpy(s, &ctx, sizeof(struct gpctx)); - - return (s); -} - -void -os_arch_init(void) -{ - mips_bissr((1 << 15) | (1 << 8)); - os_init_idle_task(); -} - -os_error_t -os_arch_os_init(void) -{ - os_error_t err; - - err = OS_ERR_IN_ISR; - if (os_in_isr() == 0) { - err = OS_OK; - - /* Call bsp related OS initializations */ - bsp_init(); - - /* should be in kernel mode here */ - os_arch_init(); - } - return err; -} - -uint32_t -os_arch_start(void) -{ - struct os_task *t; - - /* Get the highest priority ready to run to set the current task */ - t = os_sched_next_task(); - - /* set the core timer compare register */ - /* XXX: take this magic number (for a 1ms tick from a 546MHz clock) and put - ** it in bsp or mcu somewhere - */ - mips_setcompare(mips_getcount() + 273000); - - /* global interrupt enable */ - mips_bissr(1); - - /* Mark the OS as started, right before we run our first task */ - g_os_started = 1; - - /* Perform context switch to first task */ - os_arch_ctx_sw(t); - - return (uint32_t)(t->t_arg); -} - -os_error_t -os_arch_os_start(void) -{ - os_error_t err; - - err = OS_ERR_IN_ISR; - if (os_in_isr() == 0) { - err = OS_OK; - /* should be in kernel mode here */ - os_arch_start(); - } - - return err; -}
