Basic UART functionality added, still under development.
Project: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/repo Commit: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/commit/61a406f1 Tree: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/tree/61a406f1 Diff: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/diff/61a406f1 Branch: refs/heads/develop Commit: 61a406f1f079170faac2c10e9eb6d759a8c4632a Parents: 3db61b0 Author: julian <[email protected]> Authored: Tue Oct 4 15:31:58 2016 +0100 Committer: julian <[email protected]> Committed: Mon Nov 21 11:07:25 2016 +0000 ---------------------------------------------------------------------- compiler/mips/compiler.yml | 34 ++ compiler/mips/pkg.yml | 28 ++ compiler/sim-mips/compiler.yml | 38 ++ compiler/sim-mips/pkg.yml | 28 ++ compiler/simMIPS/compiler.yml | 38 -- compiler/simMIPS/pkg.yml | 29 -- hw/bsp/ci40/include/bsp/bsp.h | 55 +++ hw/bsp/ci40/include/bsp/bsp_sysid.h | 36 ++ hw/bsp/ci40/pkg.yml | 37 ++ hw/bsp/ci40/src/hal_bsp.c | 27 ++ hw/bsp/ci40/src/os_bsp.c | 81 ++++ hw/bsp/ci40/src/sbrk.c | 51 ++ hw/bsp/ci40/uhi32.ld | 307 ++++++++++++ hw/hal/include/hal/hal_uart.h | 1 + hw/mcu/mips/danube/include/mcu/mips.h | 25 + hw/mcu/mips/danube/include/mcu/mips_bsp.h | 24 + hw/mcu/mips/danube/include/mcu/mips_hal.h | 38 ++ hw/mcu/mips/danube/pkg.yml | 30 ++ hw/mcu/mips/danube/src/gic.c | 124 +++++ hw/mcu/mips/danube/src/gic.h | 16 + hw/mcu/mips/danube/src/hal_cputime2.c | 99 ++++ hw/mcu/mips/danube/src/hal_os_tick.c | 36 ++ hw/mcu/mips/danube/src/hal_system.c | 41 ++ hw/mcu/mips/danube/src/hal_uart.c | 300 ++++++++++++ libs/os/include/os/arch/mips/os/os_arch.h | 80 ++++ libs/os/include/os/arch/sim-mips/os/os_arch.h | 74 +++ libs/os/src/arch/mips/asm/ctx.S | 189 ++++++++ libs/os/src/arch/mips/asm/excpt_isr.S | 100 ++++ libs/os/src/arch/mips/os_arch_mips.c | 201 ++++++++ libs/os/src/arch/mips/os_fault.c | 123 +++++ libs/os/src/arch/sim-mips/os_arch_sim.c | 463 +++++++++++++++++++ libs/os/src/arch/sim-mips/os_arch_stack_frame.s | 65 +++ libs/os/src/arch/sim-mips/os_fault.c | 34 ++ libs/os/src/arch/simMIPS/os_arch_sim.c | 463 ------------------- libs/os/src/arch/simMIPS/os_arch_stack_frame.s | 65 --- libs/os/src/arch/simMIPS/os_fault.c | 34 -- 36 files changed, 2785 insertions(+), 629 deletions(-) ---------------------------------------------------------------------- http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/61a406f1/compiler/mips/compiler.yml ---------------------------------------------------------------------- diff --git a/compiler/mips/compiler.yml b/compiler/mips/compiler.yml new file mode 100644 index 0000000..1c48fd1 --- /dev/null +++ b/compiler/mips/compiler.yml @@ -0,0 +1,34 @@ +# +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +compiler.path.cc: "mips-mti-elf-gcc" +compiler.path.as: "mips-mti-elf-gcc -x assembler-with-cpp" +compiler.path.archive: "mips-mti-elf-ar" +compiler.path.objdump: "mips-mti-elf-objdump" +compiler.path.objsize: "mips-mti-elf-size" +compiler.path.objcopy: "mips-mti-elf-objcopy" + +compiler.flags.base: -std=gnu11 -EL -mips32r2 -Wall -Werror +compiler.flags.default: [compiler.flags.base, -O2, -g] +compiler.flags.optimized: [compiler.flags.base, -Os, -g] +compiler.flags.debug: [compiler.flags.base, -g3] + +compiler.ld.flags: -Wl,-defsym,__app_start=0x80000000 +compiler.ld.resolve_circular_deps: true +compiler.ld.mapfile: true http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/61a406f1/compiler/mips/pkg.yml ---------------------------------------------------------------------- diff --git a/compiler/mips/pkg.yml b/compiler/mips/pkg.yml new file mode 100644 index 0000000..2b72664 --- /dev/null +++ b/compiler/mips/pkg.yml @@ -0,0 +1,28 @@ +# +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +pkg.name: compiler/mips +pkg.type: compiler +pkg.description: Compiler definition for mips-elf gcc compiler. +pkg.author: "Apache Mynewt <[email protected]>" +pkg.homepage: "http://mynewt.apache.org/"; +pkg.keywords: + - sim + - compiler + - gcc http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/61a406f1/compiler/sim-mips/compiler.yml ---------------------------------------------------------------------- diff --git a/compiler/sim-mips/compiler.yml b/compiler/sim-mips/compiler.yml new file mode 100644 index 0000000..ebfdd97 --- /dev/null +++ b/compiler/sim-mips/compiler.yml @@ -0,0 +1,38 @@ +# +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +# Default. +compiler.path.cc: "mips-mti-linux-gnu-gcc" +compiler.path.as: "mips-mti-linux-gnu-gcc -x assembler-with-cpp" +compiler.path.archive: "mips-mti-linux-gnu-ar" +compiler.path.objdump: "mips-mti-linux-gnu-objdump" +compiler.path.objsize: "mips-mti-linux-gnu-size" +compiler.path.objcopy: "mips-mti-linux-gnu-objcopy" +compiler.flags.base: > + -std=gnu11 -EL -mips32r2 -Wall -Werror -ggdb +compiler.ld.resolve_circular_deps: true + +compiler.flags.default: [compiler.flags.base, -O1] +compiler.flags.debug: [compiler.flags.base, -O0] +compiler.ld.mapfile: false + +# Linux. +compiler.flags.base.LINUX: > + -DMN_LINUX +compiler.ld.flags.LINUX: -lutil http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/61a406f1/compiler/sim-mips/pkg.yml ---------------------------------------------------------------------- diff --git a/compiler/sim-mips/pkg.yml b/compiler/sim-mips/pkg.yml new file mode 100644 index 0000000..0a8753c --- /dev/null +++ b/compiler/sim-mips/pkg.yml @@ -0,0 +1,28 @@ +# +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +pkg.name: compiler/sim-mips +pkg.type: compiler +pkg.description: Compiler definition for Linux user mips gcc compiler. +pkg.author: "Apache Mynewt <[email protected]>" +pkg.homepage: "http://mynewt.apache.org/"; +pkg.keywords: + - sim + - compiler + - gcc http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/61a406f1/compiler/simMIPS/compiler.yml ---------------------------------------------------------------------- diff --git a/compiler/simMIPS/compiler.yml b/compiler/simMIPS/compiler.yml deleted file mode 100644 index ebfdd97..0000000 --- a/compiler/simMIPS/compiler.yml +++ /dev/null @@ -1,38 +0,0 @@ -# -# Licensed to the Apache Software Foundation (ASF) under one -# or more contributor license agreements. See the NOTICE file -# distributed with this work for additional information -# regarding copyright ownership. The ASF licenses this file -# to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance -# with the License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, -# software distributed under the License is distributed on an -# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY -# KIND, either express or implied. See the License for the -# specific language governing permissions and limitations -# under the License. -# - -# Default. -compiler.path.cc: "mips-mti-linux-gnu-gcc" -compiler.path.as: "mips-mti-linux-gnu-gcc -x assembler-with-cpp" -compiler.path.archive: "mips-mti-linux-gnu-ar" -compiler.path.objdump: "mips-mti-linux-gnu-objdump" -compiler.path.objsize: "mips-mti-linux-gnu-size" -compiler.path.objcopy: "mips-mti-linux-gnu-objcopy" -compiler.flags.base: > - -std=gnu11 -EL -mips32r2 -Wall -Werror -ggdb -compiler.ld.resolve_circular_deps: true - -compiler.flags.default: [compiler.flags.base, -O1] -compiler.flags.debug: [compiler.flags.base, -O0] -compiler.ld.mapfile: false - -# Linux. -compiler.flags.base.LINUX: > - -DMN_LINUX -compiler.ld.flags.LINUX: -lutil http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/61a406f1/compiler/simMIPS/pkg.yml ---------------------------------------------------------------------- diff --git a/compiler/simMIPS/pkg.yml b/compiler/simMIPS/pkg.yml deleted file mode 100644 index 99858eb..0000000 --- a/compiler/simMIPS/pkg.yml +++ /dev/null @@ -1,29 +0,0 @@ -# -# Licensed to the Apache Software Foundation (ASF) under one -# or more contributor license agreements. See the NOTICE file -# distributed with this work for additional information -# regarding copyright ownership. The ASF licenses this file -# to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance -# with the License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, -# software distributed under the License is distributed on an -# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY -# KIND, either express or implied. See the License for the -# specific language governing permissions and limitations -# under the License. -# - -pkg.name: compiler/sim -pkg.type: compiler -pkg.description: Compiler definition for native gcc compiler. -pkg.author: "Apache Mynewt <[email protected]>" -pkg.homepage: "http://mynewt.apache.org/"; -pkg.keywords: - - sim - - compiler - - gcc - http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/61a406f1/hw/bsp/ci40/include/bsp/bsp.h ---------------------------------------------------------------------- diff --git a/hw/bsp/ci40/include/bsp/bsp.h b/hw/bsp/ci40/include/bsp/bsp.h new file mode 100644 index 0000000..f317e1e --- /dev/null +++ b/hw/bsp/ci40/include/bsp/bsp.h @@ -0,0 +1,55 @@ +/** + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ +#ifndef H_BSP_H +#define H_BSP_H + +#include <inttypes.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Define special stackos sections */ +#define sec_data_core __attribute__((section(".data.core"))) +#define sec_bss_core __attribute__((section(".bss.core"))) +#define sec_bss_nz_core __attribute__((section(".bss.core.nz"))) + +/* More convenient section placement macros. */ +#define bssnz_t sec_bss_nz_core + +extern uint8_t _ram_start; +extern uint8_t _ccram_start; + +#define RAM_SIZE (128 * 1024) +#define CCRAM_SIZE (64 * 1024) + +/* LED pins */ +#define LED_BLINK_PIN (45) + +/* UART */ +#define UART_CNT 2 +#define CONSOLE_UART 1 + +#define NFFS_AREA_MAX (8) + +#ifdef __cplusplus +} +#endif + +#endif /* H_BSP_H */ http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/61a406f1/hw/bsp/ci40/include/bsp/bsp_sysid.h ---------------------------------------------------------------------- diff --git a/hw/bsp/ci40/include/bsp/bsp_sysid.h b/hw/bsp/ci40/include/bsp/bsp_sysid.h new file mode 100644 index 0000000..7b0a24b --- /dev/null +++ b/hw/bsp/ci40/include/bsp/bsp_sysid.h @@ -0,0 +1,36 @@ +/** + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ +#ifndef BSP_SYSID_H +#define BSP_SYSID_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* stub until this BSP gets new HAL */ +enum system_device_id +{ + RESERVED, +}; + +#ifdef __cplusplus +} +#endif + +#endif /* BSP_SYSID_H */ \ No newline at end of file http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/61a406f1/hw/bsp/ci40/pkg.yml ---------------------------------------------------------------------- diff --git a/hw/bsp/ci40/pkg.yml b/hw/bsp/ci40/pkg.yml new file mode 100644 index 0000000..167b7f1 --- /dev/null +++ b/hw/bsp/ci40/pkg.yml @@ -0,0 +1,37 @@ +# +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +pkg.name: hw/bsp/ci40 +pkg.type: bsp +pkg.description: BSP definition for the Creator CI40 board. +pkg.author: "Apache Mynewt <[email protected]>" +pkg.homepage: "http://mynewt.apache.org/"; +pkg.keywords: + - creator + - ci40 + - danube + - mips + +pkg.arch: mips +pkg.compiler: compiler/mips +pkg.linkerscript: "uhi32.ld" +pkg.cflags: +pkg.deps: + - hw/mcu/mips/danube + - libs/baselibc http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/61a406f1/hw/bsp/ci40/src/hal_bsp.c ---------------------------------------------------------------------- diff --git a/hw/bsp/ci40/src/hal_bsp.c b/hw/bsp/ci40/src/hal_bsp.c new file mode 100644 index 0000000..c1187c6 --- /dev/null +++ b/hw/bsp/ci40/src/hal_bsp.c @@ -0,0 +1,27 @@ +/** + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ +#include "hal/hal_bsp.h" +#include "bsp/bsp.h" +#include <assert.h> + +const struct hal_flash * +bsp_flash_dev(uint8_t id) +{ + return 0; +} http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/61a406f1/hw/bsp/ci40/src/os_bsp.c ---------------------------------------------------------------------- diff --git a/hw/bsp/ci40/src/os_bsp.c b/hw/bsp/ci40/src/os_bsp.c new file mode 100644 index 0000000..c7e40a0 --- /dev/null +++ b/hw/bsp/ci40/src/os_bsp.c @@ -0,0 +1,81 @@ +/** + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +/* + * XXXX for now have this here. + */ +#include <hal/flash_map.h> +#include <hal/hal_bsp.h> + +static struct flash_area bsp_flash_areas[] = { + [FLASH_AREA_BOOTLOADER] = { + .fa_flash_id = 0, /* internal flash */ + .fa_off = 0x08000000, /* beginning */ + .fa_size = (32 * 1024) + }, + /* 2 * 16K and 1*64K sectors here */ + [FLASH_AREA_IMAGE_0] = { + .fa_flash_id = 0, + .fa_off = 0x08020000, + .fa_size = (384 * 1024) + }, + [FLASH_AREA_IMAGE_1] = { + .fa_flash_id = 0, + .fa_off = 0x08080000, + .fa_size = (384 * 1024) + }, + [FLASH_AREA_IMAGE_SCRATCH] = { + .fa_flash_id = 0, + .fa_off = 0x080e0000, + .fa_size = (128 * 1024) + }, + [FLASH_AREA_NFFS] = { + .fa_flash_id = 0, + .fa_off = 0x08008000, + .fa_size = (32 * 1024) + } +}; + +void _close(int fd); + +/* + * Returns the flash map slot where the currently active image is located. + * If executing from internal flash from fixed location, that slot would + * be easy to find. + * If images are in external flash, and copied to RAM for execution, then + * this routine would have to figure out which one of those slots is being + * used. + */ +int +bsp_imgr_current_slot(void) +{ + return FLASH_AREA_IMAGE_0; +} + +void +bsp_init(void) +{ + /* + * XXX this reference is here to keep this function in. + */ + _sbrk(0); + //_close(0); + flash_area_init(bsp_flash_areas, + sizeof(bsp_flash_areas) / sizeof(bsp_flash_areas[0])); +} http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/61a406f1/hw/bsp/ci40/src/sbrk.c ---------------------------------------------------------------------- diff --git a/hw/bsp/ci40/src/sbrk.c b/hw/bsp/ci40/src/sbrk.c new file mode 100644 index 0000000..d3f99d6 --- /dev/null +++ b/hw/bsp/ci40/src/sbrk.c @@ -0,0 +1,51 @@ +/** + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#define HEAPSIZE (1024) + +static char __Heap[HEAPSIZE]; + +void * +_sbrk(int incr) +{ + static char *brk = __Heap; + + void *prev_brk; + + if (incr < 0) { + /* Returning memory to the heap. */ + incr = -incr; + if (brk - incr < __Heap) { + prev_brk = (void *)-1; + } else { + prev_brk = brk; + brk -= incr; + } + } else { + /* Allocating memory from the heap. */ + if ((__Heap + HEAPSIZE) - brk >= incr) { + prev_brk = brk; + brk += incr; + } else { + prev_brk = (void *)-1; + } + } + + return prev_brk; +} http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/61a406f1/hw/bsp/ci40/uhi32.ld ---------------------------------------------------------------------- diff --git a/hw/bsp/ci40/uhi32.ld b/hw/bsp/ci40/uhi32.ld new file mode 100644 index 0000000..8cc2774 --- /dev/null +++ b/hw/bsp/ci40/uhi32.ld @@ -0,0 +1,307 @@ +/* + * A platform and target independent link script to produce UHI + * compliant binaries with varying levels of system initialization + * support. + */ + +__entry = DEFINED(__reset_vector) ? 0xbfc00000 : _start; +ENTRY(__entry) +OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradbigmips", "elf32-tradlittlemips") +GROUP(-lc -luhi -lgcc -lhal) +SEARCH_DIR(.) +__DYNAMIC = 0; +STARTUP(crt0.o) +/* Force the exception handler to be registered */ +EXTERN(__register_excpt_handler) +/* Force the exception handler to be included in the link */ +EXTERN(__exception_entry) +/* + * Require verbose exceptions. This can be changed to pull in + * __exception_handle_quiet to reduce code size but be less + * informative + */ +EXTERN(__exception_handle_verbose) +/* Force the interrupt handlers to tbe included in the link */ +EXTERN(__isr_vec) +/* Require the UHI getargs support */ +EXTERN(__getargs) + +/* + * Set the location of the top of the stack. A value of 0 means + * that it will be automatically placed at the highest address + * available as described by the __memory_* setttings + */ +PROVIDE (__stack = 0); + +/* Size of the memory returned by _get_ram_range */ +PROVIDE (__memory_size = 3M); + +/* Base of the memory returned by _get_ram_range */ +PROVIDE (__memory_base = 0x80000000); + +/* Stride length for tlb software invalidate for tlbinvf + * (mipsXXr3+). Some MIPS implementations may layout the sets/ways + * differently in the index register. Either sets LSB or ways LSB. + * + * By setting this to 1 we presume that sets come first. The default boot + * code will decrement this value from the Number of TLB entries. + */ +PROVIDE (__tlb_stride_length = 1); + +/* By default, XPA is not used even if available. To enable XPA, + * __enable_xpa should be 1. + */ +PROVIDE (__enable_xpa = 0); + +/* + * 0 = Do not use exception handler present in boot for UHI + * 1 = Use exception handler present in boot for UHI if BEV is 0 at + * startup + * 2 = Always use exception handler present in boot for UHI + */ +PROVIDE (__use_excpt_boot = 1); +/* + * Include the code to be able to return to boot context. This is + * necessary if __use_excpt_boot != 0. + */ +EXTERN (__register_excpt_boot); + +ASSERT (DEFINED(__register_excpt_boot) || __use_excpt_boot == 0, + "Registration for boot context is required for UHI chaining") + +/* Control if subnormal floating-point values are flushed to zero in + hardware. This applies to both FPU and MSA operations. */ +PROVIDE (__flush_to_zero = 1); + +/* Set up the public symbols depending on whether the user has chosen + quiet or verbose exception handling above */ +EXTERN (__exception_handle); +PROVIDE(__exception_handle = (DEFINED(__exception_handle_quiet) + ? __exception_handle_quiet + : __exception_handle_verbose)); +PROVIDE(_mips_handle_exception = __exception_handle); + +/* + * Initalize some symbols to be zero so we can reference them in the + * crt0 without core dumping. These functions are all optional, but + * we do this so we can have our crt0 always use them if they exist. + * This is so BSPs work better when using the crt0 installed with gcc. + * We have to initalize them twice, so we multiple object file + * formats, as some prepend an underscore. + */ +PROVIDE (hardware_exit_hook = 0); +PROVIDE (hardware_hazard_hook = 0); +PROVIDE (hardware_init_hook = 0); +PROVIDE (software_init_hook = 0); + +/* The default base address for application code is 0x80200000 which + leaves 2M of space at the start of KSEG0 for a bootloader. */ +PROVIDE (__app_start = DEFINED(__reset_vector) ? 0x80000000 : 0x80200000); +/* Set default vector spacing to 32 bytes. */ +PROVIDE (__isr_vec_space = 32); +/* Leave space for 9 vector entries by default. 8 entry points and one + fallback handler. */ +PROVIDE (__isr_vec_count = 9); +/* + * The start of flash must be set if including boot code. By default + * the use of boot code will mean that application code is copied + * from flash to RAM at runtime before being executed. + */ +PROVIDE (__flash_start = DEFINED(__reset_vector) ? 0xbfc00000 : __app_start); + +SECTIONS +{ + /* Start of bootrom */ + .bootrom 0x9fc00000 : /* Runs uncached (from 0x9fc00000) until I$ is + initialized. */ + AT (__flash_start) + { + *(.reset) /* Reset entry point. */ + *(.boot) /* Boot code. */ + . = ALIGN(8); + } = 0 + + PROVIDE (__flash_app_start = SIZEOF(.bootrom) + __flash_start); + + /* Start of the application */ + .exception_vector ALIGN(__app_start, 0x1000) : + AT (__flash_app_start) + { + __excpt_ebase = ABSOLUTE(.); + __base = .; + KEEP(* (.text.__exception_entry)) + . = __base + 0x200; + KEEP(* (SORT(.text.__isr_vec*))) + /* Leave space for all the vector entries */ + . = __base + 0x200 + (__isr_vec_space * __isr_vec_count); + ASSERT(__isr_vec_space == (DEFINED(__isr_vec_sw0) + ? __isr_vec_sw1 - __isr_vec_sw0 + : __isr_vec_space), + "Actual ISR vector spacing does not match __isr_vec_space"); + ASSERT(__base + 0x200 == (DEFINED(__isr_vec_sw0) + ? __isr_vec_sw0 & 0xfffffffe : __base + 0x200), + "__isr_vec_sw0 is not placed at EBASE + 0x200"); + . = ALIGN(8); + } = 0 + + .text : { + _ftext = . ; + PROVIDE (eprol = .); + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + *(.mips16.fn.*) + *(.mips16.call.*) + } + .init : { + KEEP (*(.init)) + } + .fini : { + KEEP (*(.fini)) + } + .rel.sdata : { + PROVIDE (__runtime_reloc_start = .); + *(.rel.sdata) + PROVIDE (__runtime_reloc_stop = .); + } + PROVIDE (etext = .); + _etext = .; + + .eh_frame_hdr : { *(.eh_frame_hdr) } + .eh_frame : { KEEP (*(.eh_frame)) } + .gcc_except_table : { *(.gcc_except_table) } + .jcr : { KEEP (*(.jcr)) } + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + + KEEP (*crtbegin.o(.ctors)) + + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } + + . = .; + .MIPS.abiflags : { + __MIPS_abiflags_start = .; + *(.MIPS.abiflags) + __MIPS_abiflags_end = .; + } + .rodata : { + *(.rdata) + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + } + _fdata = ALIGN(16); + .data : { + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + } + . = ALIGN(8); + _gp = . + 0x8000; + __global = _gp; + .lit8 : { + *(.lit8) + } + .lit4 : { + *(.lit4) + } + .sdata : { + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + } + . = ALIGN(4); + PROVIDE (edata = .); + _edata = .; + _fbss = .; + .sbss : { + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + } + .bss : { + _bss_start = . ; + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + } + + . = ALIGN(4); + PROVIDE (end = .); + _end = .; + /* Now place the data that is only needed within start.S and can be + overwritten by the heap. */ + .startdata : { + *(.startdata) + } + + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to + the beginning of the section so we begin them at 0. */ + + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_ranges 0 : { *(.debug_ranges) } + + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + /* Special sections generated by gcc */ + /* Newer GNU linkers strip by default */ + .mdebug.abi32 0 : { KEEP(*(.mdebug.abi32)) } + .mdebug.abiN32 0 : { KEEP(*(.mdebug.abiN32)) } + .mdebug.abi64 0 : { KEEP(*(.mdebug.abi64)) } + .mdebug.abiO64 0 : { KEEP(*(.mdebug.abiO64)) } + .mdebug.eabi32 0 : { KEEP(*(.mdebug.eabi32)) } + .mdebug.eabi64 0 : { KEEP(*(.mdebug.eabi64)) } + .gcc_compiled_long32 0 : { KEEP(*(.gcc_compiled_long32)) } + .gcc_compiled_long64 0 : { KEEP(*(.gcc_compiled_long64)) } +} http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/61a406f1/hw/hal/include/hal/hal_uart.h ---------------------------------------------------------------------- diff --git a/hw/hal/include/hal/hal_uart.h b/hw/hal/include/hal/hal_uart.h index e0cffa9..bfbcbd9 100644 --- a/hw/hal/include/hal/hal_uart.h +++ b/hw/hal/include/hal/hal_uart.h @@ -26,6 +26,7 @@ extern "C" { #include <inttypes.h> + /* * Function prototype for UART driver to ask for more data to send. * Returns -1 if no more data is available for TX. http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/61a406f1/hw/mcu/mips/danube/include/mcu/mips.h ---------------------------------------------------------------------- diff --git a/hw/mcu/mips/danube/include/mcu/mips.h b/hw/mcu/mips/danube/include/mcu/mips.h new file mode 100644 index 0000000..d1d9824 --- /dev/null +++ b/hw/mcu/mips/danube/include/mcu/mips.h @@ -0,0 +1,25 @@ +/** + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#ifndef __MCU_MIPS_H__ +#define __MCU_MIPS_H__ + +#define OS_TICKS_PER_SEC (1000) + +#endif /* __MCU_CORTEX_M4_H__ */ http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/61a406f1/hw/mcu/mips/danube/include/mcu/mips_bsp.h ---------------------------------------------------------------------- diff --git a/hw/mcu/mips/danube/include/mcu/mips_bsp.h b/hw/mcu/mips/danube/include/mcu/mips_bsp.h new file mode 100644 index 0000000..01d75f4 --- /dev/null +++ b/hw/mcu/mips/danube/include/mcu/mips_bsp.h @@ -0,0 +1,24 @@ +/** + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ +#ifndef H_MIPS_BSP_ +#define H_MIPS_BSP_ + +extern const struct hal_flash native_flash_dev; + +#endif /* H_NATIVE_BSP_ */ http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/61a406f1/hw/mcu/mips/danube/include/mcu/mips_hal.h ---------------------------------------------------------------------- diff --git a/hw/mcu/mips/danube/include/mcu/mips_hal.h b/hw/mcu/mips/danube/include/mcu/mips_hal.h new file mode 100644 index 0000000..f407e0c --- /dev/null +++ b/hw/mcu/mips/danube/include/mcu/mips_hal.h @@ -0,0 +1,38 @@ +/** + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +/* This file defines the HAL implementations within this MCU */ + +#ifndef MIPS_HAL_H +#define MIPS_HAL_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Helper functions to enable/disable interrupts. */ +#define __HAL_DISABLE_INTERRUPTS(__os_sr) do {__os_sr = _mips_intdisable();} while(0) + +#define __HAL_ENABLE_INTERRUPTS(__os_sr) _mips_intrestore(__os_sr) + +#ifdef __cplusplus +} +#endif + +#endif /* MCU_HAL_H */ http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/61a406f1/hw/mcu/mips/danube/pkg.yml ---------------------------------------------------------------------- diff --git a/hw/mcu/mips/danube/pkg.yml b/hw/mcu/mips/danube/pkg.yml new file mode 100644 index 0000000..72736e5 --- /dev/null +++ b/hw/mcu/mips/danube/pkg.yml @@ -0,0 +1,30 @@ +# +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +pkg.name: hw/mcu/mips/danube +pkg.description: MCU definition for MIPS danube chips. +pkg.author: "Apache Mynewt <[email protected]>" +pkg.homepage: "http://mynewt.apache.org/"; +pkg.keywords: + - mips + - danube + +pkg.deps: + - hw/hal + - compiler/mips http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/61a406f1/hw/mcu/mips/danube/src/gic.c ---------------------------------------------------------------------- diff --git a/hw/mcu/mips/danube/src/gic.c b/hw/mcu/mips/danube/src/gic.c new file mode 100644 index 0000000..283bbd9 --- /dev/null +++ b/hw/mcu/mips/danube/src/gic.c @@ -0,0 +1,124 @@ +#include "gic.h" + +#include <mips/cpu.h> +#include <mips/hal.h> + +#include <string.h> + +static const uint32_t GIC_BASE = 0x1bdc0000ul; + +static const uint32_t GIC_EN = 1; +static const uint32_t GIC_MAP_TO_PIN = 1 << 31; + +static const uint32_t GLOBAL_CONTROL_OFF = 0x0000; +static const uint32_t GCR_GIC_BASE_OFF = 0x0080; + +static uint32_t* _GCR = NULL; +static uint32_t* _GIC = NULL; + +static inline void +gic_enable(void) +{ + _GCR[0x80 / sizeof(uint32_t)] |= GIC_EN; +} + +static inline void +gic_disable(void) +{ + _GCR[0x80 / sizeof(uint32_t)] &= ~GIC_EN; +} + +static uint32_t* +gic_sh_map_vpe(uint32_t n) +{ + return &_GIC[(0x2000 + (n * 0x0020)) / sizeof(uint32_t)]; +} + +static uint32_t* +gic_sh_map_pin(uint32_t n) +{ + return &_GIC[(0x0500 + (n * 0x0004)) / sizeof(uint32_t)]; +} + +void +gic_interrupt_set(uint32_t n) +{ + _GIC[(0x380 / sizeof(uint32_t)) + (n / 32)] = 1ul << (n % 32); +} + +void +gic_interrupt_reset(uint32_t n) +{ + _GIC[(0x300 / sizeof(uint32_t)) + (n / 32)] = 1ul << (n % 32); +} + +void +gic_interrupt_active_high(uint32_t n) +{ + _GIC[(0x100 / sizeof(uint32_t)) + (n / 32)] = 1ul << (n % 32); +} + +void +gic_interrupt_active_low(uint32_t n) +{ + _GIC[(0x100 / sizeof(uint32_t)) + (n / 32)] &= ~(1ul << (n % 32)); +} + +int +gic_interrupt_is_enabled(uint32_t n) +{ + return !!(_GIC[(0x400 / sizeof(uint32_t)) + (n / 32)] & (1ul << (n % 32))); +} + +int +gic_interrupt_poll(uint32_t n) +{ + return !!(_GIC[(0x480 / sizeof(uint32_t)) + (n / 32)] & (1ul << (n % 32))); +} + +void +gic_map(int int_no, uint8_t vpe, uint8_t pin) +{ + /* map UART0 to HW interrupt 0 */ + *gic_sh_map_vpe(int_no) = 1 << vpe; + *gic_sh_map_pin(int_no) = GIC_MAP_TO_PIN | pin; + /* enable interrupt in status register */ + mips_bissr(0x400 << pin); +} + +void +gic_unmap(int int_no, uint8_t pin) +{ + /* unmap UART0 from HW interrupt 0 */ + *gic_sh_map_vpe(int_no) = 0; + *gic_sh_map_pin(int_no) = 0; + /* disable interrupt in status register */ + mips_bicsr(0x400 << pin); +} + +static void +gic_place(uint32_t base) +{ + base &= ~GIC_EN; + _GCR[0x80 / sizeof(uint32_t)] &= GIC_EN; + _GCR[0x80 / sizeof(uint32_t)] |= base; + _GIC = PA_TO_KVA1(base); +} + +int +gic_init(void) +{ + /* Check for GCR and get GIC location */ + if (!((mips32_getconfig0() & CFG0_M) && (mips32_getconfig1() & CFG1_M) + && (mips32_getconfig2() & CFG2_M) + && (mips32_getconfig3() & CFG3_CMGCR))) { + return -1; + } + + /* get GCR base address */ + _GCR = PA_TO_KVA1((mips32_get_c0(C0_CMGCRBASE) & 0x0ffffc00) << 4); + gic_place(GIC_BASE); + gic_enable(); + + return 0; +} http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/61a406f1/hw/mcu/mips/danube/src/gic.h ---------------------------------------------------------------------- diff --git a/hw/mcu/mips/danube/src/gic.h b/hw/mcu/mips/danube/src/gic.h new file mode 100644 index 0000000..f855566 --- /dev/null +++ b/hw/mcu/mips/danube/src/gic.h @@ -0,0 +1,16 @@ +#ifndef H_GIC_H_ +#define H_GIC_H_ + +#include <stdint.h> + +void gic_interrupt_set(uint32_t n); +void gic_interrupt_reset(uint32_t n); +void gic_interrupt_active_high(uint32_t n); +void gic_interrupt_active_low(uint32_t n); +int gic_interrupt_is_enabled(uint32_t n); +int gic_interrupt_poll(uint32_t n); +void gic_map(int int_no, uint8_t vpe, uint8_t pin); +void gic_unmap(int int_no, uint8_t pin); +int gic_init(void); + +#endif http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/61a406f1/hw/mcu/mips/danube/src/hal_cputime2.c ---------------------------------------------------------------------- diff --git a/hw/mcu/mips/danube/src/hal_cputime2.c b/hw/mcu/mips/danube/src/hal_cputime2.c new file mode 100644 index 0000000..373be1c --- /dev/null +++ b/hw/mcu/mips/danube/src/hal_cputime2.c @@ -0,0 +1,99 @@ +/** + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ +#include <stdint.h> +#include <assert.h> +#include "hal/hal_cputime.h" + +/* XXX: + * - Must determine how to set priority of cpu timer interrupt + * - Determine if we should use a mutex as opposed to disabling interrupts + * - Should I use a macro for the timer being used? This is so I can + * easily change the timer from 2 to 5? What about compare channel? + * - Sync to OSTIME. + */ + +void +cputime_disable_ocmp(void) +{ +} + +/** + * cputime set ocmp + * + * Set the OCMP used by the cputime module to the desired cputime. + * + * @param timer Pointer to timer. + */ +void +cputime_set_ocmp(struct cpu_timer *timer) +{ +} + +/** + * tim5 isr + * + * This is the global timer interrupt routine. + * + */ +/*static void +cputime_isr(void) +{ +} +*/ +/** + * cputime hw init + * + * Initialize the cputime hw. This should be called only once and should be + * called before the hardware timer is used. + * + * @param clock_freq The desired cputime frequency, in hertz (Hz). + * + * @return int 0 on success; -1 on error. + */ +int +cputime_hw_init(uint32_t clock_freq) +{ + return 0; +} + +/** + * cputime get64 + * + * Returns cputime as a 64-bit number. + * + * @return uint64_t The 64-bit representation of cputime. + */ +uint64_t +cputime_get64(void) +{ + return 0; +} + +/** + * cputime get32 + * + * Returns the low 32 bits of cputime. + * + * @return uint32_t The lower 32 bits of cputime + */ +uint32_t +cputime_get32(void) +{ + return 0; +} http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/61a406f1/hw/mcu/mips/danube/src/hal_os_tick.c ---------------------------------------------------------------------- diff --git a/hw/mcu/mips/danube/src/hal_os_tick.c b/hw/mcu/mips/danube/src/hal_os_tick.c new file mode 100644 index 0000000..8fc68d6 --- /dev/null +++ b/hw/mcu/mips/danube/src/hal_os_tick.c @@ -0,0 +1,36 @@ +/** + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include <assert.h> +#include <os/os.h> +#include <hal/hal_os_tick.h> + +/* + * XXX implement tickless mode. + */ +void +os_tick_idle(os_time_t ticks) +{ + OS_ASSERT_CRITICAL(); +} + +void +os_tick_init(uint32_t os_ticks_per_sec, int prio) +{ +} http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/61a406f1/hw/mcu/mips/danube/src/hal_system.c ---------------------------------------------------------------------- diff --git a/hw/mcu/mips/danube/src/hal_system.c b/hw/mcu/mips/danube/src/hal_system.c new file mode 100644 index 0000000..44145fc --- /dev/null +++ b/hw/mcu/mips/danube/src/hal_system.c @@ -0,0 +1,41 @@ +/** + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include "hal/hal_system.h" + +#include <stdint.h> + +void +system_reset(void) +{ + while (1) { + if (system_debugger_connected()) { + /* + * If debugger is attached, breakpoint here. + */ + } + /* XXX: NVIC_SystemReset(); */ + } +} + +int +system_debugger_connected(void) +{ + return 0; +} http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/61a406f1/hw/mcu/mips/danube/src/hal_uart.c ---------------------------------------------------------------------- diff --git a/hw/mcu/mips/danube/src/hal_uart.c b/hw/mcu/mips/danube/src/hal_uart.c new file mode 100644 index 0000000..0b40ec0 --- /dev/null +++ b/hw/mcu/mips/danube/src/hal_uart.c @@ -0,0 +1,300 @@ +/** + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include "hal/hal_uart.h" +#include "bsp/bsp.h" +#include "mcu/mips_hal.h" +#include <assert.h> +#include <stdlib.h> + +#include <mips/cpu.h> +#include <mips/hal.h> + +#include "gic.h" + +static const uint32_t UART_0_INT_NO = 24; +static const uint32_t UART_1_INT_NO = 25; + +/* base values for the below functions */ +static uint32_t* const UART_0_BASE = (uint32_t* const)0xb8101400; +static uint32_t* const UART_1_BASE = (uint32_t* const)0xb8101500; +static const uint32_t UART_CLOCK_FREQ = 1843200; + +enum e_uart_regs { + CR_UART_RBR_THR_DLL = 0, + CR_UART_IER_DLH, + CR_UART_IIR_FCR, + CR_UART_LCR, + CR_UART_MCR, + CR_UART_LSR, + CR_UART_MSR, + CR_UART_SCRATCH, + CR_UART_SOFT_RESET, + CR_UART_ACC_BUF_STATUS +}; + +enum e_uart_lsr_bits { + CR_UART_LSR_DR = 1, + CR_UART_LSR_OE = 1 << 1, + CR_UART_LSR_PE = 1 << 2, + CR_UART_LSR_FE = 1 << 3, + CR_UART_LSR_BI = 1 << 4, + CR_UART_LSR_THRE = 1 << 5, + CR_UART_LSR_TEMT = 1 << 6, + CR_UART_LSR_RXFER = 1 << 7 +}; + +enum e_uart_lcr_bits { + CR_UART_LCR_WLS = 3, + CR_UART_LCR_STOPB = 1 << 2, + CR_UART_LCR_PEN = 1 << 3, + CR_UART_LCR_EPS = 1 << 4, + CR_UART_LCR_STPR = 1 << 5, + CR_UART_LCR_BREAK = 1 << 6, + CR_UART_LCR_DLAB = 1 << 7 +}; + +static inline uint32_t* +uart_reg(int port, enum e_uart_regs offset) +{ + switch (port) { + case 0: + return UART_0_BASE + offset; + case 1: + return UART_1_BASE + offset; + } + return 0; +} + +static inline uint32_t +uart_reg_read(int port, enum e_uart_regs offset) +{ + return *uart_reg(port, offset); +} + +static inline void +uart_reg_write(int port, enum e_uart_regs offset, uint32_t data) +{ + *uart_reg(port, offset) = data; +} + +struct hal_uart { + volatile uint8_t u_rx_stall:1; + volatile uint8_t u_rx_data; + hal_uart_rx_char u_rx_func; + hal_uart_tx_char u_tx_func; + hal_uart_tx_done u_tx_done; + void *u_func_arg; +}; +static struct hal_uart uarts[UART_CNT]; + +int +hal_uart_init_cbs(int port, hal_uart_tx_char tx_func, hal_uart_tx_done tx_done, + hal_uart_rx_char rx_func, void *arg) +{ + uarts[port].u_rx_func = rx_func; + uarts[port].u_tx_func = tx_func; + uarts[port].u_tx_done = tx_done; + uarts[port].u_func_arg = arg; + return 0; +} + +static void +uart_irq_handler(int port) +{ + uint8_t lsr = uart_reg_read(1, CR_UART_LSR); + if (lsr & CR_UART_LSR_RXFER) { + /* receive error */ + if (lsr & CR_UART_LSR_BI) { + /* break */ + } + if (lsr & CR_UART_LSR_FE) { + /* framing error */ + } + if (lsr & CR_UART_LSR_PE) { + /* parity */ + } + } + if (lsr & CR_UART_LSR_DR) { + /* data ready */ + uarts[port].u_rx_data = uart_reg_read(port, CR_UART_RBR_THR_DLL); + int c = uarts[port].u_rx_func(uarts[port].u_func_arg, + uarts[port].u_rx_data); + if (c < 0) { + /* disable rx interrupt */ + uart_reg_write(port, CR_UART_IER_DLH, uart_reg_read(1, + CR_UART_IER_DLH) & ~1); + uarts[port].u_rx_stall = 1; + } + } + if (lsr & CR_UART_LSR_THRE) { + /* transmit holding reg empty */ + int c = uarts[port].u_tx_func(uarts[port].u_func_arg); + if (c < 0) { + /* disable tx interrupt */ + uart_reg_write(port, CR_UART_IER_DLH, uart_reg_read(1, + CR_UART_IER_DLH) & ~2); + /* call tx done cb */ + if (uarts[port].u_tx_done) { + uarts[port].u_tx_done(uarts[port].u_func_arg); + } + } else { + /* write char out */ + uart_reg_write(port, CR_UART_RBR_THR_DLL, (uint32_t)c & 0xff); + } + } +} + +void __attribute__((interrupt, keep_interrupts_masked)) +_mips_isr_hw0(void) +{ + uart_irq_handler(0); +} + +void __attribute__((interrupt, keep_interrupts_masked)) +_mips_isr_hw1(void) +{ + uart_irq_handler(1); +} + +void +hal_uart_start_rx(int port) +{ + if (uarts[port].u_rx_stall) { + /* recover saved data */ + reg_t sr; + __HAL_DISABLE_INTERRUPTS(sr); + int c = uarts[port].u_rx_func(uarts[port].u_func_arg, + uarts[port].u_rx_data); + if (c >= 0) { + uarts[port].u_rx_stall = 0; + /* enable rx interrupt */ + uart_reg_write(port, CR_UART_IER_DLH, 1); + } + __HAL_ENABLE_INTERRUPTS(sr); + } +} + +void +hal_uart_start_tx(int port) +{ + uart_reg_write(port, CR_UART_IER_DLH, uart_reg_read(port, + CR_UART_IER_DLH) | 2); +} + +void +hal_uart_blocking_tx(int port, uint8_t data) +{ + /* write to transmit holding register */ + uart_reg_write(port, CR_UART_RBR_THR_DLL, data); + /* wait for transmit holding register to be empty */ + while(!(uart_reg_read(port, CR_UART_LSR) & CR_UART_LSR_THRE)) { + } +} + +int +hal_uart_config(int port, int32_t baudrate, uint8_t databits, uint8_t stopbits, + enum hal_uart_parity parity, enum hal_uart_flow_ctl flow_ctl) +{ + /* XXX: flow control currently unsupported */ + (void) flow_ctl; + uarts[port].u_rx_stall = 0; + + /* work out divisor */ + uint16_t divisor = (UART_CLOCK_FREQ + (baudrate << 3)) / (baudrate << 4); + /* write to divisor regs */ + uart_reg_write(port, CR_UART_LCR, CR_UART_LCR_DLAB); + uart_reg_write(port, CR_UART_RBR_THR_DLL, divisor & 0xff); + uart_reg_write(port, CR_UART_IER_DLH, divisor >> 8); + /* write to config regs */ + + if ((databits < 5) || (databits > 8) || (stopbits < 1) || (stopbits > 2)) { + return -1; + } + uint8_t value = ((databits - 5) & 3) | ((stopbits << 1) & (1 << 2)); + switch (parity) { + case HAL_UART_PARITY_NONE: + break; + case HAL_UART_PARITY_ODD: + value |= 1 << 3; + break; + case HAL_UART_PARITY_EVEN: + value |= (1 << 3) | (1 << 4); + break; + default: + return -1; + } + uart_reg_write(port, CR_UART_LCR, value); + uart_reg_write(port, CR_UART_MCR, 0); + + /* init gic, there shouldn't be any harm in calling this multiple times */ + if (gic_init() != 0) { + return -1; + } + + switch(port) { + case 0: + /* map UART0 to HW interrupt 0 */ + gic_map(UART_0_INT_NO, 0, port); + gic_interrupt_active_high(UART_0_INT_NO); + /* enable UART0 interrupt */ + gic_interrupt_set(UART_0_INT_NO); + break; + case 1: + /* map UART1 to HW interrupt 1 */ + gic_map(UART_1_INT_NO, 0, port); + gic_interrupt_active_high(UART_1_INT_NO); + /* enable UART1 interrupt */ + gic_interrupt_set(UART_1_INT_NO); + break; + default: + return -1; + } + + /* enable rx interrupt */ + uart_reg_write(port, CR_UART_IER_DLH, 1); + return 0; +} + +int +hal_uart_close(int port) +{ + /* disable gic interrupts */ + switch(port) { + case 0: + /* unmap UART0 from HW interrupt 0 */ + gic_unmap(UART_0_INT_NO, port); + /* disable UART0 interrupt */ + gic_interrupt_reset(UART_0_INT_NO); + break; + case 1: + /* unmap UART1 from HW interrupt 1 */ + gic_unmap(UART_1_INT_NO, port); + /* disable UART1 interrupt */ + gic_interrupt_reset(UART_1_INT_NO); + break; + default: + return -1; + } + + /* disable uart interrupts */ + uart_reg_write(port, CR_UART_IER_DLH, 0); + uart_reg_write(port, CR_UART_MCR, 0); + return 0; +} http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/61a406f1/libs/os/include/os/arch/mips/os/os_arch.h ---------------------------------------------------------------------- diff --git a/libs/os/include/os/arch/mips/os/os_arch.h b/libs/os/include/os/arch/mips/os/os_arch.h new file mode 100644 index 0000000..33afcee --- /dev/null +++ b/libs/os/include/os/arch/mips/os/os_arch.h @@ -0,0 +1,80 @@ +/** + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#ifndef _OS_ARCH_MIPS_H +#define _OS_ARCH_MIPS_H + +#include <stdint.h> +#include <mips/cpu.h> +#include <mips/m32c0.h> + +#include "mcu/mips.h" + +struct os_task; + +/* Run in priviliged or unprivileged Thread mode */ +/* only priv currently supported */ +#define OS_RUN_PRIV (0) +#define OS_RUN_UNPRIV (1) + +/* CPU status register */ +typedef uint32_t os_sr_t; +/* Stack type, aligned to a 32-bit word. */ +#define OS_STACK_PATTERN (0xdeadbeef) + +typedef uint32_t os_stack_t; +#define OS_ALIGNMENT (4) +#define OS_STACK_ALIGNMENT (8) + +/* + * Stack sizes for common OS tasks + */ +#define OS_SANITY_STACK_SIZE (64) +#define OS_IDLE_STACK_SIZE (64) + +#define OS_STACK_ALIGN(__nmemb) \ + (OS_ALIGN((__nmemb), OS_STACK_ALIGNMENT)) + +/* Enter a critical section, save processor state, and block interrupts */ +#define OS_ENTER_CRITICAL(__os_sr) do {__os_sr = _mips_intdisable();} while(0) + +/* Exit a critical section, restore processor state and unblock interrupts */ +#define OS_EXIT_CRITICAL(__os_sr) _mips_intrestore(__os_sr) +#define OS_IS_CRITICAL() ((mips_getsr() & 1) == 0) +#define OS_ASSERT_CRITICAL() assert(OS_IS_CRITICAL()) + +os_stack_t *os_arch_task_stack_init(struct os_task *, os_stack_t *, int); +void timer_handler(void); +void os_arch_ctx_sw(struct os_task *); +os_sr_t os_arch_save_sr(void); +void os_arch_restore_sr(os_sr_t); +int os_arch_in_critical(void); +void os_arch_init(void); +uint32_t os_arch_start(void); +os_error_t os_arch_os_init(void); +os_error_t os_arch_os_start(void); +void os_set_env(os_stack_t *); +void os_arch_init_task_stack(os_stack_t *sf); +void os_default_irq_asm(void); + +/* External function prototypes supplied by BSP */ +void os_bsp_systick_init(uint32_t os_ticks_per_sec, int prio); +void os_bsp_ctx_sw(void); + +#endif /* _OS_ARCH_ARM_H */ http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/61a406f1/libs/os/include/os/arch/sim-mips/os/os_arch.h ---------------------------------------------------------------------- diff --git a/libs/os/include/os/arch/sim-mips/os/os_arch.h b/libs/os/include/os/arch/sim-mips/os/os_arch.h new file mode 100644 index 0000000..d9570c8 --- /dev/null +++ b/libs/os/include/os/arch/sim-mips/os/os_arch.h @@ -0,0 +1,74 @@ +/** + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#ifndef _OS_ARCH_SIM_H +#define _OS_ARCH_SIM_H + +#include <mcu/mcu_sim.h> + +struct os_task; + +/* CPU status register */ +typedef unsigned int os_sr_t; +/* Stack type, aligned to a 32-bit word. */ +#define OS_STACK_PATTERN (0xdeadbeef) + +typedef unsigned int os_stack_t; +#define OS_ALIGNMENT (4) +#define OS_STACK_ALIGNMENT (16) + +/* + * Stack sizes for common OS tasks + */ +#define OS_SANITY_STACK_SIZE (1024) +#define OS_IDLE_STACK_SIZE (1024) + +/* + * The 'sim' architecture-specific code does not have as much control on + * stack usage as the real embedded architectures. + * + * For e.g. the space occupied by the signal handler frame on the task + * stack is entirely dependent on the host OS. + * + * Deal with this by scaling the stack size by a factor of 16. The scaling + * factor can be arbitrarily large because the stacks are allocated from + * BSS and thus don't add to either the executable size or resident + * memory. + */ +#define OS_STACK_ALIGN(__nmemb) \ + (OS_ALIGN(((__nmemb) * 16), OS_STACK_ALIGNMENT)) + +/* Enter a critical section, save processor state, and block interrupts */ +#define OS_ENTER_CRITICAL(__os_sr) (__os_sr = os_arch_save_sr()) +/* Exit a critical section, restore processor state and unblock interrupts */ +#define OS_EXIT_CRITICAL(__os_sr) (os_arch_restore_sr(__os_sr)) +#define OS_ASSERT_CRITICAL() (assert(os_arch_in_critical())) + +void _Die(char *file, int line); + +os_stack_t *os_arch_task_stack_init(struct os_task *, os_stack_t *, int); +void os_arch_ctx_sw(struct os_task *); +os_sr_t os_arch_save_sr(void); +void os_arch_restore_sr(os_sr_t sr); +int os_arch_in_critical(void); +os_error_t os_arch_os_init(void); +void os_arch_os_stop(void); +os_error_t os_arch_os_start(void); + +#endif /* _OS_ARCH_SIM_H */ http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/61a406f1/libs/os/src/arch/mips/asm/ctx.S ---------------------------------------------------------------------- diff --git a/libs/os/src/arch/mips/asm/ctx.S b/libs/os/src/arch/mips/asm/ctx.S new file mode 100644 index 0000000..c5a36fd --- /dev/null +++ b/libs/os/src/arch/mips/asm/ctx.S @@ -0,0 +1,189 @@ +/* + * Copyright 2016, Imagination Technologies Limited and/or its + * affiliated group companies. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. +*/ + +#include <mips/regdef.h> +#include <mips/asm.h> +#include <mips/cpu.h> +#include <mips/hal.h> + +# note that k0 is not saved when using these macros. + +# saves to location k0 +.macro _gpctx_save + REG_S $1, CTX_REG(1) (k0) + REG_S $2, CTX_REG(2) (k0) + REG_S $3, CTX_REG(3) (k0) + REG_S $4, CTX_REG(4) (k0) + REG_S $5, CTX_REG(5) (k0) + REG_S $6, CTX_REG(6) (k0) + REG_S $7, CTX_REG(7) (k0) + REG_S $8, CTX_REG(8) (k0) + REG_S $9, CTX_REG(9) (k0) + REG_S $10, CTX_REG(10) (k0) + REG_S $11, CTX_REG(11) (k0) + REG_S $12, CTX_REG(12) (k0) + REG_S $13, CTX_REG(13) (k0) + REG_S $14, CTX_REG(14) (k0) + REG_S $15, CTX_REG(15) (k0) + REG_S $16, CTX_REG(16) (k0) + REG_S $17, CTX_REG(17)(k0) + REG_S $18, CTX_REG(18)(k0) + REG_S $19, CTX_REG(19)(k0) + REG_S $20, CTX_REG(20)(k0) + REG_S $21, CTX_REG(21)(k0) + REG_S $22, CTX_REG(22)(k0) + REG_S $23, CTX_REG(23)(k0) + REG_S $24, CTX_REG(24)(k0) + REG_S $25, CTX_REG(25)(k0) + # k0 not saved + REG_S $27, CTX_REG(27)(k0) + REG_S $28, CTX_REG(28)(k0) + REG_S $29, CTX_REG(29)(k0) + REG_S $30, CTX_REG(30)(k0) + REG_S $31, CTX_REG(31)(k0) + PTR_S $0, CTX_LINK(k0) # Clear the link field + +#if (__mips_isa_rev < 6) + mfhi $9 + mflo $10 + REG_S $9, CTX_HI0(k0) + REG_S $10, CTX_LO0(k0) +#endif + + # cp0 + REG_S ra, CTX_EPC(k0) + PTR_MFC0 $9, C0_BADVADDR + REG_S $9, CTX_BADVADDR(k0) + mfc0 $9, C0_SR + sw $9, CTX_STATUS(k0) + + move $11, $0 + move $12, $0 + mfc0 $9, C0_CONFIG3 + ext $10, $9, CFG3_BP_SHIFT, 1 + beqz $10, 1f + mfc0 $11, C0_BADPINSTR +1: + ext $9, $9, CFG3_BI_SHIFT, 1 + beqz $9, 1f + mfc0 $12, C0_BADINSTR +1: + sw $11, CTX_BADPINSTR(k0) + sw $12, CTX_BADINSTR(k0) +.endm + +# restores from location a0 + +.macro _gpctx_load +#if (__mips_isa_rev < 6) + REG_L $9, CTX_HI0(a0) + REG_L $10, CTX_LO0(a0) + mthi $9 + mtlo $10 +#endif + + REG_L $1, CTX_REG(1)(a0) + REG_L $2, CTX_REG(2)(a0) + REG_L $3, CTX_REG(3)(a0) + # a0 is loaded last + REG_L $5, CTX_REG(5)(a0) + REG_L $6, CTX_REG(6)(a0) + REG_L $7, CTX_REG(7)(a0) + REG_L $8, CTX_REG(8)(a0) + REG_L $9, CTX_REG(9)(a0) + REG_L $10, CTX_REG(10)(a0) + REG_L $11, CTX_REG(11)(a0) + REG_L $12, CTX_REG(12)(a0) + REG_L $13, CTX_REG(13)(a0) + REG_L $14, CTX_REG(14)(a0) + REG_L $15, CTX_REG(15)(a0) + REG_L $16, CTX_REG(16)(a0) + REG_L $17, CTX_REG(17)(a0) + REG_L $18, CTX_REG(18)(a0) + REG_L $19, CTX_REG(19)(a0) + REG_L $20, CTX_REG(20)(a0) + REG_L $21, CTX_REG(21)(a0) + REG_L $22, CTX_REG(22)(a0) + REG_L $23, CTX_REG(23)(a0) + REG_L $24, CTX_REG(24)(a0) + REG_L $25, CTX_REG(25)(a0) + # restore k0 after interrupts have been disabled + REG_L $27, CTX_REG(27)(a0) + REG_L $28, CTX_REG(28)(a0) + # restore sp after interrupts have been disabled + REG_L $30, CTX_REG(30)(a0) + REG_L $31, CTX_REG(31)(a0) + + di + REG_L k0, CTX_EPC(a0) + PTR_MTC0 k0, C0_EPC + lw k0, CTX_STATUS(a0) + # STATUS here will have EXL set + mtc0 k0, C0_SR + ehb + + # restore k0 and sp as these may be overwritten by nested interrupts + REG_L $26, CTX_REG(26)(a0) + REG_L $29, CTX_REG(29)(a0) + # restore a0 last + REG_L $4, CTX_REG(4)(a0) +.endm + +.text +.global get_global_pointer +.ent get_global_pointer +get_global_pointer: + .set noat + move v0, gp + jr ra +.end + +.text +.global _mips_isr_sw0 +.ent _mips_isr_sw0 +_mips_isr_sw0: + /* context switch */ + .set noat + /* save k0 */ + REG_S $26, (CTX_REG(25) - CTX_SIZE) (sp) + addi k0, sp, 0 - CTX_SIZE + _gpctx_save /* save the context to sp - CTX_SIZE */ + .set at + lw t0, g_current_task /* get current task */ + beqz t0, 1f + sw k0, 0(t0) /* update stored sp */ +1: + lw t1, g_os_run_list /* get new task */ + sw t1, g_current_task /* g_current_task = g_os_run_list */ + lw a0, 0(t1) + .set noat + _gpctx_load /* update actual sp */ + eret +.end http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/61a406f1/libs/os/src/arch/mips/asm/excpt_isr.S ---------------------------------------------------------------------- diff --git a/libs/os/src/arch/mips/asm/excpt_isr.S b/libs/os/src/arch/mips/asm/excpt_isr.S new file mode 100644 index 0000000..dded29c --- /dev/null +++ b/libs/os/src/arch/mips/asm/excpt_isr.S @@ -0,0 +1,100 @@ +/* + * Copyright 2016, Imagination Technologies Limited and/or its + * affiliated group companies. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. +*/ + +# Keep each function in a separate named section +#define _FUNCTION_SECTIONS_ + +#include <mips/regdef.h> +#include <mips/asm.h> +#include <mips/cpu.h> + +#define VEC_SPACE (SZPTR * 8) + +LEAF(__isr_vec) + .set push + .set noat +AENT(__isr_vec_sw0) + j _mips_isr_sw0 +.org VEC_SPACE +AENT(__isr_vec_sw1) + j _mips_isr_sw1 +.org 2 * VEC_SPACE +AENT(__isr_vec_hw0) + j _mips_isr_hw0 +.org 3 * VEC_SPACE +AENT(__isr_vec_hw1) +.weak _mips_isr_hw1 + j _mips_isr_hw1 +.org 4 * VEC_SPACE +AENT(__isr_vec_hw2) + j _mips_isr_hw2 +.org 5 * VEC_SPACE +AENT(__isr_vec_hw3) + j _mips_isr_hw3 +.org 6 * VEC_SPACE +AENT(__isr_vec_hw4) + j _mips_isr_hw4 +.org 7 * VEC_SPACE +AENT(__isr_vec_hw5) + j _mips_isr_hw5 +.org 8 * VEC_SPACE +AENT(__isr_vec_fallback) + j _mips_interrupt + .set pop +END(__isr_vec) + +/* XXX: these are all pointelss, if there was a way to detect if a symbol is + defined elsewhere it could be fixed .ifdef does not seem to work for this */ + +.text +.weak _mips_isr_sw1 +_mips_isr_sw1: + j _mips_interrupt +.weak _mips_isr_hw0 +_mips_isr_hw0: + j _mips_interrupt +.weak _mips_isr_hw1 +_mips_isr_hw1: + j _mips_interrupt +.weak _mips_isr_hw2 +_mips_isr_hw2: + j _mips_interrupt +.weak _mips_isr_hw3 +_mips_isr_hw3: + j _mips_interrupt +.weak _mips_isr_hw4 +_mips_isr_hw4: + j _mips_interrupt +.weak _mips_isr_hw5 +_mips_isr_hw5: + j _mips_interrupt +.weak _mips_interrupt +_mips_interrupt: + j _mips_interrupt /* inf loop */ http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/61a406f1/libs/os/src/arch/mips/os_arch_mips.c ---------------------------------------------------------------------- diff --git a/libs/os/src/arch/mips/os_arch_mips.c b/libs/os/src/arch/mips/os_arch_mips.c new file mode 100644 index 0000000..3ca779b --- /dev/null +++ b/libs/os/src/arch/mips/os_arch_mips.c @@ -0,0 +1,201 @@ +/** + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include "os/os.h" +#include "os/os_arch.h" +#include <hal/hal_bsp.h> +#include <hal/hal_os_tick.h> + +#include "os_priv.h" + +#include <mips/hal.h> +#include <mips/uhi_syscalls.h> + +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void SysTick_Handler(void); + +/* XXX: determine how we will deal with running un-privileged */ +/* only priv currently supported */ +uint32_t os_flags = OS_RUN_PRIV; + +/* fucntion to call from syscall */ +void (* volatile os_ftc)(void) = 0; +extern struct os_task g_idle_task; +/* exception handler */ +void +_mips_handle_exception (struct gpctx* ctx, int exception) +{ + switch (exception) { + case EXC_SYS: + if (os_ftc != 0) { + os_ftc(); + os_ftc = 0; + return; + } + } + /* default handler for anything not handled above */ + __exception_handle(ctx, exception); +} + + +/* core timer interrupt */ +void __attribute__((interrupt, keep_interrupts_masked)) +_mips_isr_hw5(void) +{ + timer_handler(); +} + +static int +os_in_isr(void) +{ + /* check the EXL bit XXX: Actually, that breaks it for some reason. */ + return 0; //(mips_getsr() & (1 << 1)) ? 1 : 0; +} + +void +timer_handler(void) +{ + /* This actually does the context switch by calling the below function if + necessary */ + os_time_advance(1); +} + +void +os_arch_ctx_sw(struct os_task *t) +{ + if ((os_sched_get_current_task() != 0) && (t != 0)) + { + os_sched_ctx_sw_hook(t); + } + + /* trigger sw interrupt */ + mips_biscr(1 << 8); +} + +os_sr_t +os_arch_save_sr(void) +{ + os_sr_t sr; + OS_ENTER_CRITICAL(sr); + return sr; +} + +void +os_arch_restore_sr(os_sr_t isr_ctx) +{ + OS_EXIT_CRITICAL(isr_ctx); +} + +int +os_arch_in_critical(void) +{ + return OS_IS_CRITICAL(); +} + +reg_t get_global_pointer(void); + +os_stack_t * +os_arch_task_stack_init(struct os_task *t, os_stack_t *stack_top, int size) +{ + const size_t frame_size = sizeof(struct gpctx); + os_stack_t *s = stack_top - frame_size; + + struct gpctx ctx = { + .r = { + [3] = (reg_t)t->t_arg, + [27] = get_global_pointer(), + [28] = (reg_t)stack_top + }, + /* XXX: copying the status register from when the task was created + * seems like a modreately sensible thing to do? */ + .status = mips_getsr(), + .epc = (reg_t)t->t_func + }; + + /* copy struct onto the stack */ + *((struct gpctx*)s) = ctx; + + return (s); +} + +void +os_arch_init(void) +{ + os_init_idle_task(); +} + +os_error_t +os_arch_os_init(void) +{ + os_error_t err; + + err = OS_ERR_IN_ISR; + if (os_in_isr() == 0) { + err = OS_OK; + + /* Call bsp related OS initializations */ + bsp_init(); + + /* should be in kernel mode here */ + os_arch_init(); + } + return err; +} + +uint32_t +os_arch_start(void) +{ + struct os_task *t; + + /* Get the highest priority ready to run to set the current task */ + t = os_sched_next_task(); + + /* set the core timer compare register */ + /* XXX: take this magic number (for a 1ms tick from a 550MHz clock) and put + ** it in bsp or mcu somewhere + */ + mips_setcompare(275000); + + /* enable core timer and software0 interupts and global enable */ + mips_bissr((1 << 15) | (1 << 8) | 1); + + /* Mark the OS as started, right before we run our first task */ + g_os_started = 1; + + /* Perform context switch to first task */ + os_arch_ctx_sw(t); + + return (uint32_t)(t->t_arg); +} + +os_error_t +os_arch_os_start(void) +{ + os_error_t err; + + err = OS_ERR_IN_ISR; + if (os_in_isr() == 0) { // cause + err = OS_OK; + /* should be in kernel mode here */ + os_arch_start(); + } + + return err; +} http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/61a406f1/libs/os/src/arch/mips/os_fault.c ---------------------------------------------------------------------- diff --git a/libs/os/src/arch/mips/os_fault.c b/libs/os/src/arch/mips/os_fault.c new file mode 100644 index 0000000..8d89f54 --- /dev/null +++ b/libs/os/src/arch/mips/os_fault.c @@ -0,0 +1,123 @@ +/** + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include <console/console.h> +#include <hal/hal_system.h> +#ifdef COREDUMP_PRESENT +#include <coredump/coredump.h> +#endif +#include "os/os.h" + +#include <stdint.h> +#include <unistd.h> + +struct exception_frame { + uint32_t r0; + uint32_t r1; + uint32_t r2; + uint32_t r3; + uint32_t r12; + uint32_t lr; + uint32_t pc; + uint32_t psr; +}; + +struct trap_frame { + struct exception_frame *ef; + uint32_t r4; + uint32_t r5; + uint32_t r6; + uint32_t r7; + uint32_t r8; + uint32_t r9; + uint32_t r10; + uint32_t r11; + uint32_t lr; /* this LR holds EXC_RETURN */ +}; + +struct coredump_regs { + uint32_t r0; + uint32_t r1; + uint32_t r2; + uint32_t r3; + uint32_t r4; + uint32_t r5; + uint32_t r6; + uint32_t r7; + uint32_t r8; + uint32_t r9; + uint32_t r10; + uint32_t r11; + uint32_t r12; + uint32_t sp; + uint32_t lr; + uint32_t pc; + uint32_t psr; +}; + +void __assert_func(const char *file, int line, const char *func, const char *e); + +#ifdef COREDUMP_PRESENT +static void +trap_to_coredump(struct trap_frame *tf, struct coredump_regs *regs) +{ +} +#endif + +void +__assert_func(const char *file, int line, const char *func, const char *e) +{ + int sr; + + OS_ENTER_CRITICAL(sr); + (void)sr; + console_blocking_mode(); + console_printf("Assert %s; failed in %s:%d\n", e ? e : "", file, line); + if (system_debugger_connected()) { + /* + * If debugger is attached, breakpoint before the trap. + */ + } + system_reset(); +} + +void +os_default_irq(struct trap_frame *tf) +{ +#ifdef COREDUMP_PRESENT + struct coredump_regs regs; +#endif + + console_blocking_mode(); + console_printf("Unhandled interrupt, exception sp 0x%08lx\n", + (uint32_t)tf->ef); + console_printf(" r0:0x%08lx r1:0x%08lx r2:0x%08lx r3:0x%08lx\n", + tf->ef->r0, tf->ef->r1, tf->ef->r2, tf->ef->r3); + console_printf(" r4:0x%08lx r5:0x%08lx r6:0x%08lx r7:0x%08lx\n", + tf->r4, tf->r5, tf->r6, tf->r7); + console_printf(" r8:0x%08lx r9:0x%08lx r10:0x%08lx r11:0x%08lx\n", + tf->r8, tf->r9, tf->r10, tf->r11); + console_printf("r12:0x%08lx lr:0x%08lx pc:0x%08lx psr:0x%08lx\n", + tf->ef->r12, tf->ef->lr, tf->ef->pc, tf->ef->psr); +#ifdef COREDUMP_PRESENT + trap_to_coredump(tf, ®s); + coredump_dump(®s, sizeof(regs)); +#endif + system_reset(); +}
