http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a2993a9f/hw/mcu/nxp/mkw41z/include/mcu/MKW41Z4.h ---------------------------------------------------------------------- diff --git a/hw/mcu/nxp/mkw41z/include/mcu/MKW41Z4.h b/hw/mcu/nxp/mkw41z/include/mcu/MKW41Z4.h new file mode 100644 index 0000000..daed3e7 --- /dev/null +++ b/hw/mcu/nxp/mkw41z/include/mcu/MKW41Z4.h @@ -0,0 +1,12979 @@ +/* +** ################################################################### +** Processors: MKW41Z256VHT4 +** MKW41Z512VHT4 +** +** Compilers: Keil ARM C/C++ Compiler +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: MKW41Z512RM Rev. 0.1, 04/2016 +** Version: rev. 1.0, 2015-09-23 +** Build: b160720 +** +** Abstract: +** CMSIS Peripheral Access Layer for MKW41Z4 +** +** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: [email protected] +** +** Revisions: +** - rev. 1.0 (2015-09-23) +** Initial version. +** +** ################################################################### +*/ + +/*! + * @file MKW41Z4.h + * @version 1.0 + * @date 2015-09-23 + * @brief CMSIS Peripheral Access Layer for MKW41Z4 + * + * CMSIS Peripheral Access Layer for MKW41Z4 + */ + +#ifndef _MKW41Z4_H_ +#define _MKW41Z4_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ + + /* Device specific interrupts */ + DMA0_IRQn = 0, /**< DMA channel 0 transfer complete */ + DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */ + DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */ + DMA3_IRQn = 3, /**< DMA channel 3 transfer complete */ + Reserved20_IRQn = 4, /**< Reserved interrupt */ + FTFA_IRQn = 5, /**< Command complete and read collision */ + LVD_LVW_DCDC_IRQn = 6, /**< Low-voltage detect, low-voltage warning, DCDC */ + LLWU_IRQn = 7, /**< Low leakage wakeup Unit */ + I2C0_IRQn = 8, /**< I2C0 interrupt */ + I2C1_IRQn = 9, /**< I2C1 interrupt */ + SPI0_IRQn = 10, /**< SPI0 single interrupt vector for all sources */ + TSI0_IRQn = 11, /**< TSI0 single interrupt vector for all sources */ + LPUART0_IRQn = 12, /**< LPUART0 status and error */ + TRNG0_IRQn = 13, /**< TRNG0 interrupt */ + CMT_IRQn = 14, /**< CMT interrupt */ + ADC0_IRQn = 15, /**< ADC0 interrupt */ + CMP0_IRQn = 16, /**< CMP0 interrupt */ + TPM0_IRQn = 17, /**< TPM0 single interrupt vector for all sources */ + TPM1_IRQn = 18, /**< TPM1 single interrupt vector for all sources */ + TPM2_IRQn = 19, /**< TPM2 single interrupt vector for all sources */ + RTC_IRQn = 20, /**< RTC alarm */ + RTC_Seconds_IRQn = 21, /**< RTC seconds */ + PIT_IRQn = 22, /**< PIT interrupt */ + LTC0_IRQn = 23, /**< LTC0 interrupt */ + Radio_0_IRQn = 24, /**< BTLE, ZIGBEE, ANT, GENFSK interrupt 0 */ + DAC0_IRQn = 25, /**< DAC0 interrupt */ + Radio_1_IRQn = 26, /**< BTLE, ZIGBEE, ANT, GENFSK interrupt 1 */ + MCG_IRQn = 27, /**< MCG interrupt */ + LPTMR0_IRQn = 28, /**< LPTMR0 interrupt */ + SPI1_IRQn = 29, /**< SPI1 single interrupt vector for all sources */ + PORTA_IRQn = 30, /**< PORTA Pin detect */ + PORTB_PORTC_IRQn = 31 /**< PORTB and PORTC Pin detect */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M0 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration + * @{ + */ + +#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */ +#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ +#define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */ +#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ + +#include "core_cm0plus.h" /* Core Peripheral Access Layer */ +#include "system_MKW41Z4.h" /* Device specific configuration file +*/ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup edma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */ + kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */ + kDmaRequestMux0LPUART0Rx = 2|0x100U, /**< LPUART0 Receive. */ + kDmaRequestMux0LPUART0Tx = 3|0x100U, /**< LPUART0 Transmit. */ + kDmaRequestMux0Reserved4 = 4|0x100U, /**< Reserved4 */ + kDmaRequestMux0Reserved5 = 5|0x100U, /**< Reserved5 */ + kDmaRequestMux0Reserved6 = 6|0x100U, /**< Reserved6 */ + kDmaRequestMux0Reserved7 = 7|0x100U, /**< Reserved7 */ + kDmaRequestMux0Reserved8 = 8|0x100U, /**< Reserved8 */ + kDmaRequestMux0Reserved9 = 9|0x100U, /**< Reserved9 */ + kDmaRequestMux0Reserved10 = 10|0x100U, /**< Reserved10 */ + kDmaRequestMux0Reserved11 = 11|0x100U, /**< Reserved11 */ + kDmaRequestMux0Reserved12 = 12|0x100U, /**< Reserved12 */ + kDmaRequestMux0Reserved13 = 13|0x100U, /**< Reserved13 */ + kDmaRequestMux0Reserved14 = 14|0x100U, /**< Reserved14 */ + kDmaRequestMux0Reserved15 = 15|0x100U, /**< Reserved15 */ + kDmaRequestMux0SPI0Rx = 16|0x100U, /**< SPI0 Receive. */ + kDmaRequestMux0SPI0Tx = 17|0x100U, /**< SPI0 Transmit. */ + kDmaRequestMux0SPI1Rx = 18|0x100U, /**< SPI1 Receive. */ + kDmaRequestMux0SPI1Tx = 19|0x100U, /**< SPI1 Transmit. */ + kDmaRequestMux0LTC0InputFIFO = 20|0x100U, /**< LTC0 Input FIFO. */ + kDmaRequestMux0LTC0OutputFIFO = 21|0x100U, /**< LTC0 Output FIFO. */ + kDmaRequestMux0I2C0 = 22|0x100U, /**< I2C0. */ + kDmaRequestMux0I2C1 = 23|0x100U, /**< I2C1. */ + kDmaRequestMux0TPM0Channel0 = 24|0x100U, /**< TPM0 C0V. */ + kDmaRequestMux0TPM0Channel1 = 25|0x100U, /**< TPM0 C1V. */ + kDmaRequestMux0TPM0Channel2 = 26|0x100U, /**< TPM0 C2V. */ + kDmaRequestMux0TPM0Channel3 = 27|0x100U, /**< TPM0 C3V. */ + kDmaRequestMux0Reserved28 = 28|0x100U, /**< Reserved28 */ + kDmaRequestMux0Reserved29 = 29|0x100U, /**< Reserved29 */ + kDmaRequestMux0Reserved30 = 30|0x100U, /**< Reserved30 */ + kDmaRequestMux0Reserved31 = 31|0x100U, /**< Reserved31 */ + kDmaRequestMux0TPM1Channel0 = 32|0x100U, /**< TPM1 C0V. */ + kDmaRequestMux0TPM1Channel1 = 33|0x100U, /**< TPM1 C1V. */ + kDmaRequestMux0TPM2Channel0 = 34|0x100U, /**< TPM2 C0V. */ + kDmaRequestMux0TPM2Channel1 = 35|0x100U, /**< TPM2 C1V. */ + kDmaRequestMux0Reserved36 = 36|0x100U, /**< Reserved36 */ + kDmaRequestMux0Reserved37 = 37|0x100U, /**< Reserved37 */ + kDmaRequestMux0Reserved38 = 38|0x100U, /**< Reserved38 */ + kDmaRequestMux0Reserved39 = 39|0x100U, /**< Reserved39 */ + kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */ + kDmaRequestMux0Reserved41 = 41|0x100U, /**< Reserved41 */ + kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */ + kDmaRequestMux0Reserved43 = 43|0x100U, /**< Reserved43 */ + kDmaRequestMux0Reserved44 = 44|0x100U, /**< Reserved44 */ + kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */ + kDmaRequestMux0Reserved46 = 46|0x100U, /**< Reserved46 */ + kDmaRequestMux0CMT = 47|0x100U, /**< CMT. */ + kDmaRequestMux0Reserved48 = 48|0x100U, /**< Reserved48 */ + kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */ + kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */ + kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */ + kDmaRequestMux0Reserved52 = 52|0x100U, /**< Reserved52 */ + kDmaRequestMux0Reserved53 = 53|0x100U, /**< Reserved53 */ + kDmaRequestMux0TPM0Overflow = 54|0x100U, /**< TPM0. */ + kDmaRequestMux0TPM1Overflow = 55|0x100U, /**< TPM1. */ + kDmaRequestMux0TPM2Overflow = 56|0x100U, /**< TPM2. */ + kDmaRequestMux0TSI0 = 57|0x100U, /**< TSI0. */ + kDmaRequestMux0Reserved58 = 58|0x100U, /**< Reserved58 */ + kDmaRequestMux0Reserved59 = 59|0x100U, /**< Reserved59 */ + kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */ +} dma_request_source_t; + +/* @} */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */ + __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ + __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */ + __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */ + __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */ + __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */ + __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */ + __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */ + __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */ + __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */ + __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */ + __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */ + __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */ + __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */ + __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */ + __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */ + __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */ + __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */ + uint8_t RESERVED_0[4]; + __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */ + __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */ + __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */ + __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */ + __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ + __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ + __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/*! @name SC1 - ADC Status and Control Registers 1 */ +#define ADC_SC1_ADCH_MASK (0x1FU) +#define ADC_SC1_ADCH_SHIFT (0U) +#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK) +#define ADC_SC1_DIFF_MASK (0x20U) +#define ADC_SC1_DIFF_SHIFT (5U) +#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK) +#define ADC_SC1_AIEN_MASK (0x40U) +#define ADC_SC1_AIEN_SHIFT (6U) +#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK) +#define ADC_SC1_COCO_MASK (0x80U) +#define ADC_SC1_COCO_SHIFT (7U) +#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK) + +/* The count of ADC_SC1 */ +#define ADC_SC1_COUNT (2U) + +/*! @name CFG1 - ADC Configuration Register 1 */ +#define ADC_CFG1_ADICLK_MASK (0x3U) +#define ADC_CFG1_ADICLK_SHIFT (0U) +#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK) +#define ADC_CFG1_MODE_MASK (0xCU) +#define ADC_CFG1_MODE_SHIFT (2U) +#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK) +#define ADC_CFG1_ADLSMP_MASK (0x10U) +#define ADC_CFG1_ADLSMP_SHIFT (4U) +#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK) +#define ADC_CFG1_ADIV_MASK (0x60U) +#define ADC_CFG1_ADIV_SHIFT (5U) +#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK) +#define ADC_CFG1_ADLPC_MASK (0x80U) +#define ADC_CFG1_ADLPC_SHIFT (7U) +#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK) + +/*! @name CFG2 - ADC Configuration Register 2 */ +#define ADC_CFG2_ADLSTS_MASK (0x3U) +#define ADC_CFG2_ADLSTS_SHIFT (0U) +#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK) +#define ADC_CFG2_ADHSC_MASK (0x4U) +#define ADC_CFG2_ADHSC_SHIFT (2U) +#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK) +#define ADC_CFG2_ADACKEN_MASK (0x8U) +#define ADC_CFG2_ADACKEN_SHIFT (3U) +#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK) +#define ADC_CFG2_MUXSEL_MASK (0x10U) +#define ADC_CFG2_MUXSEL_SHIFT (4U) +#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK) + +/*! @name R - ADC Data Result Register */ +#define ADC_R_D_MASK (0xFFFFU) +#define ADC_R_D_SHIFT (0U) +#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK) + +/* The count of ADC_R */ +#define ADC_R_COUNT (2U) + +/*! @name CV1 - Compare Value Registers */ +#define ADC_CV1_CV_MASK (0xFFFFU) +#define ADC_CV1_CV_SHIFT (0U) +#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK) + +/*! @name CV2 - Compare Value Registers */ +#define ADC_CV2_CV_MASK (0xFFFFU) +#define ADC_CV2_CV_SHIFT (0U) +#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK) + +/*! @name SC2 - Status and Control Register 2 */ +#define ADC_SC2_REFSEL_MASK (0x3U) +#define ADC_SC2_REFSEL_SHIFT (0U) +#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK) +#define ADC_SC2_DMAEN_MASK (0x4U) +#define ADC_SC2_DMAEN_SHIFT (2U) +#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK) +#define ADC_SC2_ACREN_MASK (0x8U) +#define ADC_SC2_ACREN_SHIFT (3U) +#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK) +#define ADC_SC2_ACFGT_MASK (0x10U) +#define ADC_SC2_ACFGT_SHIFT (4U) +#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK) +#define ADC_SC2_ACFE_MASK (0x20U) +#define ADC_SC2_ACFE_SHIFT (5U) +#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK) +#define ADC_SC2_ADTRG_MASK (0x40U) +#define ADC_SC2_ADTRG_SHIFT (6U) +#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK) +#define ADC_SC2_ADACT_MASK (0x80U) +#define ADC_SC2_ADACT_SHIFT (7U) +#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK) + +/*! @name SC3 - Status and Control Register 3 */ +#define ADC_SC3_AVGS_MASK (0x3U) +#define ADC_SC3_AVGS_SHIFT (0U) +#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK) +#define ADC_SC3_AVGE_MASK (0x4U) +#define ADC_SC3_AVGE_SHIFT (2U) +#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK) +#define ADC_SC3_ADCO_MASK (0x8U) +#define ADC_SC3_ADCO_SHIFT (3U) +#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK) +#define ADC_SC3_CALF_MASK (0x40U) +#define ADC_SC3_CALF_SHIFT (6U) +#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK) +#define ADC_SC3_CAL_MASK (0x80U) +#define ADC_SC3_CAL_SHIFT (7U) +#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK) + +/*! @name OFS - ADC Offset Correction Register */ +#define ADC_OFS_OFS_MASK (0xFFFFU) +#define ADC_OFS_OFS_SHIFT (0U) +#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) + +/*! @name PG - ADC Plus-Side Gain Register */ +#define ADC_PG_PG_MASK (0xFFFFU) +#define ADC_PG_PG_SHIFT (0U) +#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK) + +/*! @name MG - ADC Minus-Side Gain Register */ +#define ADC_MG_MG_MASK (0xFFFFU) +#define ADC_MG_MG_SHIFT (0U) +#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK) + +/*! @name CLPD - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLPD_CLPD_MASK (0x3FU) +#define ADC_CLPD_CLPD_SHIFT (0U) +#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK) + +/*! @name CLPS - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLPS_CLPS_MASK (0x3FU) +#define ADC_CLPS_CLPS_SHIFT (0U) +#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK) + +/*! @name CLP4 - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLP4_CLP4_MASK (0x3FFU) +#define ADC_CLP4_CLP4_SHIFT (0U) +#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK) + +/*! @name CLP3 - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLP3_CLP3_MASK (0x1FFU) +#define ADC_CLP3_CLP3_SHIFT (0U) +#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK) + +/*! @name CLP2 - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLP2_CLP2_MASK (0xFFU) +#define ADC_CLP2_CLP2_SHIFT (0U) +#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK) + +/*! @name CLP1 - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLP1_CLP1_MASK (0x7FU) +#define ADC_CLP1_CLP1_SHIFT (0U) +#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK) + +/*! @name CLP0 - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLP0_CLP0_MASK (0x3FU) +#define ADC_CLP0_CLP0_SHIFT (0U) +#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK) + +/*! @name CLMD - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLMD_CLMD_MASK (0x3FU) +#define ADC_CLMD_CLMD_SHIFT (0U) +#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK) + +/*! @name CLMS - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLMS_CLMS_MASK (0x3FU) +#define ADC_CLMS_CLMS_SHIFT (0U) +#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK) + +/*! @name CLM4 - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLM4_CLM4_MASK (0x3FFU) +#define ADC_CLM4_CLM4_SHIFT (0U) +#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK) + +/*! @name CLM3 - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLM3_CLM3_MASK (0x1FFU) +#define ADC_CLM3_CLM3_SHIFT (0U) +#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK) + +/*! @name CLM2 - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLM2_CLM2_MASK (0xFFU) +#define ADC_CLM2_CLM2_SHIFT (0U) +#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK) + +/*! @name CLM1 - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLM1_CLM1_MASK (0x7FU) +#define ADC_CLM1_CLM1_SHIFT (0U) +#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK) + +/*! @name CLM0 - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLM0_CLM0_MASK (0x3FU) +#define ADC_CLM0_CLM0_SHIFT (0U) +#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK) + + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC0 base address */ +#define ADC0_BASE (0x4003B000u) +/** Peripheral ADC0 base pointer */ +#define ADC0 ((ADC_Type *)ADC0_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { ADC0_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { ADC0 } +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn } + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ANT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ANT_Peripheral_Access_Layer ANT Peripheral Access Layer + * @{ + */ + +/** ANT - Register Layout Typedef */ +typedef struct { + __IO uint32_t IRQ_CTRL; /**< IRQ CONTROL, offset: 0x0 */ + __IO uint32_t EVENT_TMR; /**< EVENT TIMER, offset: 0x4 */ + __IO uint32_t T1_CMP; /**< T1 COMPARE, offset: 0x8 */ + __IO uint32_t T2_CMP; /**< T2 COMPARE, offset: 0xC */ + __I uint32_t TIMESTAMP; /**< TIMESTAMP, offset: 0x10 */ + __IO uint32_t XCVR_CTRL; /**< TRANSCEIVER CONTROL, offset: 0x14 */ + __I uint32_t XCVR_STS; /**< TRANSCEIVER STATUS, offset: 0x18 */ + __IO uint32_t XCVR_CFG; /**< TRANSCEIVER CONFIGURATION, offset: 0x1C */ + __IO uint32_t CHANNEL_NUM; /**< CHANNEL NUMBER, offset: 0x20 */ + __IO uint32_t TX_POWER; /**< TRANSMIT POWER, offset: 0x24 */ + __IO uint32_t NTW_ADR_CTRL; /**< NETWORK ADDRESS CONTROL, offset: 0x28 */ + __IO uint32_t NTW_ADR_0; /**< NETWORK ADDRESS 0, offset: 0x2C */ + __IO uint32_t NTW_ADR_1; /**< NETWORK ADDRESS 1, offset: 0x30 */ + __IO uint32_t NTW_ADR_2; /**< NETWORK ADDRESS 2, offset: 0x34 */ + __IO uint32_t NTW_ADR_3; /**< NETWORK ADDRESS 3, offset: 0x38 */ + __IO uint32_t RX_WATERMARK; /**< RX WATERMARK, offset: 0x3C */ + __IO uint32_t DSM_CTRL; /**< DSM CONTROL, offset: 0x40 */ + __I uint32_t PART_ID; /**< PART ID, offset: 0x44 */ + uint8_t RESERVED_0[184]; + __IO uint16_t PACKET_BUFFER[64]; /**< PACKET BUFFER, array offset: 0x100, array step: 0x2 */ +} ANT_Type; + +/* ---------------------------------------------------------------------------- + -- ANT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ANT_Register_Masks ANT Register Masks + * @{ + */ + +/*! @name IRQ_CTRL - IRQ CONTROL */ +#define ANT_IRQ_CTRL_SEQ_END_IRQ_MASK (0x1U) +#define ANT_IRQ_CTRL_SEQ_END_IRQ_SHIFT (0U) +#define ANT_IRQ_CTRL_SEQ_END_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_SEQ_END_IRQ_SHIFT)) & ANT_IRQ_CTRL_SEQ_END_IRQ_MASK) +#define ANT_IRQ_CTRL_TX_IRQ_MASK (0x2U) +#define ANT_IRQ_CTRL_TX_IRQ_SHIFT (1U) +#define ANT_IRQ_CTRL_TX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_TX_IRQ_SHIFT)) & ANT_IRQ_CTRL_TX_IRQ_MASK) +#define ANT_IRQ_CTRL_RX_IRQ_MASK (0x4U) +#define ANT_IRQ_CTRL_RX_IRQ_SHIFT (2U) +#define ANT_IRQ_CTRL_RX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_RX_IRQ_SHIFT)) & ANT_IRQ_CTRL_RX_IRQ_MASK) +#define ANT_IRQ_CTRL_NTW_ADR_IRQ_MASK (0x8U) +#define ANT_IRQ_CTRL_NTW_ADR_IRQ_SHIFT (3U) +#define ANT_IRQ_CTRL_NTW_ADR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_NTW_ADR_IRQ_SHIFT)) & ANT_IRQ_CTRL_NTW_ADR_IRQ_MASK) +#define ANT_IRQ_CTRL_T1_IRQ_MASK (0x10U) +#define ANT_IRQ_CTRL_T1_IRQ_SHIFT (4U) +#define ANT_IRQ_CTRL_T1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_T1_IRQ_SHIFT)) & ANT_IRQ_CTRL_T1_IRQ_MASK) +#define ANT_IRQ_CTRL_T2_IRQ_MASK (0x20U) +#define ANT_IRQ_CTRL_T2_IRQ_SHIFT (5U) +#define ANT_IRQ_CTRL_T2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_T2_IRQ_SHIFT)) & ANT_IRQ_CTRL_T2_IRQ_MASK) +#define ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_MASK (0x40U) +#define ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_SHIFT (6U) +#define ANT_IRQ_CTRL_PLL_UNLOCK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_SHIFT)) & ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_MASK) +#define ANT_IRQ_CTRL_WAKE_IRQ_MASK (0x80U) +#define ANT_IRQ_CTRL_WAKE_IRQ_SHIFT (7U) +#define ANT_IRQ_CTRL_WAKE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_WAKE_IRQ_SHIFT)) & ANT_IRQ_CTRL_WAKE_IRQ_MASK) +#define ANT_IRQ_CTRL_RX_WATERMARK_IRQ_MASK (0x100U) +#define ANT_IRQ_CTRL_RX_WATERMARK_IRQ_SHIFT (8U) +#define ANT_IRQ_CTRL_RX_WATERMARK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_RX_WATERMARK_IRQ_SHIFT)) & ANT_IRQ_CTRL_RX_WATERMARK_IRQ_MASK) +#define ANT_IRQ_CTRL_TSM_IRQ_MASK (0x200U) +#define ANT_IRQ_CTRL_TSM_IRQ_SHIFT (9U) +#define ANT_IRQ_CTRL_TSM_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_TSM_IRQ_SHIFT)) & ANT_IRQ_CTRL_TSM_IRQ_MASK) +#define ANT_IRQ_CTRL_SEQ_END_IRQ_EN_MASK (0x10000U) +#define ANT_IRQ_CTRL_SEQ_END_IRQ_EN_SHIFT (16U) +#define ANT_IRQ_CTRL_SEQ_END_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_SEQ_END_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_SEQ_END_IRQ_EN_MASK) +#define ANT_IRQ_CTRL_TX_IRQ_EN_MASK (0x20000U) +#define ANT_IRQ_CTRL_TX_IRQ_EN_SHIFT (17U) +#define ANT_IRQ_CTRL_TX_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_TX_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_TX_IRQ_EN_MASK) +#define ANT_IRQ_CTRL_RX_IRQ_EN_MASK (0x40000U) +#define ANT_IRQ_CTRL_RX_IRQ_EN_SHIFT (18U) +#define ANT_IRQ_CTRL_RX_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_RX_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_RX_IRQ_EN_MASK) +#define ANT_IRQ_CTRL_NTW_ADR_IRQ_EN_MASK (0x80000U) +#define ANT_IRQ_CTRL_NTW_ADR_IRQ_EN_SHIFT (19U) +#define ANT_IRQ_CTRL_NTW_ADR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_NTW_ADR_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_NTW_ADR_IRQ_EN_MASK) +#define ANT_IRQ_CTRL_T1_IRQ_EN_MASK (0x100000U) +#define ANT_IRQ_CTRL_T1_IRQ_EN_SHIFT (20U) +#define ANT_IRQ_CTRL_T1_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_T1_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_T1_IRQ_EN_MASK) +#define ANT_IRQ_CTRL_T2_IRQ_EN_MASK (0x200000U) +#define ANT_IRQ_CTRL_T2_IRQ_EN_SHIFT (21U) +#define ANT_IRQ_CTRL_T2_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_T2_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_T2_IRQ_EN_MASK) +#define ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_MASK (0x400000U) +#define ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_SHIFT (22U) +#define ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_MASK) +#define ANT_IRQ_CTRL_WAKE_IRQ_EN_MASK (0x800000U) +#define ANT_IRQ_CTRL_WAKE_IRQ_EN_SHIFT (23U) +#define ANT_IRQ_CTRL_WAKE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_WAKE_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_WAKE_IRQ_EN_MASK) +#define ANT_IRQ_CTRL_RX_WATERMARK_IRQ_EN_MASK (0x1000000U) +#define ANT_IRQ_CTRL_RX_WATERMARK_IRQ_EN_SHIFT (24U) +#define ANT_IRQ_CTRL_RX_WATERMARK_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_RX_WATERMARK_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_RX_WATERMARK_IRQ_EN_MASK) +#define ANT_IRQ_CTRL_TSM_IRQ_EN_MASK (0x2000000U) +#define ANT_IRQ_CTRL_TSM_IRQ_EN_SHIFT (25U) +#define ANT_IRQ_CTRL_TSM_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_TSM_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_TSM_IRQ_EN_MASK) +#define ANT_IRQ_CTRL_ANT_IRQ_EN_MASK (0x4000000U) +#define ANT_IRQ_CTRL_ANT_IRQ_EN_SHIFT (26U) +#define ANT_IRQ_CTRL_ANT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_ANT_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_ANT_IRQ_EN_MASK) +#define ANT_IRQ_CTRL_CRC_IGNORE_MASK (0x8000000U) +#define ANT_IRQ_CTRL_CRC_IGNORE_SHIFT (27U) +#define ANT_IRQ_CTRL_CRC_IGNORE(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_CRC_IGNORE_SHIFT)) & ANT_IRQ_CTRL_CRC_IGNORE_MASK) +#define ANT_IRQ_CTRL_CRC_VALID_MASK (0x80000000U) +#define ANT_IRQ_CTRL_CRC_VALID_SHIFT (31U) +#define ANT_IRQ_CTRL_CRC_VALID(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_CRC_VALID_SHIFT)) & ANT_IRQ_CTRL_CRC_VALID_MASK) + +/*! @name EVENT_TMR - EVENT TIMER */ +#define ANT_EVENT_TMR_EVENT_TMR_MASK (0xFFFFFFU) +#define ANT_EVENT_TMR_EVENT_TMR_SHIFT (0U) +#define ANT_EVENT_TMR_EVENT_TMR(x) (((uint32_t)(((uint32_t)(x)) << ANT_EVENT_TMR_EVENT_TMR_SHIFT)) & ANT_EVENT_TMR_EVENT_TMR_MASK) +#define ANT_EVENT_TMR_EVENT_TMR_LD_MASK (0x1000000U) +#define ANT_EVENT_TMR_EVENT_TMR_LD_SHIFT (24U) +#define ANT_EVENT_TMR_EVENT_TMR_LD(x) (((uint32_t)(((uint32_t)(x)) << ANT_EVENT_TMR_EVENT_TMR_LD_SHIFT)) & ANT_EVENT_TMR_EVENT_TMR_LD_MASK) +#define ANT_EVENT_TMR_EVENT_TMR_ADD_MASK (0x2000000U) +#define ANT_EVENT_TMR_EVENT_TMR_ADD_SHIFT (25U) +#define ANT_EVENT_TMR_EVENT_TMR_ADD(x) (((uint32_t)(((uint32_t)(x)) << ANT_EVENT_TMR_EVENT_TMR_ADD_SHIFT)) & ANT_EVENT_TMR_EVENT_TMR_ADD_MASK) + +/*! @name T1_CMP - T1 COMPARE */ +#define ANT_T1_CMP_T1_CMP_MASK (0xFFFFFFU) +#define ANT_T1_CMP_T1_CMP_SHIFT (0U) +#define ANT_T1_CMP_T1_CMP(x) (((uint32_t)(((uint32_t)(x)) << ANT_T1_CMP_T1_CMP_SHIFT)) & ANT_T1_CMP_T1_CMP_MASK) +#define ANT_T1_CMP_T1_CMP_EN_MASK (0x1000000U) +#define ANT_T1_CMP_T1_CMP_EN_SHIFT (24U) +#define ANT_T1_CMP_T1_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_T1_CMP_T1_CMP_EN_SHIFT)) & ANT_T1_CMP_T1_CMP_EN_MASK) + +/*! @name T2_CMP - T2 COMPARE */ +#define ANT_T2_CMP_T2_CMP_MASK (0xFFFFFFU) +#define ANT_T2_CMP_T2_CMP_SHIFT (0U) +#define ANT_T2_CMP_T2_CMP(x) (((uint32_t)(((uint32_t)(x)) << ANT_T2_CMP_T2_CMP_SHIFT)) & ANT_T2_CMP_T2_CMP_MASK) +#define ANT_T2_CMP_T2_CMP_EN_MASK (0x1000000U) +#define ANT_T2_CMP_T2_CMP_EN_SHIFT (24U) +#define ANT_T2_CMP_T2_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_T2_CMP_T2_CMP_EN_SHIFT)) & ANT_T2_CMP_T2_CMP_EN_MASK) + +/*! @name TIMESTAMP - TIMESTAMP */ +#define ANT_TIMESTAMP_TIMESTAMP_MASK (0xFFFFFFU) +#define ANT_TIMESTAMP_TIMESTAMP_SHIFT (0U) +#define ANT_TIMESTAMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ANT_TIMESTAMP_TIMESTAMP_SHIFT)) & ANT_TIMESTAMP_TIMESTAMP_MASK) + +/*! @name XCVR_CTRL - TRANSCEIVER CONTROL */ +#define ANT_XCVR_CTRL_SEQCMD_MASK (0xFU) +#define ANT_XCVR_CTRL_SEQCMD_SHIFT (0U) +#define ANT_XCVR_CTRL_SEQCMD(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CTRL_SEQCMD_SHIFT)) & ANT_XCVR_CTRL_SEQCMD_MASK) +#define ANT_XCVR_CTRL_TX_PKT_LENGTH_MASK (0x3F00U) +#define ANT_XCVR_CTRL_TX_PKT_LENGTH_SHIFT (8U) +#define ANT_XCVR_CTRL_TX_PKT_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CTRL_TX_PKT_LENGTH_SHIFT)) & ANT_XCVR_CTRL_TX_PKT_LENGTH_MASK) +#define ANT_XCVR_CTRL_RX_PKT_LENGTH_MASK (0x3F0000U) +#define ANT_XCVR_CTRL_RX_PKT_LENGTH_SHIFT (16U) +#define ANT_XCVR_CTRL_RX_PKT_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CTRL_RX_PKT_LENGTH_SHIFT)) & ANT_XCVR_CTRL_RX_PKT_LENGTH_MASK) +#define ANT_XCVR_CTRL_CMDDEC_CS_MASK (0x7000000U) +#define ANT_XCVR_CTRL_CMDDEC_CS_SHIFT (24U) +#define ANT_XCVR_CTRL_CMDDEC_CS(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CTRL_CMDDEC_CS_SHIFT)) & ANT_XCVR_CTRL_CMDDEC_CS_MASK) +#define ANT_XCVR_CTRL_XCVR_BUSY_MASK (0x80000000U) +#define ANT_XCVR_CTRL_XCVR_BUSY_SHIFT (31U) +#define ANT_XCVR_CTRL_XCVR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CTRL_XCVR_BUSY_SHIFT)) & ANT_XCVR_CTRL_XCVR_BUSY_MASK) + +/*! @name XCVR_STS - TRANSCEIVER STATUS */ +#define ANT_XCVR_STS_TX_START_T1_PEND_MASK (0x1U) +#define ANT_XCVR_STS_TX_START_T1_PEND_SHIFT (0U) +#define ANT_XCVR_STS_TX_START_T1_PEND(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_TX_START_T1_PEND_SHIFT)) & ANT_XCVR_STS_TX_START_T1_PEND_MASK) +#define ANT_XCVR_STS_TX_START_T2_PEND_MASK (0x2U) +#define ANT_XCVR_STS_TX_START_T2_PEND_SHIFT (1U) +#define ANT_XCVR_STS_TX_START_T2_PEND(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_TX_START_T2_PEND_SHIFT)) & ANT_XCVR_STS_TX_START_T2_PEND_MASK) +#define ANT_XCVR_STS_TX_IN_WARMUP_MASK (0x4U) +#define ANT_XCVR_STS_TX_IN_WARMUP_SHIFT (2U) +#define ANT_XCVR_STS_TX_IN_WARMUP(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_TX_IN_WARMUP_SHIFT)) & ANT_XCVR_STS_TX_IN_WARMUP_MASK) +#define ANT_XCVR_STS_TX_IN_PROGRESS_MASK (0x8U) +#define ANT_XCVR_STS_TX_IN_PROGRESS_SHIFT (3U) +#define ANT_XCVR_STS_TX_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_TX_IN_PROGRESS_SHIFT)) & ANT_XCVR_STS_TX_IN_PROGRESS_MASK) +#define ANT_XCVR_STS_TX_IN_WARMDN_MASK (0x10U) +#define ANT_XCVR_STS_TX_IN_WARMDN_SHIFT (4U) +#define ANT_XCVR_STS_TX_IN_WARMDN(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_TX_IN_WARMDN_SHIFT)) & ANT_XCVR_STS_TX_IN_WARMDN_MASK) +#define ANT_XCVR_STS_RX_START_T1_PEND_MASK (0x20U) +#define ANT_XCVR_STS_RX_START_T1_PEND_SHIFT (5U) +#define ANT_XCVR_STS_RX_START_T1_PEND(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RX_START_T1_PEND_SHIFT)) & ANT_XCVR_STS_RX_START_T1_PEND_MASK) +#define ANT_XCVR_STS_RX_START_T2_PEND_MASK (0x40U) +#define ANT_XCVR_STS_RX_START_T2_PEND_SHIFT (6U) +#define ANT_XCVR_STS_RX_START_T2_PEND(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RX_START_T2_PEND_SHIFT)) & ANT_XCVR_STS_RX_START_T2_PEND_MASK) +#define ANT_XCVR_STS_RX_STOP_T1_PEND_MASK (0x80U) +#define ANT_XCVR_STS_RX_STOP_T1_PEND_SHIFT (7U) +#define ANT_XCVR_STS_RX_STOP_T1_PEND(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RX_STOP_T1_PEND_SHIFT)) & ANT_XCVR_STS_RX_STOP_T1_PEND_MASK) +#define ANT_XCVR_STS_RX_STOP_T2_PEND_MASK (0x100U) +#define ANT_XCVR_STS_RX_STOP_T2_PEND_SHIFT (8U) +#define ANT_XCVR_STS_RX_STOP_T2_PEND(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RX_STOP_T2_PEND_SHIFT)) & ANT_XCVR_STS_RX_STOP_T2_PEND_MASK) +#define ANT_XCVR_STS_RX_IN_WARMUP_MASK (0x200U) +#define ANT_XCVR_STS_RX_IN_WARMUP_SHIFT (9U) +#define ANT_XCVR_STS_RX_IN_WARMUP(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RX_IN_WARMUP_SHIFT)) & ANT_XCVR_STS_RX_IN_WARMUP_MASK) +#define ANT_XCVR_STS_RX_IN_SEARCH_MASK (0x400U) +#define ANT_XCVR_STS_RX_IN_SEARCH_SHIFT (10U) +#define ANT_XCVR_STS_RX_IN_SEARCH(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RX_IN_SEARCH_SHIFT)) & ANT_XCVR_STS_RX_IN_SEARCH_MASK) +#define ANT_XCVR_STS_RX_IN_PROGRESS_MASK (0x800U) +#define ANT_XCVR_STS_RX_IN_PROGRESS_SHIFT (11U) +#define ANT_XCVR_STS_RX_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RX_IN_PROGRESS_SHIFT)) & ANT_XCVR_STS_RX_IN_PROGRESS_MASK) +#define ANT_XCVR_STS_RX_IN_WARMDN_MASK (0x1000U) +#define ANT_XCVR_STS_RX_IN_WARMDN_SHIFT (12U) +#define ANT_XCVR_STS_RX_IN_WARMDN(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RX_IN_WARMDN_SHIFT)) & ANT_XCVR_STS_RX_IN_WARMDN_MASK) +#define ANT_XCVR_STS_CRC_VALID_MASK (0x8000U) +#define ANT_XCVR_STS_CRC_VALID_SHIFT (15U) +#define ANT_XCVR_STS_CRC_VALID(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_CRC_VALID_SHIFT)) & ANT_XCVR_STS_CRC_VALID_MASK) +#define ANT_XCVR_STS_RSSI_MASK (0xFF0000U) +#define ANT_XCVR_STS_RSSI_SHIFT (16U) +#define ANT_XCVR_STS_RSSI(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RSSI_SHIFT)) & ANT_XCVR_STS_RSSI_MASK) + +/*! @name XCVR_CFG - TRANSCEIVER CONFIGURATION */ +#define ANT_XCVR_CFG_TX_WHITEN_DIS_MASK (0x1U) +#define ANT_XCVR_CFG_TX_WHITEN_DIS_SHIFT (0U) +#define ANT_XCVR_CFG_TX_WHITEN_DIS(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CFG_TX_WHITEN_DIS_SHIFT)) & ANT_XCVR_CFG_TX_WHITEN_DIS_MASK) +#define ANT_XCVR_CFG_RX_DEWHITEN_DIS_MASK (0x2U) +#define ANT_XCVR_CFG_RX_DEWHITEN_DIS_SHIFT (1U) +#define ANT_XCVR_CFG_RX_DEWHITEN_DIS(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CFG_RX_DEWHITEN_DIS_SHIFT)) & ANT_XCVR_CFG_RX_DEWHITEN_DIS_MASK) +#define ANT_XCVR_CFG_SW_CRC_EN_MASK (0x4U) +#define ANT_XCVR_CFG_SW_CRC_EN_SHIFT (2U) +#define ANT_XCVR_CFG_SW_CRC_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CFG_SW_CRC_EN_SHIFT)) & ANT_XCVR_CFG_SW_CRC_EN_MASK) +#define ANT_XCVR_CFG_PREAMBLE_SZ_MASK (0x30U) +#define ANT_XCVR_CFG_PREAMBLE_SZ_SHIFT (4U) +#define ANT_XCVR_CFG_PREAMBLE_SZ(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CFG_PREAMBLE_SZ_SHIFT)) & ANT_XCVR_CFG_PREAMBLE_SZ_MASK) +#define ANT_XCVR_CFG_TX_WARMUP_MASK (0xFF00U) +#define ANT_XCVR_CFG_TX_WARMUP_SHIFT (8U) +#define ANT_XCVR_CFG_TX_WARMUP(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CFG_TX_WARMUP_SHIFT)) & ANT_XCVR_CFG_TX_WARMUP_MASK) +#define ANT_XCVR_CFG_RX_WARMUP_MASK (0xFF0000U) +#define ANT_XCVR_CFG_RX_WARMUP_SHIFT (16U) +#define ANT_XCVR_CFG_RX_WARMUP(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CFG_RX_WARMUP_SHIFT)) & ANT_XCVR_CFG_RX_WARMUP_MASK) + +/*! @name CHANNEL_NUM - CHANNEL NUMBER */ +#define ANT_CHANNEL_NUM_CHANNEL_NUM_MASK (0x7FU) +#define ANT_CHANNEL_NUM_CHANNEL_NUM_SHIFT (0U) +#define ANT_CHANNEL_NUM_CHANNEL_NUM(x) (((uint32_t)(((uint32_t)(x)) << ANT_CHANNEL_NUM_CHANNEL_NUM_SHIFT)) & ANT_CHANNEL_NUM_CHANNEL_NUM_MASK) + +/*! @name TX_POWER - TRANSMIT POWER */ +#define ANT_TX_POWER_TX_POWER_MASK (0x3FU) +#define ANT_TX_POWER_TX_POWER_SHIFT (0U) +#define ANT_TX_POWER_TX_POWER(x) (((uint32_t)(((uint32_t)(x)) << ANT_TX_POWER_TX_POWER_SHIFT)) & ANT_TX_POWER_TX_POWER_MASK) + +/*! @name NTW_ADR_CTRL - NETWORK ADDRESS CONTROL */ +#define ANT_NTW_ADR_CTRL_NTW_ADR_EN_MASK (0xFU) +#define ANT_NTW_ADR_CTRL_NTW_ADR_EN_SHIFT (0U) +#define ANT_NTW_ADR_CTRL_NTW_ADR_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR_EN_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR_EN_MASK) +#define ANT_NTW_ADR_CTRL_NTW_ADR_MCH_MASK (0xF0U) +#define ANT_NTW_ADR_CTRL_NTW_ADR_MCH_SHIFT (4U) +#define ANT_NTW_ADR_CTRL_NTW_ADR_MCH(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR_MCH_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR_MCH_MASK) +#define ANT_NTW_ADR_CTRL_NTW_ADR0_SZ_MASK (0x300U) +#define ANT_NTW_ADR_CTRL_NTW_ADR0_SZ_SHIFT (8U) +#define ANT_NTW_ADR_CTRL_NTW_ADR0_SZ(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR0_SZ_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR0_SZ_MASK) +#define ANT_NTW_ADR_CTRL_NTW_ADR1_SZ_MASK (0xC00U) +#define ANT_NTW_ADR_CTRL_NTW_ADR1_SZ_SHIFT (10U) +#define ANT_NTW_ADR_CTRL_NTW_ADR1_SZ(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR1_SZ_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR1_SZ_MASK) +#define ANT_NTW_ADR_CTRL_NTW_ADR2_SZ_MASK (0x3000U) +#define ANT_NTW_ADR_CTRL_NTW_ADR2_SZ_SHIFT (12U) +#define ANT_NTW_ADR_CTRL_NTW_ADR2_SZ(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR2_SZ_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR2_SZ_MASK) +#define ANT_NTW_ADR_CTRL_NTW_ADR3_SZ_MASK (0xC000U) +#define ANT_NTW_ADR_CTRL_NTW_ADR3_SZ_SHIFT (14U) +#define ANT_NTW_ADR_CTRL_NTW_ADR3_SZ(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR3_SZ_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR3_SZ_MASK) +#define ANT_NTW_ADR_CTRL_NTW_ADR_THR0_MASK (0x70000U) +#define ANT_NTW_ADR_CTRL_NTW_ADR_THR0_SHIFT (16U) +#define ANT_NTW_ADR_CTRL_NTW_ADR_THR0(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR_THR0_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR_THR0_MASK) +#define ANT_NTW_ADR_CTRL_NTW_ADR_THR1_MASK (0x700000U) +#define ANT_NTW_ADR_CTRL_NTW_ADR_THR1_SHIFT (20U) +#define ANT_NTW_ADR_CTRL_NTW_ADR_THR1(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR_THR1_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR_THR1_MASK) +#define ANT_NTW_ADR_CTRL_NTW_ADR_THR2_MASK (0x7000000U) +#define ANT_NTW_ADR_CTRL_NTW_ADR_THR2_SHIFT (24U) +#define ANT_NTW_ADR_CTRL_NTW_ADR_THR2(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR_THR2_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR_THR2_MASK) +#define ANT_NTW_ADR_CTRL_NTW_ADR_THR3_MASK (0x70000000U) +#define ANT_NTW_ADR_CTRL_NTW_ADR_THR3_SHIFT (28U) +#define ANT_NTW_ADR_CTRL_NTW_ADR_THR3(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR_THR3_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR_THR3_MASK) + +/*! @name NTW_ADR_0 - NETWORK ADDRESS 0 */ +#define ANT_NTW_ADR_0_NTW_ADR_0_MASK (0xFFFFFFFFU) +#define ANT_NTW_ADR_0_NTW_ADR_0_SHIFT (0U) +#define ANT_NTW_ADR_0_NTW_ADR_0(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_0_NTW_ADR_0_SHIFT)) & ANT_NTW_ADR_0_NTW_ADR_0_MASK) + +/*! @name NTW_ADR_1 - NETWORK ADDRESS 1 */ +#define ANT_NTW_ADR_1_NTW_ADR_1_MASK (0xFFFFFFFFU) +#define ANT_NTW_ADR_1_NTW_ADR_1_SHIFT (0U) +#define ANT_NTW_ADR_1_NTW_ADR_1(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_1_NTW_ADR_1_SHIFT)) & ANT_NTW_ADR_1_NTW_ADR_1_MASK) + +/*! @name NTW_ADR_2 - NETWORK ADDRESS 2 */ +#define ANT_NTW_ADR_2_NTW_ADR_2_MASK (0xFFFFFFFFU) +#define ANT_NTW_ADR_2_NTW_ADR_2_SHIFT (0U) +#define ANT_NTW_ADR_2_NTW_ADR_2(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_2_NTW_ADR_2_SHIFT)) & ANT_NTW_ADR_2_NTW_ADR_2_MASK) + +/*! @name NTW_ADR_3 - NETWORK ADDRESS 3 */ +#define ANT_NTW_ADR_3_NTW_ADR_3_MASK (0xFFFFFFFFU) +#define ANT_NTW_ADR_3_NTW_ADR_3_SHIFT (0U) +#define ANT_NTW_ADR_3_NTW_ADR_3(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_3_NTW_ADR_3_SHIFT)) & ANT_NTW_ADR_3_NTW_ADR_3_MASK) + +/*! @name RX_WATERMARK - RX WATERMARK */ +#define ANT_RX_WATERMARK_RX_WATERMARK_MASK (0x7FU) +#define ANT_RX_WATERMARK_RX_WATERMARK_SHIFT (0U) +#define ANT_RX_WATERMARK_RX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << ANT_RX_WATERMARK_RX_WATERMARK_SHIFT)) & ANT_RX_WATERMARK_RX_WATERMARK_MASK) +#define ANT_RX_WATERMARK_BYTE_COUNTER_MASK (0x7F0000U) +#define ANT_RX_WATERMARK_BYTE_COUNTER_SHIFT (16U) +#define ANT_RX_WATERMARK_BYTE_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << ANT_RX_WATERMARK_BYTE_COUNTER_SHIFT)) & ANT_RX_WATERMARK_BYTE_COUNTER_MASK) + +/*! @name DSM_CTRL - DSM CONTROL */ +#define ANT_DSM_CTRL_ANT_SLEEP_EN_MASK (0x1U) +#define ANT_DSM_CTRL_ANT_SLEEP_EN_SHIFT (0U) +#define ANT_DSM_CTRL_ANT_SLEEP_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_DSM_CTRL_ANT_SLEEP_EN_SHIFT)) & ANT_DSM_CTRL_ANT_SLEEP_EN_MASK) + +/*! @name PART_ID - PART ID */ +#define ANT_PART_ID_PART_ID_MASK (0xFFU) +#define ANT_PART_ID_PART_ID_SHIFT (0U) +#define ANT_PART_ID_PART_ID(x) (((uint32_t)(((uint32_t)(x)) << ANT_PART_ID_PART_ID_SHIFT)) & ANT_PART_ID_PART_ID_MASK) + +/*! @name PACKET_BUFFER - PACKET BUFFER */ +#define ANT_PACKET_BUFFER_PACKET_BUFFER_MASK (0xFFFFU) +#define ANT_PACKET_BUFFER_PACKET_BUFFER_SHIFT (0U) +#define ANT_PACKET_BUFFER_PACKET_BUFFER(x) (((uint16_t)(((uint16_t)(x)) << ANT_PACKET_BUFFER_PACKET_BUFFER_SHIFT)) & ANT_PACKET_BUFFER_PACKET_BUFFER_MASK) + +/* The count of ANT_PACKET_BUFFER */ +#define ANT_PACKET_BUFFER_COUNT (64U) + + +/*! + * @} + */ /* end of group ANT_Register_Masks */ + + +/* ANT - Peripheral instance base addresses */ +/** Peripheral ANT base address */ +#define ANT_BASE (0x4005E000u) +/** Peripheral ANT base pointer */ +#define ANT ((ANT_Type *)ANT_BASE) +/** Array initializer of ANT peripheral base addresses */ +#define ANT_BASE_ADDRS { ANT_BASE } +/** Array initializer of ANT peripheral base pointers */ +#define ANT_BASE_PTRS { ANT } + +/*! + * @} + */ /* end of group ANT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- BTLE_RF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BTLE_RF_Peripheral_Access_Layer BTLE_RF Peripheral Access Layer + * @{ + */ + +/** BTLE_RF - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[1536]; + __I uint16_t BLE_PART_ID; /**< BLUETOOTH LOW ENERGY PART ID, offset: 0x600 */ + uint8_t RESERVED_1[2]; + __I uint16_t DSM_STATUS; /**< BLE DSM STATUS, offset: 0x604 */ + uint8_t RESERVED_2[2]; + __IO uint16_t MISC_CTRL; /**< BLUETOOTH LOW ENERGY MISCELLANEOUS CONTROL, offset: 0x608 */ +} BTLE_RF_Type; + +/* ---------------------------------------------------------------------------- + -- BTLE_RF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BTLE_RF_Register_Masks BTLE_RF Register Masks + * @{ + */ + +/*! @name BLE_PART_ID - BLUETOOTH LOW ENERGY PART ID */ +#define BTLE_RF_BLE_PART_ID_BLE_PART_ID_MASK (0xFFFFU) +#define BTLE_RF_BLE_PART_ID_BLE_PART_ID_SHIFT (0U) +#define BTLE_RF_BLE_PART_ID_BLE_PART_ID(x) (((uint16_t)(((uint16_t)(x)) << BTLE_RF_BLE_PART_ID_BLE_PART_ID_SHIFT)) & BTLE_RF_BLE_PART_ID_BLE_PART_ID_MASK) + +/*! @name DSM_STATUS - BLE DSM STATUS */ +#define BTLE_RF_DSM_STATUS_ORF_SYSCLK_REQ_MASK (0x1U) +#define BTLE_RF_DSM_STATUS_ORF_SYSCLK_REQ_SHIFT (0U) +#define BTLE_RF_DSM_STATUS_ORF_SYSCLK_REQ(x) (((uint16_t)(((uint16_t)(x)) << BTLE_RF_DSM_STATUS_ORF_SYSCLK_REQ_SHIFT)) & BTLE_RF_DSM_STATUS_ORF_SYSCLK_REQ_MASK) +#define BTLE_RF_DSM_STATUS_RIF_LL_ACTIVE_MASK (0x2U) +#define BTLE_RF_DSM_STATUS_RIF_LL_ACTIVE_SHIFT (1U) +#define BTLE_RF_DSM_STATUS_RIF_LL_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << BTLE_RF_DSM_STATUS_RIF_LL_ACTIVE_SHIFT)) & BTLE_RF_DSM_STATUS_RIF_LL_ACTIVE_MASK) +#define BTLE_RF_DSM_STATUS_XCVR_BUSY_MASK (0x4U) +#define BTLE_RF_DSM_STATUS_XCVR_BUSY_SHIFT (2U) +#define BTLE_RF_DSM_STATUS_XCVR_BUSY(x) (((uint16_t)(((uint16_t)(x)) << BTLE_RF_DSM_STATUS_XCVR_BUSY_SHIFT)) & BTLE_RF_DSM_STATUS_XCVR_BUSY_MASK) + +/*! @name MISC_CTRL - BLUETOOTH LOW ENERGY MISCELLANEOUS CONTROL */ +#define BTLE_RF_MISC_CTRL_TSM_INTR_EN_MASK (0x2U) +#define BTLE_RF_MISC_CTRL_TSM_INTR_EN_SHIFT (1U) +#define BTLE_RF_MISC_CTRL_TSM_INTR_EN(x) (((uint16_t)(((uint16_t)(x)) << BTLE_RF_MISC_CTRL_TSM_INTR_EN_SHIFT)) & BTLE_RF_MISC_CTRL_TSM_INTR_EN_MASK) + + +/*! + * @} + */ /* end of group BTLE_RF_Register_Masks */ + + +/* BTLE_RF - Peripheral instance base addresses */ +/** Peripheral BTLE_RF base address */ +#define BTLE_RF_BASE (0x4005B000u) +/** Peripheral BTLE_RF base pointer */ +#define BTLE_RF ((BTLE_RF_Type *)BTLE_RF_BASE) +/** Array initializer of BTLE_RF peripheral base addresses */ +#define BTLE_RF_BASE_ADDRS { BTLE_RF_BASE } +/** Array initializer of BTLE_RF peripheral base pointers */ +#define BTLE_RF_BASE_PTRS { BTLE_RF } + +/*! + * @} + */ /* end of group BTLE_RF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CMP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer + * @{ + */ + +/** CMP - Register Layout Typedef */ +typedef struct { + __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ + __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ + __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */ + __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */ + __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */ + __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ +} CMP_Type; + +/* ---------------------------------------------------------------------------- + -- CMP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMP_Register_Masks CMP Register Masks + * @{ + */ + +/*! @name CR0 - CMP Control Register 0 */ +#define CMP_CR0_HYSTCTR_MASK (0x3U) +#define CMP_CR0_HYSTCTR_SHIFT (0U) +#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK) +#define CMP_CR0_FILTER_CNT_MASK (0x70U) +#define CMP_CR0_FILTER_CNT_SHIFT (4U) +#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK) + +/*! @name CR1 - CMP Control Register 1 */ +#define CMP_CR1_EN_MASK (0x1U) +#define CMP_CR1_EN_SHIFT (0U) +#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK) +#define CMP_CR1_OPE_MASK (0x2U) +#define CMP_CR1_OPE_SHIFT (1U) +#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK) +#define CMP_CR1_COS_MASK (0x4U) +#define CMP_CR1_COS_SHIFT (2U) +#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK) +#define CMP_CR1_INV_MASK (0x8U) +#define CMP_CR1_INV_SHIFT (3U) +#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK) +#define CMP_CR1_PMODE_MASK (0x10U) +#define CMP_CR1_PMODE_SHIFT (4U) +#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK) +#define CMP_CR1_TRIGM_MASK (0x20U) +#define CMP_CR1_TRIGM_SHIFT (5U) +#define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK) +#define CMP_CR1_WE_MASK (0x40U) +#define CMP_CR1_WE_SHIFT (6U) +#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK) +#define CMP_CR1_SE_MASK (0x80U) +#define CMP_CR1_SE_SHIFT (7U) +#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK) + +/*! @name FPR - CMP Filter Period Register */ +#define CMP_FPR_FILT_PER_MASK (0xFFU) +#define CMP_FPR_FILT_PER_SHIFT (0U) +#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK) + +/*! @name SCR - CMP Status and Control Register */ +#define CMP_SCR_COUT_MASK (0x1U) +#define CMP_SCR_COUT_SHIFT (0U) +#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK) +#define CMP_SCR_CFF_MASK (0x2U) +#define CMP_SCR_CFF_SHIFT (1U) +#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK) +#define CMP_SCR_CFR_MASK (0x4U) +#define CMP_SCR_CFR_SHIFT (2U) +#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK) +#define CMP_SCR_IEF_MASK (0x8U) +#define CMP_SCR_IEF_SHIFT (3U) +#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK) +#define CMP_SCR_IER_MASK (0x10U) +#define CMP_SCR_IER_SHIFT (4U) +#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK) +#define CMP_SCR_DMAEN_MASK (0x40U) +#define CMP_SCR_DMAEN_SHIFT (6U) +#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK) + +/*! @name DACCR - DAC Control Register */ +#define CMP_DACCR_VOSEL_MASK (0x3FU) +#define CMP_DACCR_VOSEL_SHIFT (0U) +#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK) +#define CMP_DACCR_VRSEL_MASK (0x40U) +#define CMP_DACCR_VRSEL_SHIFT (6U) +#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK) +#define CMP_DACCR_DACEN_MASK (0x80U) +#define CMP_DACCR_DACEN_SHIFT (7U) +#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK) + +/*! @name MUXCR - MUX Control Register */ +#define CMP_MUXCR_MSEL_MASK (0x7U) +#define CMP_MUXCR_MSEL_SHIFT (0U) +#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK) +#define CMP_MUXCR_PSEL_MASK (0x38U) +#define CMP_MUXCR_PSEL_SHIFT (3U) +#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK) +#define CMP_MUXCR_PSTM_MASK (0x80U) +#define CMP_MUXCR_PSTM_SHIFT (7U) +#define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK) + + +/*! + * @} + */ /* end of group CMP_Register_Masks */ + + +/* CMP - Peripheral instance base addresses */ +/** Peripheral CMP0 base address */ +#define CMP0_BASE (0x40073000u) +/** Peripheral CMP0 base pointer */ +#define CMP0 ((CMP_Type *)CMP0_BASE) +/** Array initializer of CMP peripheral base addresses */ +#define CMP_BASE_ADDRS { CMP0_BASE } +/** Array initializer of CMP peripheral base pointers */ +#define CMP_BASE_PTRS { CMP0 } +/** Interrupt vectors for the CMP peripheral type */ +#define CMP_IRQS { CMP0_IRQn } + +/*! + * @} + */ /* end of group CMP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CMT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer + * @{ + */ + +/** CMT - Register Layout Typedef */ +typedef struct { + __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */ + __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */ + __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */ + __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */ + __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */ + __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */ + __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */ + __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */ + __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */ + __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */ + __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */ + __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */ +} CMT_Type; + +/* ---------------------------------------------------------------------------- + -- CMT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMT_Register_Masks CMT Register Masks + * @{ + */ + +/*! @name CGH1 - CMT Carrier Generator High Data Register 1 */ +#define CMT_CGH1_PH_MASK (0xFFU) +#define CMT_CGH1_PH_SHIFT (0U) +#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK) + +/*! @name CGL1 - CMT Carrier Generator Low Data Register 1 */ +#define CMT_CGL1_PL_MASK (0xFFU) +#define CMT_CGL1_PL_SHIFT (0U) +#define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK) + +/*! @name CGH2 - CMT Carrier Generator High Data Register 2 */ +#define CMT_CGH2_SH_MASK (0xFFU) +#define CMT_CGH2_SH_SHIFT (0U) +#define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK) + +/*! @name CGL2 - CMT Carrier Generator Low Data Register 2 */ +#define CMT_CGL2_SL_MASK (0xFFU) +#define CMT_CGL2_SL_SHIFT (0U) +#define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK) + +/*! @name OC - CMT Output Control Register */ +#define CMT_OC_IROPEN_MASK (0x20U) +#define CMT_OC_IROPEN_SHIFT (5U) +#define CMT_OC_IROPEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK) +#define CMT_OC_CMTPOL_MASK (0x40U) +#define CMT_OC_CMTPOL_SHIFT (6U) +#define CMT_OC_CMTPOL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK) +#define CMT_OC_IROL_MASK (0x80U) +#define CMT_OC_IROL_SHIFT (7U) +#define CMT_OC_IROL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK) + +/*! @name MSC - CMT Modulator Status and Control Register */ +#define CMT_MSC_MCGEN_MASK (0x1U) +#define CMT_MSC_MCGEN_SHIFT (0U) +#define CMT_MSC_MCGEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK) +#define CMT_MSC_EOCIE_MASK (0x2U) +#define CMT_MSC_EOCIE_SHIFT (1U) +#define CMT_MSC_EOCIE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK) +#define CMT_MSC_FSK_MASK (0x4U) +#define CMT_MSC_FSK_SHIFT (2U) +#define CMT_MSC_FSK(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK) +#define CMT_MSC_BASE_MASK (0x8U) +#define CMT_MSC_BASE_SHIFT (3U) +#define CMT_MSC_BASE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK) +#define CMT_MSC_EXSPC_MASK (0x10U) +#define CMT_MSC_EXSPC_SHIFT (4U) +#define CMT_MSC_EXSPC(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK) +#define CMT_MSC_CMTDIV_MASK (0x60U) +#define CMT_MSC_CMTDIV_SHIFT (5U) +#define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK) +#define CMT_MSC_EOCF_MASK (0x80U) +#define CMT_MSC_EOCF_SHIFT (7U) +#define CMT_MSC_EOCF(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK) + +/*! @name CMD1 - CMT Modulator Data Register Mark High */ +#define CMT_CMD1_MB_MASK (0xFFU) +#define CMT_CMD1_MB_SHIFT (0U) +#define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK) + +/*! @name CMD2 - CMT Modulator Data Register Mark Low */ +#define CMT_CMD2_MB_MASK (0xFFU) +#define CMT_CMD2_MB_SHIFT (0U) +#define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK) + +/*! @name CMD3 - CMT Modulator Data Register Space High */ +#define CMT_CMD3_SB_MASK (0xFFU) +#define CMT_CMD3_SB_SHIFT (0U) +#define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK) + +/*! @name CMD4 - CMT Modulator Data Register Space Low */ +#define CMT_CMD4_SB_MASK (0xFFU) +#define CMT_CMD4_SB_SHIFT (0U) +#define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK) + +/*! @name PPS - CMT Primary Prescaler Register */ +#define CMT_PPS_PPSDIV_MASK (0xFU) +#define CMT_PPS_PPSDIV_SHIFT (0U) +#define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK) + +/*! @name DMA - CMT Direct Memory Access Register */ +#define CMT_DMA_DMA_MASK (0x1U) +#define CMT_DMA_DMA_SHIFT (0U) +#define CMT_DMA_DMA(x) (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK) + + +/*! + * @} + */ /* end of group CMT_Register_Masks */ + + +/* CMT - Peripheral instance base addresses */ +/** Peripheral CMT base address */ +#define CMT_BASE (0x40062000u) +/** Peripheral CMT base pointer */ +#define CMT ((CMT_Type *)CMT_BASE) +/** Array initializer of CMT peripheral base addresses */ +#define CMT_BASE_ADDRS { CMT_BASE } +/** Array initializer of CMT peripheral base pointers */ +#define CMT_BASE_PTRS { CMT } +/** Interrupt vectors for the CMT peripheral type */ +#define CMT_IRQS { CMT_IRQn } + +/*! + * @} + */ /* end of group CMT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DAC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer + * @{ + */ + +/** DAC - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x2 */ + __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */ + __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */ + } DAT[2]; + uint8_t RESERVED_0[28]; + __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */ + __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ + __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */ + __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */ +} DAC_Type; + +/* ---------------------------------------------------------------------------- + -- DAC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DAC_Register_Masks DAC Register Masks + * @{ + */ + +/*! @name DATL - DAC Data Low Register */ +#define DAC_DATL_DATA0_MASK (0xFFU) +#define DAC_DATL_DATA0_SHIFT (0U) +#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK) + +/* The count of DAC_DATL */ +#define DAC_DATL_COUNT (2U) + +/*! @name DATH - DAC Data High Register */ +#define DAC_DATH_DATA1_MASK (0xFU) +#define DAC_DATH_DATA1_SHIFT (0U) +#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK) + +/* The count of DAC_DATH */ +#define DAC_DATH_COUNT (2U) + +/*! @name SR - DAC Status Register */ +#define DAC_SR_DACBFRPBF_MASK (0x1U) +#define DAC_SR_DACBFRPBF_SHIFT (0U) +#define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK) +#define DAC_SR_DACBFRPTF_MASK (0x2U) +#define DAC_SR_DACBFRPTF_SHIFT (1U) +#define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK) +#define DAC_SR_DACBFWMF_MASK (0x4U) +#define DAC_SR_DACBFWMF_SHIFT (2U) +#define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK) + +/*! @name C0 - DAC Control Register */ +#define DAC_C0_DACBBIEN_MASK (0x1U) +#define DAC_C0_DACBBIEN_SHIFT (0U) +#define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK) +#define DAC_C0_DACBTIEN_MASK (0x2U) +#define DAC_C0_DACBTIEN_SHIFT (1U) +#define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK) +#define DAC_C0_DACBWIEN_MASK (0x4U) +#define DAC_C0_DACBWIEN_SHIFT (2U) +#define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK) +#define DAC_C0_LPEN_MASK (0x8U) +#define DAC_C0_LPEN_SHIFT (3U) +#define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK) +#define DAC_C0_DACSWTRG_MASK (0x10U) +#define DAC_C0_DACSWTRG_SHIFT (4U) +#define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK) +#define DAC_C0_DACTRGSEL_MASK (0x20U) +#define DAC_C0_DACTRGSEL_SHIFT (5U) +#define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK) +#define DAC_C0_DACRFS_MASK (0x40U) +#define DAC_C0_DACRFS_SHIFT (6U) +#define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK) +#define DAC_C0_DACEN_MASK (0x80U) +#define DAC_C0_DACEN_SHIFT (7U) +#define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK) + +/*! @name C1 - DAC Control Register 1 */ +#define DAC_C1_DACBFEN_MASK (0x1U) +#define DAC_C1_DACBFEN_SHIFT (0U) +#define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK) +#define DAC_C1_DACBFMD_MASK (0x4U) +#define DAC_C1_DACBFMD_SHIFT (2U) +#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK) +#define DAC_C1_DACBFWM_MASK (0x18U) +#define DAC_C1_DACBFWM_SHIFT (3U) +#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK) +#define DAC_C1_DMAEN_MASK (0x80U) +#define DAC_C1_DMAEN_SHIFT (7U) +#define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK) + +/*! @name C2 - DAC Control Register 2 */ +#define DAC_C2_DACBFUP_MASK (0x1U) +#define DAC_C2_DACBFUP_SHIFT (0U) +#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK) +#define DAC_C2_DACBFRP_MASK (0x10U) +#define DAC_C2_DACBFRP_SHIFT (4U) +#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK) + + +/*! + * @} + */ /* end of group DAC_Register_Masks */ + + +/* DAC - Peripheral instance base addresses */ +/** Peripheral DAC0 base address */ +#define DAC0_BASE (0x4003F000u) +/** Peripheral DAC0 base pointer */ +#define DAC0 ((DAC_Type *)DAC0_BASE) +/** Array initializer of DAC peripheral base addresses */ +#define DAC_BASE_ADDRS { DAC0_BASE } +/** Array initializer of DAC peripheral base pointers */ +#define DAC_BASE_PTRS { DAC0 } +/** Interrupt vectors for the DAC peripheral type */ +#define DAC_IRQS { DAC0_IRQn } + +/*! + * @} + */ /* end of group DAC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DCDC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCDC_Peripheral_Access_Layer DCDC Peripheral Access Layer + * @{ + */ + +/** DCDC - Register Layout Typedef */ +typedef struct { + __IO uint32_t REG0; /**< DCDC REGISTER 0, offset: 0x0 */ + __IO uint32_t REG1; /**< DCDC REGISTER 1, offset: 0x4 */ + __IO uint32_t REG2; /**< DCDC REGISTER 2, offset: 0x8 */ + __IO uint32_t REG3; /**< DCDC REGISTER 3, offset: 0xC */ + __IO uint32_t REG4; /**< DCDC REGISTER 4, offset: 0x10 */ + uint8_t RESERVED_0[4]; + __IO uint32_t REG6; /**< DCDC REGISTER 6, offset: 0x18 */ + __IO uint32_t REG7; /**< DCDC REGISTER 7, offset: 0x1C */ +} DCDC_Type; + +/* ---------------------------------------------------------------------------- + -- DCDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCDC_Register_Masks DCDC Register Masks + * @{ + */ + +/*! @name REG0 - DCDC REGISTER 0 */ +#define DCDC_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U) +#define DCDC_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U) +#define DCDC_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH_MASK) +#define DCDC_REG0_DCDC_SEL_CLK_MASK (0x4U) +#define DCDC_REG0_DCDC_SEL_CLK_SHIFT (2U) +#define DCDC_REG0_DCDC_SEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_SEL_CLK_SHIFT)) & DCDC_REG0_DCDC_SEL_CLK_MASK) +#define DCDC_REG0_DCDC_PWD_OSC_INT_MASK (0x8U) +#define DCDC_REG0_DCDC_PWD_OSC_INT_SHIFT (3U) +#define DCDC_REG0_DCDC_PWD_OSC_INT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_PWD_OSC_INT_SHIFT)) & DCDC_REG0_DCDC_PWD_OSC_INT_MASK) +#define DCDC_REG0_DCDC_LP_DF_CMP_ENABLE_MASK (0x200U) +#define DCDC_REG0_DCDC_LP_DF_CMP_ENABLE_SHIFT (9U) +#define DCDC_REG0_DCDC_LP_DF_CMP_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_LP_DF_CMP_ENABLE_SHIFT)) & DCDC_REG0_DCDC_LP_DF_CMP_ENABLE_MASK) +#define DCDC_REG0_DCDC_VBAT_DIV_CTRL_MASK (0xC00U) +#define DCDC_REG0_DCDC_VBAT_DIV_CTRL_SHIFT (10U) +#define DCDC_REG0_DCDC_VBAT_DIV_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_VBAT_DIV_CTRL_SHIFT)) & DCDC_REG0_DCDC_VBAT_DIV_CTRL_MASK) +#define DCDC_REG0_DCDC_LP_STATE_HYS_L_MASK (0x60000U) +#define DCDC_REG0_DCDC_LP_STATE_HYS_L_SHIFT (17U) +#define DCDC_REG0_DCDC_LP_STATE_HYS_L(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_LP_STATE_HYS_L_SHIFT)) & DCDC_REG0_DCDC_LP_STATE_HYS_L_MASK) +#define DCDC_REG0_DCDC_LP_STATE_HYS_H_MASK (0x180000U) +#define DCDC_REG0_DCDC_LP_STATE_HYS_H_SHIFT (19U) +#define DCDC_REG0_DCDC_LP_STATE_HYS_H(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_LP_STATE_HYS_H_SHIFT)) & DCDC_REG0_DCDC_LP_STATE_HYS_H_MASK) +#define DCDC_REG0_HYST_LP_COMP_ADJ_MASK (0x200000U) +#define DCDC_REG0_HYST_LP_COMP_ADJ_SHIFT (21U) +#define DCDC_REG0_HYST_LP_COMP_ADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_HYST_LP_COMP_ADJ_SHIFT)) & DCDC_REG0_HYST_LP_COMP_ADJ_MASK) +#define DCDC_REG0_HYST_LP_CMP_DISABLE_MASK (0x400000U) +#define DCDC_REG0_HYST_LP_CMP_DISABLE_SHIFT (22U) +#define DCDC_REG0_HYST_LP_CMP_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_HYST_LP_CMP_DISABLE_SHIFT)) & DCDC_REG0_HYST_LP_CMP_DISABLE_MASK) +#define DCDC_REG0_OFFSET_RSNS_LP_ADJ_MASK (0x800000U) +#define DCDC_REG0_OFFSET_RSNS_LP_ADJ_SHIFT (23U) +#define DCDC_REG0_OFFSET_RSNS_LP_ADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OFFSET_RSNS_LP_ADJ_SHIFT)) & DCDC_REG0_OFFSET_RSNS_LP_ADJ_MASK) +#define DCDC_REG0_OFFSET_RSNS_LP_DISABLE_MASK (0x1000000U) +#define DCDC_REG0_OFFSET_RSNS_LP_DISABLE_SHIFT (24U) +#define DCDC_REG0_OFFSET_RSNS_LP_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OFFSET_RSNS_LP_DISABLE_SHIFT)) & DCDC_REG0_OFFSET_RSNS_LP_DISABLE_MASK) +#define DCDC_REG0_DCDC_LESS_I_MASK (0x2000000U) +#define DCDC_REG0_DCDC_LESS_I_SHIFT (25U) +#define DCDC_REG0_DCDC_LESS_I(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_LESS_I_SHIFT)) & DCDC_REG0_DCDC_LESS_I_MASK) +#define DCDC_REG0_PWD_CMP_OFFSET_MASK (0x4000000U) +#define DCDC_REG0_PWD_CMP_OFFSET_SHIFT (26U) +#define DCDC_REG0_PWD_CMP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK) +#define DCDC_REG0_DCDC_XTALOK_DISABLE_MASK (0x8000000U) +#define DCDC_REG0_DCDC_XTALOK_DISABLE_SHIFT (27U) +#define DCDC_REG0_DCDC_XTALOK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_DCDC_XTALOK_DISABLE_MASK) +#define DCDC_REG0_PSWITCH_STATUS_MASK (0x10000000U) +#define DCDC_REG0_PSWITCH_STATUS_SHIFT (28U) +#define DCDC_REG0_PSWITCH_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PSWITCH_STATUS_SHIFT)) & DCDC_REG0_PSWITCH_STATUS_MASK) +#define DCDC_REG0_VLPS_CONFIG_DCDC_HP_MASK (0x20000000U) +#define DCDC_REG0_VLPS_CONFIG_DCDC_HP_SHIFT (29U) +#define DCDC_REG0_VLPS_CONFIG_DCDC_HP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_VLPS_CONFIG_DCDC_HP_SHIFT)) & DCDC_REG0_VLPS_CONFIG_DCDC_HP_MASK) +#define DCDC_REG0_VLPR_VLPW_CONFIG_DCDC_HP_MASK (0x40000000U) +#define DCDC_REG0_VLPR_VLPW_CONFIG_DCDC_HP_SHIFT (30U) +#define DCDC_REG0_VLPR_VLPW_CONFIG_DCDC_HP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_VLPR_VLPW_CONFIG_DCDC_HP_SHIFT
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