Repository: incubator-mynewt-core Updated Branches: refs/heads/develop 0a81b25c0 -> a2993a9f8
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a2993a9f/hw/mcu/nxp/mkw41z/include/mcu/cortex_m0.h ---------------------------------------------------------------------- diff --git a/hw/mcu/nxp/mkw41z/include/mcu/cortex_m0.h b/hw/mcu/nxp/mkw41z/include/mcu/cortex_m0.h new file mode 100644 index 0000000..db4cc66 --- /dev/null +++ b/hw/mcu/nxp/mkw41z/include/mcu/cortex_m0.h @@ -0,0 +1,41 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#ifndef __MCU_CORTEX_M0_H__ +#define __MCU_CORTEX_M0_H__ + +#include "mkw41z4.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * NOTE: the current timer used for this chip is a 1 kHz clock. Thus, the + * number of OS ticks per second should be a multiple of 1000. If interrupts + * are disabled for longer than an ostick it is possible that os time will not + * be accurate. + */ +#define OS_TICKS_PER_SEC (1000) + +#ifdef __cplusplus +} +#endif + +#endif /* __MCU_CORTEX_M0_H__ */ http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a2993a9f/hw/mcu/nxp/mkw41z/include/mcu/fsl_device_registers.h ---------------------------------------------------------------------- diff --git a/hw/mcu/nxp/mkw41z/include/mcu/fsl_device_registers.h b/hw/mcu/nxp/mkw41z/include/mcu/fsl_device_registers.h new file mode 100644 index 0000000..9a42bad --- /dev/null +++ b/hw/mcu/nxp/mkw41z/include/mcu/fsl_device_registers.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2014 - 2016, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MKW41Z256VHT4) || defined(CPU_MKW41Z512VHT4)) + +#define KW41Z4_SERIES + +/* CMSIS-style register definitions */ +#include "MKW41Z4.h" +/* CPU specific feature definitions */ +#include "MKW41Z4_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a2993a9f/hw/mcu/nxp/mkw41z/include/mcu/mcu.h ---------------------------------------------------------------------- diff --git a/hw/mcu/nxp/mkw41z/include/mcu/mcu.h b/hw/mcu/nxp/mkw41z/include/mcu/mcu.h new file mode 100644 index 0000000..7451c57 --- /dev/null +++ b/hw/mcu/nxp/mkw41z/include/mcu/mcu.h @@ -0,0 +1,38 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#ifndef __MCU_MCU_H_ +#define __MCU_MCU_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Defines for naming GPIOs. + */ +#define MCU_GPIO_PORTA(pin) ((0 * 32) + (pin)) +#define MCU_GPIO_PORTB(pin) ((1 * 32) + (pin)) +#define MCU_GPIO_PORTC(pin) ((2 * 32) + (pin)) + +#ifdef __cplusplus +} +#endif + +#endif /* __MCU_MCU_H_ */ http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a2993a9f/hw/mcu/nxp/mkw41z/include/mcu/mkw41z_hal.h ---------------------------------------------------------------------- diff --git a/hw/mcu/nxp/mkw41z/include/mcu/mkw41z_hal.h b/hw/mcu/nxp/mkw41z/include/mcu/mkw41z_hal.h new file mode 100755 index 0000000..a65e3c3 --- /dev/null +++ b/hw/mcu/nxp/mkw41z/include/mcu/mkw41z_hal.h @@ -0,0 +1,46 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#ifndef H_MKW41Z_HAL_ +#define H_MKW41Z_HAL_ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Helper functions to enable/disable interrupts. */ +#define __HAL_DISABLE_INTERRUPTS(x) \ + do { \ + x = __get_PRIMASK(); \ + __disable_irq(); \ + } while(0); + +#define __HAL_ENABLE_INTERRUPTS(x) \ + do { \ + if (!x) { \ + __enable_irq(); \ + } \ + } while(0); + +#ifdef __cplusplus +} +#endif + +#endif /* H_MKW41Z_HAL_ */ + http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a2993a9f/hw/mcu/nxp/mkw41z/include/mcu/system_MKW41Z4.h ---------------------------------------------------------------------- diff --git a/hw/mcu/nxp/mkw41z/include/mcu/system_MKW41Z4.h b/hw/mcu/nxp/mkw41z/include/mcu/system_MKW41Z4.h new file mode 100644 index 0000000..655328d --- /dev/null +++ b/hw/mcu/nxp/mkw41z/include/mcu/system_MKW41Z4.h @@ -0,0 +1,133 @@ +/* +** ################################################################### +** Processors: MKW41Z256VHT4 +** MKW41Z512VHT4 +** +** Compilers: Keil ARM C/C++ Compiler +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: MKW41Z512RM Rev. 0.1, 04/2016 +** Version: rev. 1.0, 2015-09-23 +** Build: b160720 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: [email protected] +** +** Revisions: +** - rev. 1.0 (2015-09-23) +** Initial version. +** +** ################################################################### +*/ + +/*! + * @file MKW41Z4 + * @version 1.0 + * @date 2015-09-23 + * @brief Device specific configuration file for MKW41Z4 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MKW41Z4_H_ +#define _SYSTEM_MKW41Z4_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include <stdint.h> + + +#ifndef DISABLE_WDOG + #define DISABLE_WDOG 1 +#endif + +/* Define clock source values */ + +#define CPU_XTAL_CLK_HZ 32000000u /* Value of the external crystal or oscillator clock frequency in Hz */ +#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ +#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ +#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ + +/* RF oscillator setting */ +#define SYSTEM_RSIM_CONTROL_VALUE 0xC00100U /* Enable RF oscillator in Run/Wait mode */ + +/* Low power mode enable */ + +/* SMC_PMPROT: ?=0,?=0,AVLP=1,?=0,?=0,?=0,AVLLS=1,?=0 */ +#define SYSTEM_SMC_PMPROT_VALUE (SMC_PMPROT_AVLP_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLLS_MASK) /* Mask of allowed low power modes used to initialize power modes protection register */ + +#define DEFAULT_SYSTEM_CLOCK 20971520U /* Default System clock value */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MKW41Z4_H_ */ http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a2993a9f/hw/mcu/nxp/mkw41z/pkg.yml ---------------------------------------------------------------------- diff --git a/hw/mcu/nxp/mkw41z/pkg.yml b/hw/mcu/nxp/mkw41z/pkg.yml new file mode 100644 index 0000000..4042296 --- /dev/null +++ b/hw/mcu/nxp/mkw41z/pkg.yml @@ -0,0 +1,31 @@ +# +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +pkg.name: hw/mcu/nxp/mkw41z +pkg.description: MCU definition for NXP MKW41Z ARM Cortex-M0 chips. +pkg.author: "Apache Mynewt <[email protected]>" +pkg.homepage: "http://mynewt.apache.org/"; +pkg.keywords: + - mkw41z + - nxp + +pkg.deps: + - compiler/arm-none-eabi-m0 + - hw/cmsis-core + - hw/hal http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a2993a9f/hw/mcu/nxp/mkw41z/src/hal_gpio.c ---------------------------------------------------------------------- diff --git a/hw/mcu/nxp/mkw41z/src/hal_gpio.c b/hw/mcu/nxp/mkw41z/src/hal_gpio.c new file mode 100644 index 0000000..290bb49 --- /dev/null +++ b/hw/mcu/nxp/mkw41z/src/hal_gpio.c @@ -0,0 +1,161 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include <assert.h> +#include "hal/hal_gpio.h" +#include "bsp/cmsis_nvic.h" + +/** + * gpio init in + * + * Initializes the specified pin as an input + * + * @param pin Pin number to set as input + * @param pull pull type + * + * @return int 0: no error; -1 otherwise. + */ +int +hal_gpio_init_in(int pin, hal_gpio_pull_t pull) +{ + return 0; +} + +/** + * gpio init out + * + * Initialize the specified pin as an output, setting the pin to the specified + * value. + * + * @param pin Pin number to set as output + * @param val Value to set pin + * + * @return int 0: no error; -1 otherwise. + */ +int +hal_gpio_init_out(int pin, int val) +{ + return 0; +} + +/** + * gpio write + * + * Write a value (either high or low) to the specified pin. + * + * @param pin Pin to set + * @param val Value to set pin (0:low 1:high) + */ +void +hal_gpio_write(int pin, int val) +{ + return; +} + +/** + * gpio read + * + * Reads the specified pin. + * + * @param pin Pin number to read + * + * @return int 0: low, 1: high + */ +int +hal_gpio_read(int pin) +{ + return 0; +} + +/** + * gpio toggle + * + * Toggles the specified pin + * + * @param pin Pin number to toggle + * + * @return current pin state int 0: low, 1: high + */ +int +hal_gpio_toggle(int pin) +{ + int pin_state = (hal_gpio_read(pin) == 0); + hal_gpio_write(pin, pin_state); + return pin_state; +} + +/** + * gpio irq init + * + * Initialize an external interrupt on a gpio pin + * + * @param pin Pin number to enable gpio. + * @param handler Interrupt handler + * @param arg Argument to pass to interrupt handler + * @param trig Trigger mode of interrupt + * @param pull Push/pull mode of input. + * + * @return int + */ +int +hal_gpio_irq_init(int pin, hal_gpio_irq_handler_t handler, void *arg, + hal_gpio_irq_trig_t trig, hal_gpio_pull_t pull) +{ + return 0; +} + +/** + * gpio irq release + * + * No longer interrupt when something occurs on the pin. NOTE: this function + * does not change the GPIO push/pull setting. + * It also does not disable the NVIC interrupt enable setting for the irq. + * + * @param pin + */ +void +hal_gpio_irq_release(int pin) +{ + return; +} + +/** + * gpio irq enable + * + * Enable the irq on the specified pin + * + * @param pin + */ +void +hal_gpio_irq_enable(int pin) +{ + return; +} + +/** + * gpio irq disable + * + * + * @param pin + */ +void +hal_gpio_irq_disable(int pin) +{ + return; +} http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a2993a9f/hw/mcu/nxp/mkw41z/src/hal_os_tick.c ---------------------------------------------------------------------- diff --git a/hw/mcu/nxp/mkw41z/src/hal_os_tick.c b/hw/mcu/nxp/mkw41z/src/hal_os_tick.c new file mode 100644 index 0000000..502cbb3 --- /dev/null +++ b/hw/mcu/nxp/mkw41z/src/hal_os_tick.c @@ -0,0 +1,104 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ +#include <assert.h> +#include <os/os.h> +#include "syscfg/syscfg.h" +#include <hal/hal_os_tick.h> +#include <bsp/cmsis_nvic.h> +//#include <mkw41z4.h> +#include <mcu/mkw41z_hal.h> + +/* Timer frequency used for os tick */ +#define MKW41Z_LPTMR_FREQ (1000) /* in Hz */ + +static uint16_t timer_ticks_per_ostick; + +/* + * LPTMR irq handler + * + * This IRQ handles OS time. Currently, this MCU does not have the tickless + * OS implemented. It is also possible to miss OS ticks if interrupts are + * disabled for too long (longer than one tick). + */ +static void +mkw41z_os_tick_handler(void) +{ + uint32_t csr; + uint32_t sr; + + OS_ENTER_CRITICAL(sr); + + /* Must make sure flag is set when we get interrupt */ + csr = LPTMR0->CSR; + if (csr & LPTMR_CSR_TCF_MASK) { + /* Advance os time */ + os_time_advance(1); + + /* Clear mask */ + LPTMR0->CSR = csr; + } + + OS_EXIT_CRITICAL(sr); +} + +void +os_tick_idle(os_time_t ticks) +{ + OS_ASSERT_CRITICAL(); + + __DSB(); + __WFI(); +} + +void +os_tick_init(uint32_t os_ticks_per_sec, int prio) +{ + uint32_t ctx; + uint32_t prescaler_reg; + + /* Make os ticks per sec divides evenly into frequency */ + timer_ticks_per_ostick = MKW41Z_LPTMR_FREQ / os_ticks_per_sec; + assert((timer_ticks_per_ostick * os_ticks_per_sec) == MKW41Z_LPTMR_FREQ); + + /* disable interrupts */ + __HAL_DISABLE_INTERRUPTS(ctx); + + /* Enable access to LPTMR module. LPTMR is bit 0 */ + SIM->SCGC5 |= 1; + + /* Make sure timer is disabled */ + LPTMR0->CSR = 0; + + /* Set isr in vector table and enable interrupt */ + NVIC_SetPriority(LPTMR0_IRQn, prio); + NVIC_SetVector(LPTMR0_IRQn, (uint32_t)mkw41z_os_tick_handler); + NVIC_EnableIRQ(LPTMR0_IRQn); + + /* Set prescaler register. Bypass prescalar and use LPO (clock 1) */ + prescaler_reg = LPTMR_PSR_PBYP_MASK | 1; + LPTMR0->PSR = prescaler_reg; + + /* Write output compare while disabled */ + LPTMR0->CMR = timer_ticks_per_ostick - 1; + + /* Enable the timer: note you cannot alter bits 5 to 1 (inclusive) */ + LPTMR0->CSR = LPTMR_CSR_TIE_MASK | LPTMR_CSR_TEN_MASK; + + __HAL_ENABLE_INTERRUPTS(ctx); +} http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a2993a9f/hw/mcu/nxp/mkw41z/src/hal_system.c ---------------------------------------------------------------------- diff --git a/hw/mcu/nxp/mkw41z/src/hal_system.c b/hw/mcu/nxp/mkw41z/src/hal_system.c new file mode 100644 index 0000000..62379a7 --- /dev/null +++ b/hw/mcu/nxp/mkw41z/src/hal_system.c @@ -0,0 +1,37 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include <mcu/cortex_m0.h> +#include "hal/hal_system.h" + +void +hal_system_reset(void) +{ + while (1) { + NVIC_SystemReset(); + } +} + +int +hal_debugger_connected(void) +{ + /* XXX is there a way? */ + return 0; +} + http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a2993a9f/hw/mcu/nxp/mkw41z/src/hal_watchdog.c ---------------------------------------------------------------------- diff --git a/hw/mcu/nxp/mkw41z/src/hal_watchdog.c b/hw/mcu/nxp/mkw41z/src/hal_watchdog.c new file mode 100644 index 0000000..c41ab64 --- /dev/null +++ b/hw/mcu/nxp/mkw41z/src/hal_watchdog.c @@ -0,0 +1,41 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include <assert.h> +#include "hal/hal_watchdog.h" +#include "bsp/cmsis_nvic.h" + +int +hal_watchdog_init(uint32_t expire_msecs) +{ + return 0; +} + +void +hal_watchdog_enable(void) +{ + return; +} + +void +hal_watchdog_tickle(void) +{ + return; +} + http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a2993a9f/hw/mcu/nxp/mkw41z/src/system_MKW41Z4.c ---------------------------------------------------------------------- diff --git a/hw/mcu/nxp/mkw41z/src/system_MKW41Z4.c b/hw/mcu/nxp/mkw41z/src/system_MKW41Z4.c new file mode 100644 index 0000000..5e7b243 --- /dev/null +++ b/hw/mcu/nxp/mkw41z/src/system_MKW41Z4.c @@ -0,0 +1,179 @@ +/* +** ################################################################### +** Processors: MKW41Z256VHT4 +** MKW41Z512VHT4 +** +** Compilers: Keil ARM C/C++ Compiler +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: MKW41Z512RM Rev. 0.1, 04/2016 +** Version: rev. 1.0, 2015-09-23 +** Build: b160720 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: [email protected] +** +** Revisions: +** - rev. 1.0 (2015-09-23) +** Initial version. +** +** ################################################################### +*/ + +/*! + * @file MKW41Z4 + * @version 1.0 + * @date 2015-09-23 + * @brief Device specific configuration file for MKW41Z4 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include <stdint.h> +#include "mcu/fsl_device_registers.h" +#include "bsp/cmsis_nvic.h" + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +void SystemInit (void) { + +#if (DISABLE_WDOG) + /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */ + SIM->COPC = (uint32_t)0x00u; +#endif /* (DISABLE_WDOG) */ + + NVIC_Relocate(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { + + uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */ + uint16_t Divider; + + if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) { + /* FLL is selected */ + if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) { + /* External reference clock is selected */ + if((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x00U) { + MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ + } else { + MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ + } + if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { + switch (MCG->C1 & MCG_C1_FRDIV_MASK) { + case 0x38U: + Divider = 1536U; + break; + case 0x30U: + Divider = 1280U; + break; + default: + Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); + break; + } + } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */ + Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); + } + MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ + } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */ + MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */ + } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */ + /* Select correct multiplier to calculate the MCG output clock */ + switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { + case 0x00U: + MCGOUTClock *= 640U; + break; + case 0x20U: + MCGOUTClock *= 1280U; + break; + case 0x40U: + MCGOUTClock *= 1920U; + break; + case 0x60U: + MCGOUTClock *= 2560U; + break; + case 0x80U: + MCGOUTClock *= 732U; + break; + case 0xA0U: + MCGOUTClock *= 1464U; + break; + case 0xC0U: + MCGOUTClock *= 2197U; + break; + case 0xE0U: + MCGOUTClock *= 2929U; + break; + default: + break; + } + } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) { + /* Internal reference clock is selected */ + if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) { + MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */ + } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */ + Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); + MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */ + } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */ + } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) { + /* External reference clock is selected */ + if((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x00U) { + MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ + } else { + MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ + } + } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */ + /* Reserved value */ + return; + } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */ + SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT))); + +}
