hartmannathan commented on a change in pull request #1051: URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426281875
########## File path: arch/arm/src/stm32/hardware/stm32g47xxx_pwr.h ########## @@ -0,0 +1,485 @@ +/**************************************************************************** + * arch/arm/src/stm32/hardware/stm32g47xxx_pwr.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_PWR_H +#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_PWR_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_PWR_CR1_OFFSET 0x0000 /* PWR Power Control Register 1 */ +#define STM32_PWR_CR2_OFFSET 0x0004 /* PWR Power Control Register 2 */ +#define STM32_PWR_CR3_OFFSET 0x0008 /* PWR Power Control Register 3 */ +#define STM32_PWR_CR4_OFFSET 0x000c /* PWR Power Control Register 4 */ +#define STM32_PWR_SR1_OFFSET 0x0010 /* PWR Power Status Register 1 */ +#define STM32_PWR_SR2_OFFSET 0x0014 /* PWR Power Status Register 2 */ +#define STM32_PWR_SCR_OFFSET 0x0018 /* PWR Power Status Reset Register */ + /* Offset 0x001c Reserved */ +#define STM32_PWR_PUCRA_OFFSET 0x0020 /* Power Port A Pull Up Control Register */ +#define STM32_PWR_PDCRA_OFFSET 0x0024 /* Power Port A Pull Down Control Register */ +#define STM32_PWR_PUCRB_OFFSET 0x0028 /* Power Port B Pull Up Control Register */ +#define STM32_PWR_PDCRB_OFFSET 0x002c /* Power Port B Pull Down Control Register */ +#define STM32_PWR_PUCRC_OFFSET 0x0030 /* Power Port C Pull Up Control Register */ +#define STM32_PWR_PDCRC_OFFSET 0x0034 /* Power Port C Pull Down Control Register */ +#define STM32_PWR_PUCRD_OFFSET 0x0038 /* Power Port D Pull Up Control Register */ +#define STM32_PWR_PDCRD_OFFSET 0x003c /* Power Port D Pull Down Control Register */ +#define STM32_PWR_PUCRE_OFFSET 0x0040 /* Power Port E Pull Up Control Register */ +#define STM32_PWR_PDCRE_OFFSET 0x0044 /* Power Port E Pull Down Control Register */ +#define STM32_PWR_PUCRF_OFFSET 0x0048 /* Power Port F Pull Up Control Register */ +#define STM32_PWR_PDCRF_OFFSET 0x004c /* Power Port F Pull Down Control Register */ +#define STM32_PWR_PUCRG_OFFSET 0x0050 /* Power Port G Pull Up Control Register */ +#define STM32_PWR_PDCRG_OFFSET 0x0054 /* Power Port G Pull Down Control Register */ + /* Offset 0x0058 Reserved */ + /* Offset 0x005C Reserved */ + /* Offset 0x0060 Reserved */ + /* Offset 0x0064 Reserved */ + /* Offset 0x0068 Reserved */ + /* Offset 0x006C Reserved */ + /* Offset 0x0070 Reserved */ + /* Offset 0x0074 Reserved */ + /* Offset 0x0078 Reserved */ + /* Offset 0x007C Reserved */ +#define STM32_PWR_CR5_OFFSET 0x0080 /* PWR Power Control Register 5 */ + +/* Register Addresses *******************************************************/ + +#define STM32_PWR_CR1 (STM32_PWR_BASE + STM32_PWR_CR1_OFFSET) +#define STM32_PWR_CR2 (STM32_PWR_BASE + STM32_PWR_CR2_OFFSET) +#define STM32_PWR_CR3 (STM32_PWR_BASE + STM32_PWR_CR3_OFFSET) +#define STM32_PWR_CR4 (STM32_PWR_BASE + STM32_PWR_CR4_OFFSET) +#define STM32_PWR_SR1 (STM32_PWR_BASE + STM32_PWR_SR1_OFFSET) +#define STM32_PWR_SR2 (STM32_PWR_BASE + STM32_PWR_SR2_OFFSET) +#define STM32_PWR_SCR (STM32_PWR_BASE + STM32_PWR_SCR_OFFSET) +#define STM32_PWR_PUCRA (STM32_PWR_BASE + STM32_PWR_PUCRA_OFFSET) +#define STM32_PWR_PDCRA (STM32_PWR_BASE + STM32_PWR_PDCRA_OFFSET) +#define STM32_PWR_PUCRB (STM32_PWR_BASE + STM32_PWR_PUCRB_OFFSET) +#define STM32_PWR_PDCRB (STM32_PWR_BASE + STM32_PWR_PDCRB_OFFSET) +#define STM32_PWR_PUCRC (STM32_PWR_BASE + STM32_PWR_PUCRC_OFFSET) +#define STM32_PWR_PDCRC (STM32_PWR_BASE + STM32_PWR_PDCRC_OFFSET) +#define STM32_PWR_PUCRD (STM32_PWR_BASE + STM32_PWR_PUCRD_OFFSET) +#define STM32_PWR_PDCRD (STM32_PWR_BASE + STM32_PWR_PDCRD_OFFSET) +#define STM32_PWR_PUCRE (STM32_PWR_BASE + STM32_PWR_PUCRE_OFFSET) +#define STM32_PWR_PDCRE (STM32_PWR_BASE + STM32_PWR_PDCRE_OFFSET) +#define STM32_PWR_PUCRF (STM32_PWR_BASE + STM32_PWR_PUCRF_OFFSET) +#define STM32_PWR_PDCRF (STM32_PWR_BASE + STM32_PWR_PDCRF_OFFSET) +#define STM32_PWR_PUCRG (STM32_PWR_BASE + STM32_PWR_PUCRG_OFFSET) +#define STM32_PWR_PDCRG (STM32_PWR_BASE + STM32_PWR_PDCRG_OFFSET) +#define STM32_PWR_CR5 (STM32_PWR_BASE + STM32_PWR_CR5_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* PWR Power Control Register 1 (CR1) */ + +#define PWR_CR1_LPR_SHIFT (14) /* Low Power Run */ +#define PWR_CR1_LPR (0x1 << PWR_CR1_LPR_SHIFT) +#define PWR_CR1_VOS_SHIFT (9) /* Voltage Scaling Range Selection */ +#define PWR_CR1_VOS_MASK (0x3 << PWR_CR1_VOS_SHIFT) +# define PWR_CR1_VOS_RANGE_1 (0x1 << PWR_CR1_VOS_SHIFT) +# define PWR_CR1_VOS_RANGE_2 (0x2 << PWR_CR1_VOS_SHIFT) +#define PWR_CR1_DBP_SHIFT (8) /* Disable Backup Domain Write Protection */ +#define PWR_CR1_DBP (0x1 << PWR_CR1_DBP_SHIFT) +#define PWR_CR1_LPMS_SHIFT (0) /* Low Power Mode Selection */ +#define PWR_CR1_LPMS_MASK (0x7 << PWR_CR1_LPMS_SHIFT) +# define PWR_CR1_LPMS_STOP_0 (0x0 << PWR_CR1_LPMS_SHIFT) /* Stop 0 Mode */ +# define PWR_CR1_LPMS_STOP_1 (0x1 << PWR_CR1_LPMS_SHIFT) /* Stop 1 Mode */ +# define PWR_CR1_LPMS_STANDBY (0x3 << PWR_CR1_LPMS_SHIFT) /* Standby Mode */ +# define PWR_CR1_LPMS_SHUTDOWN (0x4 << PWR_CR1_LPMS_SHIFT) /* Shutdown Mode */ + +/* PWR Power Control Register 2 (CR2) */ + +#define PWR_CR2_PVMEN2_SHIFT (7) /* Peripheral Voltage Monitoring 4 Enable (VDDA vs DAC 1Msps or 15Msps Minimum Voltage) */ +#define PWR_CR2_PVMEN2 (0x1 << PWR_CR2_PVMEN2_SHIFT) +#define PWR_CR2_PVMEN1_SHIFT (6) /* Peripheral Voltage Monitoring 3 Enable (VDDA vs ADC or COMP Minimum Voltage) */ +#define PWR_CR2_PVMEN1 (0x1 << PWR_CR2_PVMEN1_SHIFT) +#define PWR_CR2_PLS_SHIFT (1) /* Power Voltage Detector Level Selection */ +#define PWR_CR2_PLS_MASK (0x7 << PWR_CR2_PLS_SHIFT) +# define PWR_CR2_PLS_0 (0x0 << PWR_CR2_PLS_SHIFT) +# define PWR_CR2_PLS_1 (0x1 << PWR_CR2_PLS_SHIFT) +# define PWR_CR2_PLS_2 (0x2 << PWR_CR2_PLS_SHIFT) +# define PWR_CR2_PLS_3 (0x3 << PWR_CR2_PLS_SHIFT) +# define PWR_CR2_PLS_4 (0x4 << PWR_CR2_PLS_SHIFT) +# define PWR_CR2_PLS_5 (0x5 << PWR_CR2_PLS_SHIFT) +# define PWR_CR2_PLS_6 (0x6 << PWR_CR2_PLS_SHIFT) +# define PWR_CR2_PLS_7 (0x7 << PWR_CR2_PLS_SHIFT) +#define PWR_CR2_PVDE_SHIFT (0) /* Power Voltage Detector Enable */ +#define PWR_CR2_PVDE (0x1 << PWR_CR2_PVDE_SHIFT) + +/* PWR Power Control Register 3 (CR3) */ + +#define PWR_CR3_EIWUL_SHIFT (15) /* Enable Internal Wake Up Line */ +#define PWR_CR3_EIWUL (0x1 << PWR_CR3_EIWUL_SHIFT) +#define PWR_CR3_UCPD1_DBDIS_SHIFT (14) /* USB Type C And Power Delivery Dead Battery Disable */ +#define PWR_CR3_UCPD1_DBDIS (0x1 << PWR_CR3_UCPD1_DBDIS_SHIFT) +#define PWR_CR3_UCPD1_STDBY_SHIFT (13) /* USB Type C And Power Delivery Standby Mode */ +#define PWR_CR3_UCPD1_STDBY (0x1 << PWR_CR3_UCPD1_STDBY_SHIFT) +#define PWR_CR3_APC_SHIFT (10) /* Apply Pull Up And Pull Down Configuration */ +#define PWR_CR3_APC (0x1 << PWR_CR3_APC_SHIFT) +#define PWR_CR3_RRS_SHIFT (8) /* SRAM2 Retention In Standby Mode */ +#define PWR_CR3_RRS (0x1 << PWR_CR3_RRS_SHIFT) +#define PWR_CR3_EWUP5_SHIFT (4) /* Enable Wake Up Pin WKUP5 */ +#define PWR_CR3_EWUP5 (0x1 << PWR_CR3_EWUP5_SHIFT) +#define PWR_CR3_EWUP4_SHIFT (3) /* Enable Wake Up Pin WKUP4 */ +#define PWR_CR3_EWUP4 (0x1 << PWR_CR3_EWUP4_SHIFT) +#define PWR_CR3_EWUP3_SHIFT (2) /* Enable Wake Up Pin WKUP3 */ +#define PWR_CR3_EWUP3 (0x1 << PWR_CR3_EWUP3_SHIFT) +#define PWR_CR3_EWUP2_SHIFT (1) /* Enable Wake Up Pin WKUP2 */ +#define PWR_CR3_EWUP2 (0x1 << PWR_CR3_EWUP2_SHIFT) +#define PWR_CR3_EWUP1_SHIFT (0) /* Enable Wake Up Pin WKUP1 */ +#define PWR_CR3_EWUP1 (0x1 << PWR_CR3_EWUP1_SHIFT) + +/* PWR Power Control Register 4 (CR4) */ + +#define PWR_CR4_VBRS_SHIFT (9) /* VBAT Battery charging Resistor Selection */ +#define PWR_CR4_VBRS (0x1 << PWR_CR4_VBRS_SHIFT) +#define PWR_CR4_VBE_SHIFT (8) /* VBAT Battery charging Enable */ +#define PWR_CR4_VBE (0x1 << PWR_CR4_VBE_SHIFT) +#define PWR_CR4_WP5_SHIFT (4) /* Wake Up Pin WKUP5 polarity */ +#define PWR_CR4_WP5 (0x1 << PWR_CR4_WP5_SHIFT) +#define PWR_CR4_WP4_SHIFT (3) /* Wake Up Pin WKUP4 polarity */ +#define PWR_CR4_WP4 (0x1 << PWR_CR4_WP4_SHIFT) +#define PWR_CR4_WP3_SHIFT (2) /* Wake Up Pin WKUP3 polarity */ +#define PWR_CR4_WP3 (0x1 << PWR_CR4_WP3_SHIFT) +#define PWR_CR4_WP2_SHIFT (1) /* Wake Up Pin WKUP2 polarity */ +#define PWR_CR4_WP2 (0x1 << PWR_CR4_WP2_SHIFT) +#define PWR_CR4_WP1_SHIFT (0) /* Wake Up Pin WKUP1 polarity */ +#define PWR_CR4_WP1 (0x1 << PWR_CR4_WP1_SHIFT) + +/* PWR Power Status Register 1 (SR1) */ + +#define PWR_SR1_WUFI_SHIFT (15) /* Wake Up Flag Internal */ +#define PWR_SR1_WUFI (0x1 << PWR_SR1_WUFI_SHIFT) +#define PWR_SR1_SBF_SHIFT (8) /* Stand-By Flag */ +#define PWR_SR1_SBF (0x1 << PWR_SR1_SBF_SHIFT) +#define PWR_SR1_WUF_SHIFT (0) /* Wake Up Flags */ +#define PWR_SR1_WUF_MASK (0x1f << PWR_SR1_WUF_SHIFT) +# define PWR_SR1_WUF5 (0x10 << PWR_SR1_WUF_SHIFT) /* Wake Up Flag 5 */ +# define PWR_SR1_WUF4 (0x8 << PWR_SR1_WUF_SHIFT) /* Wake Up Flag 4 */ +# define PWR_SR1_WUF3 (0x4 << PWR_SR1_WUF_SHIFT) /* Wake Up Flag 3 */ +# define PWR_SR1_WUF2 (0x2 << PWR_SR1_WUF_SHIFT) /* Wake Up Flag 2 */ +# define PWR_SR1_WUF1 (0x1 << PWR_SR1_WUF_SHIFT) /* Wake Up Flag 1 */ + +/* PWR Power Status Register 2 (SR2) */ + +#define PWR_SR2_PVMO4_SHIFT (15) /* Peripheral Voltage Monitoring Output 4 */ +#define PWR_SR2_PVMO4 (0x1 << PWR_SR2_PVMO4_SHIFT) +#define PWR_SR2_PVMO3_SHIFT (14) /* Peripheral Voltage Monitoring Output 3 */ +#define PWR_SR2_PVMO3 (0x1 << PWR_SR2_PVMO3_SHIFT) +#define PWR_SR2_PVMO2_SHIFT (13) /* Peripheral Voltage Monitoring Output 2 */ +#define PWR_SR2_PVMO2 (0x1 << PWR_SR2_PVMO2_SHIFT) +#define PWR_SR2_PVMO1_SHIFT (12) /* Peripheral Voltage Monitoring Output 1 */ +#define PWR_SR2_PVMO1 (0x1 << PWR_SR2_PVMO1_SHIFT) +#define PWR_SR2_PVDO_SHIFT (11) /* Power Voltage Detector Output */ +#define PWR_SR2_PVDO (0x1 << PWR_SR2_PVDO_SHIFT) +#define PWR_SR2_VOSF_SHIFT (10) /* Voltage Scaling Flag */ +#define PWR_SR2_VOSF (0x1 << PWR_SR2_VOSF_SHIFT) +#define PWR_SR2_REGLPF_SHIFT (9) /* Low-power Regulator Flag */ +#define PWR_SR2_REGLPF (0x1 << PWR_SR2_REGLPF_SHIFT) +#define PWR_SR2_REGLPS_SHIFT (8) /* Low-power Regulator Started */ +#define PWR_SR2_REGLPS (0x1 << PWR_SR2_REGLPS_SHIFT) +#define PWR_SR2_FLASHRDY_SHIFT (7) /* Flash Ready Flag */ +#define PWR_SR2_FLASHRDY (0x1 << PWR_SR2_FLASHRDY_SHIFT) + +/* PWR Power Status Reset Register (SCR) */ + +#define PWR_SCR_CSBF_SHIFT (8) /* Clear Standby Flag */ Review comment: Fixed in 076cceb7b7da7510a6c7aed40cae7789343956c0. ---------------------------------------------------------------- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. For queries about this service, please contact Infrastructure at: us...@infra.apache.org
