yf13 commented on code in PR #11379:
URL: https://github.com/apache/nuttx/pull/11379#discussion_r1426091218
##########
arch/risc-v/src/common/riscv_mtimer.c:
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@@ -83,7 +83,7 @@ static const struct oneshot_operations_s g_riscv_mtimer_ops =
#ifndef CONFIG_ARCH_USE_S_MODE
static uint64_t riscv_mtimer_get_mtime(struct riscv_mtimer_lowerhalf_s *priv)
{
-#ifdef CONFIG_ARCH_RV64
+#if defined(CONFIG_ARCH_RV64) && !defined(CONFIG_ARCH_CHIP_K230)
Review Comment:
@xiaoxiang781216 Good catch! This is quick-n-dirty solution as I mentioned
in maillist.
The current common design assumes MMIO width is alway same as CPU width.
This is not true for chips like K230 (64-bit CPU with 32-bit MMIO only).
Other solutions I can think of are:
a) See if current RiscV layer design already allows overriding this common
layer behavior at chip specific layer.
b) Refactoring the common layer so that to use explicit config options for
MMIO width choice. However, doing this will need broader consensus as it
impacts all Risc-V ports, if MMIO_WIDTH != ARCH_WIDTH also holds for other
architecture, then the new option may go beyond RiscV scope.
As I am new with NuttX, I don't know if option [a] holds or not at this
time. If it doesn't hold, then I would suggest to take current solution first.
Then solve option [b], then clean up this dirty one.
Please teach your suggestions.
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