yf13 commented on code in PR #11379:
URL: https://github.com/apache/nuttx/pull/11379#discussion_r1427483175
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arch/risc-v/src/common/riscv_mtimer.c:
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@@ -83,7 +83,7 @@ static const struct oneshot_operations_s g_riscv_mtimer_ops =
#ifndef CONFIG_ARCH_USE_S_MODE
static uint64_t riscv_mtimer_get_mtime(struct riscv_mtimer_lowerhalf_s *priv)
{
-#ifdef CONFIG_ARCH_RV64
+#if defined(CONFIG_ARCH_RV64) && !defined(CONFIG_ARCH_CHIP_K230)
Review Comment:
@xiaoxiang781216
if you are sure that non-RISCV architectures won't have this different MMIO
width issue, I am fine to contain the issue within RISCV scope for now.
Otherwise later you will see that ARCH_MMIO_NO_64BIT is more proper.
On the other side I am concerned with this NO_64BIT style design as when 128
bit RiscV chip arrives later you will need add MMIO_NO_128BIT.
Maybe we can consider explicit options like::
- two booleans like `ARCH_RV_MMIO_64BIT` and `ARCH_RV_MMIO_32BIT`?
- one enum like `ARCH_RV_MMIO_BITS`?
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