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commit 3ee422766870c51b2c51d29387d87b257da08d8a Author: chao an <[email protected]> AuthorDate: Mon Jan 15 20:55:24 2024 +0800 risc-v/toolchain: add "Q" Standard Extension into command line "Q" Standard Extension for Quad-Precision Floating-Point Signed-off-by: chao an <[email protected]> --- arch/risc-v/src/common/Toolchain.defs | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/arch/risc-v/src/common/Toolchain.defs b/arch/risc-v/src/common/Toolchain.defs index 3d0e5296a9..8a2f969c04 100644 --- a/arch/risc-v/src/common/Toolchain.defs +++ b/arch/risc-v/src/common/Toolchain.defs @@ -148,29 +148,35 @@ ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVG) # Detect cpu ISA support flags + ARCHCPUEXTFLAGS = i + ifeq ($(CONFIG_ARCH_RV_ISA_M),y) - ARCHRVISAM = m + ARCHCPUEXTFLAGS := $(ARCHCPUEXTFLAGS)m endif ifeq ($(CONFIG_ARCH_RV_ISA_A),y) - ARCHRVISAA = a - endif - - ifeq ($(CONFIG_ARCH_RV_ISA_C),y) - ARCHRVISAC = c + ARCHCPUEXTFLAGS := $(ARCHCPUEXTFLAGS)a endif ifeq ($(CONFIG_ARCH_FPU),y) - ARCHRVISAF = f + ARCHCPUEXTFLAGS := $(ARCHCPUEXTFLAGS)f endif ifeq ($(CONFIG_ARCH_DPFPU),y) - ARCHRVISAD = d + ARCHCPUEXTFLAGS := $(ARCHCPUEXTFLAGS)d + endif + + ifeq ($(CONFIG_ARCH_QPFPU),y) + ARCHCPUEXTFLAGS := $(ARCHCPUEXTFLAGS)q + endif + + ifeq ($(CONFIG_ARCH_RV_ISA_C),y) + ARCHCPUEXTFLAGS := $(ARCHCPUEXTFLAGS)c endif GCC_VERSION = ${shell $(CROSSDEV)gcc --version | grep gcc | grep -oE '[0-9]+\.[0-9]+\.[0-9]+' | tail -n 1 | cut -d"." -f1 } ifeq ($(shell expr $(GCC_VERSION) \>= 12), 1) - ARCHRVISAZ = _zicsr_zifencei + ARCHCPUEXTFLAGS := $(ARCHCPUEXTFLAGS)_zicsr_zifencei endif # Detect abi type @@ -189,7 +195,6 @@ ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVG) # Construct arch flags - ARCHCPUEXTFLAGS = i$(ARCHRVISAM)$(ARCHRVISAA)$(ARCHRVISAF)$(ARCHRVISAD)$(ARCHRVISAC)$(ARCHRVISAZ) ARCHCPUFLAGS += -march=$(ARCHTYPE)$(ARCHCPUEXTFLAGS) # Construct arch abi flags
