tmedicci commented on PR #13222: URL: https://github.com/apache/nuttx/pull/13222#issuecomment-2322276572
> I may have found a bug here. Let me debug it properly. Confirmed. I'm sorry for the confusion. The tests regarding ESP32 + SMP without PSRAM failed because the change in https://github.com/apache/nuttx/pull/13249 is valid only when PSRAM is enabled, so we need to make it part of the general case. Can you commit the following to revert it and place it in the correct position: ``` Author: Tiago Medicci Serrano <[email protected]> Date: Fri Aug 30 15:11:59 2024 -0300 esp32: fix initialization with PSRAM + SMP Cache flush must be done prior to the APP cpu initalization. This, however, must be true for the case where PSRAM is not available or not selected. To do that, this commit flushs the cache during the device initialization. diff --git a/arch/xtensa/src/common/espressif/esp_loader.c b/arch/xtensa/src/common/espressif/esp_loader.c index bf21c5f096..ebbf128044 100644 --- a/arch/xtensa/src/common/espressif/esp_loader.c +++ b/arch/xtensa/src/common/espressif/esp_loader.c @@ -273,8 +273,12 @@ int map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr, #endif #ifdef CONFIG_ARCH_CHIP_ESP32 - cache_read_disable(0); - cache_flush(0); + cache_read_disable(PRO_CPU_NUM); + cache_flush(PRO_CPU_NUM); +# ifdef CONFIG_SMP + cache_flush(APP_CPU_NUM); + cache_read_enable(APP_CPU_NUM); +# endif #else cache_hal_disable(CACHE_TYPE_ALL); #endif diff --git a/arch/xtensa/src/esp32/esp32_spiram.c b/arch/xtensa/src/esp32/esp32_spiram.c index eed50e1fff..7eaa5295ec 100644 --- a/arch/xtensa/src/esp32/esp32_spiram.c +++ b/arch/xtensa/src/esp32/esp32_spiram.c @@ -68,13 +68,6 @@ # error "FLASH speed can only be equal to or higher than SRAM speed while SRAM is enabled!" #endif -/**************************************************************************** - * ROM Function Prototypes - ****************************************************************************/ - -extern void cache_flush(int cpu); -extern void cache_read_enable(int cpu); - /**************************************************************************** * Private Data ****************************************************************************/ @@ -253,8 +246,6 @@ void IRAM_ATTR esp_spiram_init_cache(void) /* Flush and enable icache for APP CPU */ #ifdef CONFIG_SMP - cache_flush(APP_CPU_NUM); - cache_read_enable(APP_CPU_NUM); regval = getreg32(DPORT_APP_CACHE_CTRL1_REG); regval &= ~(1 << DPORT_APP_CACHE_MASK_DRAM1); putreg32(regval, DPORT_APP_CACHE_CTRL1_REG); ``` -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
