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commit 6df9de8788be01fa98fcbf9e43026109deb76fbc Author: Tiago Medicci Serrano <[email protected]> AuthorDate: Sat Aug 31 12:46:26 2024 +0900 esp32: fix initialization with PSRAM + SMP Cache flush must be done prior to the APP cpu initalization. This, however, must be true for the case where PSRAM is not available or not selected. To do that, this commit flushs the cache during the device initialization. --- arch/xtensa/src/common/espressif/esp_loader.c | 8 ++++++-- arch/xtensa/src/esp32/esp32_spiram.c | 9 --------- 2 files changed, 6 insertions(+), 11 deletions(-) diff --git a/arch/xtensa/src/common/espressif/esp_loader.c b/arch/xtensa/src/common/espressif/esp_loader.c index bf21c5f096..ebbf128044 100644 --- a/arch/xtensa/src/common/espressif/esp_loader.c +++ b/arch/xtensa/src/common/espressif/esp_loader.c @@ -273,8 +273,12 @@ int map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr, #endif #ifdef CONFIG_ARCH_CHIP_ESP32 - cache_read_disable(0); - cache_flush(0); + cache_read_disable(PRO_CPU_NUM); + cache_flush(PRO_CPU_NUM); +# ifdef CONFIG_SMP + cache_flush(APP_CPU_NUM); + cache_read_enable(APP_CPU_NUM); +# endif #else cache_hal_disable(CACHE_TYPE_ALL); #endif diff --git a/arch/xtensa/src/esp32/esp32_spiram.c b/arch/xtensa/src/esp32/esp32_spiram.c index eed50e1fff..7eaa5295ec 100644 --- a/arch/xtensa/src/esp32/esp32_spiram.c +++ b/arch/xtensa/src/esp32/esp32_spiram.c @@ -68,13 +68,6 @@ # error "FLASH speed can only be equal to or higher than SRAM speed while SRAM is enabled!" #endif -/**************************************************************************** - * ROM Function Prototypes - ****************************************************************************/ - -extern void cache_flush(int cpu); -extern void cache_read_enable(int cpu); - /**************************************************************************** * Private Data ****************************************************************************/ @@ -253,8 +246,6 @@ void IRAM_ATTR esp_spiram_init_cache(void) /* Flush and enable icache for APP CPU */ #ifdef CONFIG_SMP - cache_flush(APP_CPU_NUM); - cache_read_enable(APP_CPU_NUM); regval = getreg32(DPORT_APP_CACHE_CTRL1_REG); regval &= ~(1 << DPORT_APP_CACHE_MASK_DRAM1); putreg32(regval, DPORT_APP_CACHE_CTRL1_REG);
