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commit 064415a765c17a6d14b502cb9da9676ab12de9b5 Author: ligd <[email protected]> AuthorDate: Fri Aug 9 22:33:40 2024 +0800 armv6m: add up_trigger_irq() support Signed-off-by: ligd <[email protected]> --- arch/arm/Kconfig | 1 + arch/arm/src/armv6-m/CMakeLists.txt | 1 + arch/arm/src/armv6-m/Make.defs | 1 + arch/arm/src/armv6-m/arm_trigger_irq.c | 87 ++++++++++++++++++++++++++++++++++ arch/arm/src/armv6-m/nvic.h | 25 ++++++++++ 5 files changed, 115 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 192edc4bb5..4e4d50131c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -817,6 +817,7 @@ config ARCH_CORTEXM0 select ARM_THUMB select ARCH_ARMV6M select ARCH_HAVE_IRQPRIO + select ARCH_HAVE_IRQTRIGGER select ARCH_HAVE_RAMVECTORS select ARCH_HAVE_RESET select ARCH_HAVE_HARDFAULT_DEBUG diff --git a/arch/arm/src/armv6-m/CMakeLists.txt b/arch/arm/src/armv6-m/CMakeLists.txt index deffc19040..6bfb544929 100644 --- a/arch/arm/src/armv6-m/CMakeLists.txt +++ b/arch/arm/src/armv6-m/CMakeLists.txt @@ -29,6 +29,7 @@ set(SRCS arm_svcall.c arm_systemreset.c arm_tcbinfo.c + arm_trigger_irq.c arm_vectors.c) if(CONFIG_DEBUG_FEATURES) diff --git a/arch/arm/src/armv6-m/Make.defs b/arch/arm/src/armv6-m/Make.defs index 669a586cef..9a39ab04bf 100644 --- a/arch/arm/src/armv6-m/Make.defs +++ b/arch/arm/src/armv6-m/Make.defs @@ -27,6 +27,7 @@ CMN_ASRCS += arm_exception.S arm_saveusercontext.S CMN_CSRCS += arm_cpuinfo.c arm_doirq.c arm_hardfault.c arm_initialstate.c CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_svcall.c CMN_CSRCS += arm_systemreset.c arm_tcbinfo.c arm_vectors.c +CMN_CSRCS += arm_trigger_irq.c ifeq ($(CONFIG_DEBUG_FEATURES),y) CMN_CSRCS += arm_dumpnvic.c diff --git a/arch/arm/src/armv6-m/arm_trigger_irq.c b/arch/arm/src/armv6-m/arm_trigger_irq.c new file mode 100644 index 0000000000..397a18705d --- /dev/null +++ b/arch/arm/src/armv6-m/arm_trigger_irq.c @@ -0,0 +1,87 @@ +/**************************************************************************** + * arch/arm/src/armv6-m/arm_trigger_irq.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <assert.h> + +#include <nuttx/arch.h> +#include <arch/irq.h> + +#include "arm_internal.h" +#include "nvic.h" + +#ifdef CONFIG_ARCH_HAVE_IRQTRIGGER + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_trigger_irq + * + * Description: + * Trigger an IRQ by software. + * + ****************************************************************************/ + +void up_trigger_irq(int irq, cpu_set_t cpuset) +{ + uint32_t pend_bit = 0; + + DEBUGASSERT(irq >= NVIC_IRQ_NMI && irq < NR_IRQS); + + if (irq >= NVIC_IRQ_FIRST) + { + putreg32(irq - NVIC_IRQ_FIRST, ARMV6M_NVIC2_BASE); + } + else + { + switch (irq) + { + case NVIC_IRQ_PENDSV: + pend_bit = SYSCON_ICSR_PENDSVSET; + break; + + case NVIC_IRQ_NMI: + pend_bit = SYSCON_ICSR_NMIPENDSET; + break; + + case NVIC_IRQ_SYSTICK: + pend_bit = SYSCON_ICSR_PENDSTSET; + break; + + default: + break; + } + + if (pend_bit) + { + modifyreg32(ARMV6M_SYSCON_ICSR, 0, pend_bit); + } + } +} + +#endif /* CONFIG_ARCH_HAVE_IRQTRIGGER */ diff --git a/arch/arm/src/armv6-m/nvic.h b/arch/arm/src/armv6-m/nvic.h index 62be901b69..3296006884 100644 --- a/arch/arm/src/armv6-m/nvic.h +++ b/arch/arm/src/armv6-m/nvic.h @@ -32,6 +32,31 @@ * Pre-processor Definitions ****************************************************************************/ +/* Exception/interrupt vector numbers ***************************************/ + + /* Vector 0: Reset stack + * pointer value + */ + + /* Vector 1: Reset */ +#define NVIC_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define NVIC_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define NVIC_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define NVIC_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define NVIC_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ + /* Vectors 7-10: Reserved */ +#define NVIC_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define NVIC_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define NVIC_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define NVIC_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16). + * These definitions are chip-specific + */ + +#define NVIC_IRQ_FIRST (16) /* Vector number of the first interrupt */ + /* Base addresses ***********************************************************/ #define ARMV6M_SYSCON1_BASE 0xe000e008 /* 0xe000e008-0xe000e00f System Control Block */
