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new 51171d66f2 riscv/riscv_ipi.h: Do not write to CSR_MIP.MSIP as it is
read-only
51171d66f2 is described below
commit 51171d66f28b73a28a6edfe51fbc814f58b49c49
Author: Ville Juven <[email protected]>
AuthorDate: Wed Nov 27 13:00:07 2024 +0200
riscv/riscv_ipi.h: Do not write to CSR_MIP.MSIP as it is read-only
From the RISV-V Privileged Spec v1.10 (3.1.14 MIP/MIE):
Only the bits corresponding to lower-privilege software interrupts
(USIP, SSIP), timer interrupts (UTIP, STIP), and external interrupts
(UEIP, SEIP) in mip are writable through this CSR address; the
remaining bits are read-only.
Thus, it is futile to write to the M-mode status bit via the CSR, only
access via RISCV_IPI is valid.
---
arch/risc-v/src/common/riscv_ipi.h | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/risc-v/src/common/riscv_ipi.h
b/arch/risc-v/src/common/riscv_ipi.h
index 9f61e58798..666aa546d1 100644
--- a/arch/risc-v/src/common/riscv_ipi.h
+++ b/arch/risc-v/src/common/riscv_ipi.h
@@ -46,10 +46,13 @@ static inline void riscv_ipi_send(int cpu)
static inline void riscv_ipi_clear(int cpu)
{
-#if defined(RISCV_IPI) && !defined(CONFIG_ARCH_USE_S_MODE)
+#if defined(CONFIG_ARCH_USE_S_MODE)
+ CLEAR_CSR(CSR_IP, IP_SIP);
+#elif defined(RISCV_IPI)
putreg32(0, (uintptr_t)RISCV_IPI + (4 * riscv_cpuid_to_hartid(cpu)));
+#else
+# error "No IPI support for this SoC"
#endif
- CLEAR_CSR(CSR_IP, IP_SIP);
}
#endif /* __ARCH_RISCV_SRC_COMMON_RISCV_IPI_H */
