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xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
The following commit(s) were added to refs/heads/master by this push:
new 0476895c0d fix nxstyle
0476895c0d is described below
commit 0476895c0d523becdf5973c8f59fe0e280bb276b
Author: simbit18 <[email protected]>
AuthorDate: Wed Nov 27 12:25:54 2024 +0100
fix nxstyle
Remove TABs
---
arch/arm/src/csk6/csk6_lowputc.c | 6 ++---
arch/arm/src/stm32/stm32g4xxx_flash.c | 4 +--
arch/arm64/src/imx9/hardware/imx9_trdc.h | 16 ++++++------
arch/arm64/src/imx9/imx9_trdc.c | 2 +-
arch/arm64/src/zynq-mpsoc/zynq_serial.c | 38 ++++++++++++++---------------
arch/risc-v/src/bl808/hardware/bl808_m0ic.h | 6 ++---
6 files changed, 36 insertions(+), 36 deletions(-)
diff --git a/arch/arm/src/csk6/csk6_lowputc.c b/arch/arm/src/csk6/csk6_lowputc.c
index 0766c0c2e1..290d66e957 100644
--- a/arch/arm/src/csk6/csk6_lowputc.c
+++ b/arch/arm/src/csk6/csk6_lowputc.c
@@ -36,10 +36,10 @@
* Pre-processor Definitions
****************************************************************************/
-#define CSK6_IOMUX_BASE 0x46200000 // size=1MB
-#define CSK6_SYSCTRL_BASE 0x46000000 // size=64KB
+#define CSK6_IOMUX_BASE 0x46200000 // size=1MB
+#define CSK6_SYSCTRL_BASE 0x46000000 // size=64KB
#define CSK6_SYSPLL_CTRL_BASE 0x46020000 // size=64KB
-#define CSK6_UART0_BASE 0x45000000 // size=1MB
+#define CSK6_UART0_BASE 0x45000000 // size=1MB
#define CSK6011A_NANO_BOARD_H_XTAL_SRC_FREQ 24000000UL
#define CSK6011A_NANO_BOARD_L_XTAL_SRC_FREQ 32768UL
diff --git a/arch/arm/src/stm32/stm32g4xxx_flash.c
b/arch/arm/src/stm32/stm32g4xxx_flash.c
index bb0d3681df..f47bd9c8ae 100644
--- a/arch/arm/src/stm32/stm32g4xxx_flash.c
+++ b/arch/arm/src/stm32/stm32g4xxx_flash.c
@@ -119,7 +119,7 @@ static uint32_t get_flash_page_size(void)
}
#else
return STM32_FLASH_PAGESIZE;
-#endif
+#endif
}
static uint32_t get_flash_npages(void)
@@ -135,7 +135,7 @@ static uint32_t get_flash_npages(void)
}
#else
return STM32_FLASH_NPAGES;
-#endif
+#endif
}
static void flash_unlock(void)
diff --git a/arch/arm64/src/imx9/hardware/imx9_trdc.h
b/arch/arm64/src/imx9/hardware/imx9_trdc.h
index 8a5d074354..ba5e6ab507 100644
--- a/arch/arm64/src/imx9/hardware/imx9_trdc.h
+++ b/arch/arm64/src/imx9/hardware/imx9_trdc.h
@@ -43,7 +43,7 @@
#define AHAB_CMD_TAG 0x17
#define AHAB_RESP_TAG 0xe1
#define ELE_RELEASE_RDC_REQ 0xc4
-#define ELE_READ_FUSE_REQ 0x97
+#define ELE_READ_FUSE_REQ 0x97
#define ELE_OK 0xd6
#define FSB_BASE 0x47510000UL
@@ -51,15 +51,15 @@
#define BLK_CTRL_NS_ANOMIX_BASE IMX9_BLK_CTRL_NS_AONMIX1_BASE
-#define ELE_MU_TCR (IMX9_S3MUA_BASE+ 0x120)
-#define ELE_MU_TSR (IMX9_S3MUA_BASE+ 0x124)
-#define ELE_MU_RCR (IMX9_S3MUA_BASE+ 0x128)
-#define ELE_MU_RSR (IMX9_S3MUA_BASE+ 0x12c)
+#define ELE_MU_TCR (IMX9_S3MUA_BASE+ 0x120)
+#define ELE_MU_TSR (IMX9_S3MUA_BASE+ 0x124)
+#define ELE_MU_RCR (IMX9_S3MUA_BASE+ 0x128)
+#define ELE_MU_RSR (IMX9_S3MUA_BASE+ 0x12c)
#define ELE_RR_NUM 4
#define ELE_TR_NUM 8
-#define ELE_MU_TR(i) (IMX9_S3MUA_BASE + 0x200 + (i) * 4)
-#define ELE_MU_RR(i) (IMX9_S3MUA_BASE + 0x280 + (i) * 4)
+#define ELE_MU_TR(i) (IMX9_S3MUA_BASE + 0x200 + (i) * 4)
+#define ELE_MU_RR(i) (IMX9_S3MUA_BASE + 0x280 + (i) * 4)
#define DID_NUM 16
#define MBC_MAX_NUM 4
@@ -70,7 +70,7 @@
#define MBC_BLK_NUM(GLBCFG) (GLBCFG & 0x3FF)
#define MRC_RGN_NUM(GLBCFG) (GLBCFG & 0x1F)
-#define GLBAC_SETTING_MASK (0x7777)
+#define GLBAC_SETTING_MASK (0x7777)
#define GLBAC_LOCK_MASK BIT(31)
struct ele_header_t
diff --git a/arch/arm64/src/imx9/imx9_trdc.c b/arch/arm64/src/imx9/imx9_trdc.c
index fbd8483b99..34d43b7c9b 100644
--- a/arch/arm64/src/imx9/imx9_trdc.c
+++ b/arch/arm64/src/imx9/imx9_trdc.c
@@ -42,7 +42,7 @@
* Pre-processor Definitions
****************************************************************************/
-#define mmio_read_32(c) getreg32(c)
+#define mmio_read_32(c) getreg32(c)
#define mmio_write_32(c, v) putreg32(v, c)
#define mmio_clrbits_32(addr, clear) modifyreg32(addr, clear, 0)
#define mmio_setbits_32(addr, set) modifyreg32(addr, 0, set)
diff --git a/arch/arm64/src/zynq-mpsoc/zynq_serial.c
b/arch/arm64/src/zynq-mpsoc/zynq_serial.c
index d5abc5c11a..792637b66c 100644
--- a/arch/arm64/src/zynq-mpsoc/zynq_serial.c
+++ b/arch/arm64/src/zynq-mpsoc/zynq_serial.c
@@ -124,7 +124,7 @@
***************************************************************************/
#define XUARTPS_CR_STOPBRK 0x00000100U /* Stop transmission of break */
-#define XUARTPS_CR_STARTBRK 0x00000080U /* Set break */
+#define XUARTPS_CR_STARTBRK 0x00000080U /* Set break */
#define XUARTPS_CR_TORST 0x00000040U /* RX timeout counter restart */
#define XUARTPS_CR_TX_DIS 0x00000020U /* TX disabled. */
#define XUARTPS_CR_TX_EN 0x00000010U /* TX enabled */
@@ -235,8 +235,8 @@
*
***************************************************************************/
-#define XUARTPS_BAUDDIV_MASK 0x000000FFU /* 8 bit baud divider
mask */
-#define XUARTPS_BAUDDIV_RESET_VAL 0x0000000FU /* Reset value */
+#define XUARTPS_BAUDDIV_MASK 0x000000FFU /* 8 bit baud divider mask */
+#define XUARTPS_BAUDDIV_RESET_VAL 0x0000000FU /* Reset value */
/***************************************************************************
* The following constant defines the amount of error that is allowed for
@@ -298,9 +298,9 @@
*
***************************************************************************/
-#define XUARTPS_MODEMCR_FCM 0x00000020U /* Flow control mode */
-#define XUARTPS_MODEMCR_RTS 0x00000002U /* Request to send */
-#define XUARTPS_MODEMCR_DTR 0x00000001U /* Data terminal ready */
+#define XUARTPS_MODEMCR_FCM 0x00000020U /* Flow control mode */
+#define XUARTPS_MODEMCR_RTS 0x00000002U /* Request to send */
+#define XUARTPS_MODEMCR_DTR 0x00000001U /* Data terminal ready */
/***************************************************************************
* Modem Status Register
@@ -361,7 +361,7 @@
*
***************************************************************************/
-#define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /* Valid bit mask */
+#define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /* Valid bit mask */
/***************************************************************************
* Receiver FIFO Byte Status Register
@@ -376,18 +376,18 @@
***************************************************************************/
#define XUARTPS_RXBS_BYTE3_BRKE 0x00000800U /* Byte3 Break Error */
-#define XUARTPS_RXBS_BYTE3_FRME 0x00000400U /* Byte3 Frame Error */
-#define XUARTPS_RXBS_BYTE3_PARE 0x00000200U /* Byte3 Parity Error */
-#define XUARTPS_RXBS_BYTE2_BRKE 0x00000100U /* Byte2 Break Error */
-#define XUARTPS_RXBS_BYTE2_FRME 0x00000080U /* Byte2 Frame Error */
-#define XUARTPS_RXBS_BYTE2_PARE 0x00000040U /* Byte2 Parity Error */
-#define XUARTPS_RXBS_BYTE1_BRKE 0x00000020U /* Byte1 Break Error */
-#define XUARTPS_RXBS_BYTE1_FRME 0x00000010U /* Byte1 Frame Error */
-#define XUARTPS_RXBS_BYTE1_PARE 0x00000008U /* Byte1 Parity Error */
-#define XUARTPS_RXBS_BYTE0_BRKE 0x00000004U /* Byte0 Break Error */
-#define XUARTPS_RXBS_BYTE0_FRME 0x00000002U /* Byte0 Frame Error */
-#define XUARTPS_RXBS_BYTE0_PARE 0x00000001U /* Byte0 Parity Error */
-#define XUARTPS_RXBS_MASK 0x00000007U /* 3 bit RX byte status mask
*/
+#define XUARTPS_RXBS_BYTE3_FRME 0x00000400U /* Byte3 Frame Error */
+#define XUARTPS_RXBS_BYTE3_PARE 0x00000200U /* Byte3 Parity Error */
+#define XUARTPS_RXBS_BYTE2_BRKE 0x00000100U /* Byte2 Break Error */
+#define XUARTPS_RXBS_BYTE2_FRME 0x00000080U /* Byte2 Frame Error */
+#define XUARTPS_RXBS_BYTE2_PARE 0x00000040U /* Byte2 Parity Error */
+#define XUARTPS_RXBS_BYTE1_BRKE 0x00000020U /* Byte1 Break Error */
+#define XUARTPS_RXBS_BYTE1_FRME 0x00000010U /* Byte1 Frame Error */
+#define XUARTPS_RXBS_BYTE1_PARE 0x00000008U /* Byte1 Parity Error */
+#define XUARTPS_RXBS_BYTE0_BRKE 0x00000004U /* Byte0 Break Error */
+#define XUARTPS_RXBS_BYTE0_FRME 0x00000002U /* Byte0 Frame Error */
+#define XUARTPS_RXBS_BYTE0_PARE 0x00000001U /* Byte0 Parity Error */
+#define XUARTPS_RXBS_MASK 0x00000007U /* 3 bit RX byte status mask */
/***************************************************************************
* Private Types
diff --git a/arch/risc-v/src/bl808/hardware/bl808_m0ic.h
b/arch/risc-v/src/bl808/hardware/bl808_m0ic.h
index 0276f2c563..30d5cfce64 100644
--- a/arch/risc-v/src/bl808/hardware/bl808_m0ic.h
+++ b/arch/risc-v/src/bl808/hardware/bl808_m0ic.h
@@ -34,9 +34,9 @@
/* Register offsets */
-#define BL808_M0IC_STATUS_OFFSET(n) (0x00 + 4 * (n))
-#define BL808_M0IC_MASK_OFFSET(n) (0x08 + 4 * (n))
-#define BL808_M0IC_CLEAR_OFFSET(n) (0x10 + 4 * (n))
+#define BL808_M0IC_STATUS_OFFSET(n) (0x00 + 4 * (n))
+#define BL808_M0IC_MASK_OFFSET(n) (0x08 + 4 * (n))
+#define BL808_M0IC_CLEAR_OFFSET(n) (0x10 + 4 * (n))
/* Register locations */
