chirping78 commented on PR #14672:
URL: https://github.com/apache/nuttx/pull/14672#issuecomment-2553126081

   @tmedicci 
   As you can see in this PR, each time when enter level1 interrupt/exception, 
and after `_xtensa_context_save`,
   I added this assemble snippet:
   ```
   +       /* Overwrite the PS saved by the exception entry. */
   +
   +       movi    a2, ~PS_EXCM_MASK
   +       l32i    a3, sp, (4 * REG_PS)
   +       and     a3, a3, a2
   +       s32i    a3, sp, (4 * REG_PS)
   +
   ```
   Before leave from level1 interrupt/exception, and before 
`_xtensa_context_restore`,
   the following snippet is added:
   ```
   +       /* Set PS.EXCM to 1 */
   +
   +       movi    a3, PS_EXCM_MASK
   +       l32i    a4, a2, (4 * REG_PS)
   +       or      a4, a3, a4
   +       s32i    a4, a2, (4 * REG_PS)
   +
   ```
   
   
   Here is the explaination of why these two snippets are added.
   
   As been defined by Xtensa Architecture, the level1 interrupt is different 
from other interrupt levels:
   
   1. the level1 interrupt has no it's own `EPS_X` register to save `PS`. 
   There are only `EPS2..7` for interrupt above level1. This means the `REG_PS` 
saved in the task stack is not `PS` value before interrupt.
   
   2. the instruction to return from level1 interrupt is `RFE`, while `RFI` for 
other interrupt levels.
   `RFE` sets `PS.EXCM` back to 0, while `RFI` restores the `PS` from `EPS_X`.
   
   Taking into consideration the above two facts, the level1 interrupt needs 
special handling:
   - after `_xtensa_context_save`, `EXCM` bit needs be cleard from `REG_PS`, 
since we don't know the interruptee task will be resumed by `RFE` or `RFI`
   - before `_xtensa_context_restore`, `EXCM` bit needs be set to `REG_PS`, or 
there will be risky to interrupt nested in `exception_exit`/`ps_excp_write`
   
   Actually I found these points during the evolution of this PR. You can see 
from the test history there are many asserts and panics in the history version.
   You can try to remove these two snippets, then you will meet the errors that 
 I have met.


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