chirping78 commented on PR #15985: URL: https://github.com/apache/nuttx/pull/15985#issuecomment-2731529034
@sdc-g , to be more elaborate, Take into consideration the task being interrupted and resumed, there are four combination scenarios: two symmetric scenarios: 1. task being interrupted by level1 int, and resumed by level1 int; 2. task being interrupted by level2+ int, and resumed by level2+ int; and two asymmetric scenarios: 3. task being interrupted by level1 int, and resumed by level2+ int; 4. task being interrupted by level2+ int, and resumed by level1 int; For new task creation, since we are pretended the task is being interrupted, and resume it later, it's just a special one of above scenarios. Before the current PR change, in new task‘s register save area, REG_PS's `EXCM` bit is clear. This means it looks like scenario 2 or 4. My changes in PR [14672](https://github.com/apache/nuttx/pull/14672) have done special handling to achieve the balence: level 1 enter, clear REG_PS's `EXCM` bit; level 1 leave, set REG_PS's `EXCM` bit before `rfe`. With the current PR change, in new task‘s register save area, REG_PS's `EXCM` bit is set. This means it looks like scenario 1 or 3. But the new task missed what have been done for hardware interrupt, clear REG_PS's `EXCM` bit. This means it breaks the balence, this is why I said error will arise in scenario 3. -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: commits-unsubscr...@nuttx.apache.org For queries about this service, please contact Infrastructure at: us...@infra.apache.org
