xiaoxiang781216 commented on code in PR #16500:
URL: https://github.com/apache/nuttx/pull/16500#discussion_r2136767948
##########
arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h:
##########
@@ -210,7 +243,11 @@
#define ADC_SMPR_SMP2_SHIFT (4) /* Bits 4-6: Sampling time
selection 2 */
#define ADC_SMPR_SMP2_MASK (7 << ADC_SMPR_SMP_SHIFT)
#define ADC_SMPR_SMPSEL_SHIFT (8) /* Bits 8-26: channel-x sampling
time selection */
-#define ADC_SMPR_SMPSEL(ch, smp) (smp << ADC_SMPR_SMPSEL_SHIFT)
+#if defined(CONFIG_ARCH_CHIP_STM32G0)
+# define ADC_SMPR_SMPSEL(ch, smp) ((smp) << (ADC_SMPR_SMPSEL_SHIFT + ch)) /*
ch = [0..18] and smp = 1 or 0 */
+#else
+# define ADC_SMPR_SMPSEL(ch, smp) (smp << ADC_SMPR_SMPSEL_SHIFT)
Review Comment:
```suggestion
# define ADC_SMPR_SMPSEL(ch, smp) (smp << ADC_SMPR_SMPSEL_SHIFT)
```
##########
arch/arm/src/stm32f0l0g0/stm32_adc.c:
##########
@@ -1295,6 +1312,31 @@ static void adc_configure(struct adc_dev_s *dev)
adc_dumpregs(priv);
}
+ #if defined(CONFIG_STM32F0L0G0_ADC_OVERSAMPLE)
+
+/****************************************************************************
+ * Name: adc_oversample
+ ****************************************************************************/
+
+static void adc_oversample(struct adc_dev_s *dev)
+{
+ struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv;
+
+ uint32_t clrbits = ADC_CFGR2_OVSE | ADC_CFGR2_TOVS |
+ ADC_CFGR2_OVSR_MASK | ADC_CFGR2_OVSS_MASK;
+
+ uint32_t setbits = ADC_CFGR2_OVSE |
+ (CONFIG_STM32F0L0G0_ADC_OVSR << ADC_CFGR2_OVSR_SHIFT) |
+ (CONFIG_STM32F0L0G0_ADC_OVSS << ADC_CFGR2_OVSS_SHIFT);
+
+# ifdef CONFIG_STM32F0L0G0_ADC_TOVS
Review Comment:
```suggestion
# ifdef CONFIG_STM32F0L0G0_ADC_TOVS
```
##########
arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h:
##########
@@ -92,12 +92,17 @@
#define STM32_ADC_CFGR2_OFFSET 0x0010 /* ADC configuration register 2 */
#define STM32_ADC_SMPR_OFFSET 0x0014 /* ADC sample time register */
#define STM32_ADC_TR_OFFSET 0x0020 /* ADC watchdog threshold register
*/
+#define STM32_ADC_AWD2TR_OFFSET 0x0024 /* ADC watchdog 2 threshold
register */
#define STM32_ADC_CHSELR_OFFSET 0x0028 /* ADC channel selection register
*/
+#define STM32_ADC_AWD3TR_OFFSET 0x002c /* ADC watchdog 3 threshold
register */
#define STM32_ADC_DR_OFFSET 0x0040 /* ADC regular data register */
+#define STM32_ADC_AWD2CR_OFFSET 0x00a0 /* ADC watchdog 2 control register
*/
+#define STM32_ADC_AWD3CR_OFFSET 0x00a4 /* ADC watchdog 2 control register
*/
+#define STM32_ADC_CALFACT_OFFSET 0x00b4 /* ADC Calibration factor register
*/
/* Master and Slave ADC Common Registers */
-#define STM32_ADC_CCR_OFFSET 0x0008 /* Common control register */
+#define STM32_ADC_CCR_OFFSET 0x0008 /* Common control register */
Review Comment:
let's align the number with other
##########
arch/arm/src/stm32f0l0g0/stm32_adc.c:
##########
@@ -1295,6 +1312,31 @@ static void adc_configure(struct adc_dev_s *dev)
adc_dumpregs(priv);
}
+ #if defined(CONFIG_STM32F0L0G0_ADC_OVERSAMPLE)
+
+/****************************************************************************
+ * Name: adc_oversample
+ ****************************************************************************/
+
+static void adc_oversample(struct adc_dev_s *dev)
+{
+ struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv;
+
+ uint32_t clrbits = ADC_CFGR2_OVSE | ADC_CFGR2_TOVS |
+ ADC_CFGR2_OVSR_MASK | ADC_CFGR2_OVSS_MASK;
+
+ uint32_t setbits = ADC_CFGR2_OVSE |
+ (CONFIG_STM32F0L0G0_ADC_OVSR << ADC_CFGR2_OVSR_SHIFT) |
+ (CONFIG_STM32F0L0G0_ADC_OVSS << ADC_CFGR2_OVSS_SHIFT);
+
+# ifdef CONFIG_STM32F0L0G0_ADC_TOVS
+ setbits |= ADC_CFGR2_TOVS;
+# endif
Review Comment:
need two spaces after #
##########
boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_bringup.c:
##########
@@ -26,14 +26,18 @@
#include <nuttx/config.h>
+#include <sys/mount.h>
#include <sys/types.h>
#include <syslog.h>
+#include <debug.h>
#include <nuttx/board.h>
+#include <nuttx/input/buttons.h>
#include <nuttx/leds/userled.h>
#include "nucleo-g0b1re.h"
+#include <arch/board/board.h>
Review Comment:
move before line 37
##########
arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h:
##########
@@ -108,9 +113,16 @@
#define STM32_ADC1_CFGR2 (STM32_ADC1_BASE + STM32_ADC_CFGR2_OFFSET)
#define STM32_ADC1_SMPR (STM32_ADC1_BASE + STM32_ADC_SMPR_OFFSET)
#define STM32_ADC1_TR (STM32_ADC1_BASE + STM32_ADC_TR_OFFSET)
+#define STM32_ADC1_AWD2TR (STM32_ADC1_BASE + STM32_ADC_AWD2TR_OFFSET)
#define STM32_ADC1_CHSELR (STM32_ADC1_BASE + STM32_ADC_CHSELR_OFFSET)
+#define STM32_ADC1_AWD3TR (STM32_ADC1_BASE + STM32_ADC_AWD3TR_OFFSET)
#define STM32_ADC1_DR (STM32_ADC1_BASE + STM32_ADC_DR_OFFSET)
-#define STM32_ADC1_CCR (STM32_ADC1_BASE + STM32_ADC_CCR_OFFSET)
+#define STM32_ADC1_AWD2CR (STM32_ADC1_BASE + STM32_ADC_AWD2CR_OFFSET)
+#define STM32_ADC1_AWD3CR (STM32_ADC1_BASE + STM32_ADC_AWD3CR_OFFSET)
+#define STM32_ADC1_CALFACT (STM32_ADC1_BASE +
STM32_ADC_CALFACT_OFFSET)
+#if defined(CONFIG_ARCH_CHIP_STM32G0)
+# define STM32_ADC1_CCR (STM32_ADC1_BASE + STM32_ADC_CCR_OFFSET)
Review Comment:
align too
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