raiden00pl commented on code in PR #16500:
URL: https://github.com/apache/nuttx/pull/16500#discussion_r2137149183
##########
arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h:
##########
@@ -108,9 +113,16 @@
#define STM32_ADC1_CFGR2 (STM32_ADC1_BASE + STM32_ADC_CFGR2_OFFSET)
#define STM32_ADC1_SMPR (STM32_ADC1_BASE + STM32_ADC_SMPR_OFFSET)
#define STM32_ADC1_TR (STM32_ADC1_BASE + STM32_ADC_TR_OFFSET)
+#define STM32_ADC1_AWD2TR (STM32_ADC1_BASE + STM32_ADC_AWD2TR_OFFSET)
#define STM32_ADC1_CHSELR (STM32_ADC1_BASE + STM32_ADC_CHSELR_OFFSET)
+#define STM32_ADC1_AWD3TR (STM32_ADC1_BASE + STM32_ADC_AWD3TR_OFFSET)
#define STM32_ADC1_DR (STM32_ADC1_BASE + STM32_ADC_DR_OFFSET)
-#define STM32_ADC1_CCR (STM32_ADC1_BASE + STM32_ADC_CCR_OFFSET)
+#define STM32_ADC1_AWD2CR (STM32_ADC1_BASE + STM32_ADC_AWD2CR_OFFSET)
+#define STM32_ADC1_AWD3CR (STM32_ADC1_BASE + STM32_ADC_AWD3CR_OFFSET)
+#define STM32_ADC1_CALFACT (STM32_ADC1_BASE +
STM32_ADC_CALFACT_OFFSET)
+#if defined(CONFIG_ARCH_CHIP_STM32G0)
+# define STM32_ADC1_CCR (STM32_ADC1_BASE + STM32_ADC_CCR_OFFSET)
Review Comment:
I don't think this is true. Please remove STM32_ADC1_CCR, it's not used
anyway
##########
arch/arm/src/stm32f0l0g0/stm32_adc.c:
##########
@@ -1132,6 +1139,16 @@ static void adc_common_cfg(struct stm32_dev_s *priv)
uint32_t clrbits = 0;
uint32_t setbits = 0;
+#if defined(CONFIG_STM32F0L0G0_STM32G0)
+
+ /* G0 series maps CCR inside ADC1; access directly */
Review Comment:
Remove this comment, its not true. CCR register is at offset 0x300, which is
not ADC1 region (ADC1: 0x000-0x100, ADC2: 0x100-0x200, ADCCMN:0x300).
##########
arch/arm/src/stm32f0l0g0/Kconfig:
##########
@@ -3152,6 +3152,45 @@ config STM32F0L0G0_ADC1_DMA_CFG
---help---
0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode
+config STM32F0L0G0_ADC_OVERSAMPLE
+ bool "Enable ADC hardware oversampling support"
+ depends on STM32F0L0G0_ADC1 && (STM32F0L0G0_STM32L0 || STM32F0L0G0_STM32G0)
Review Comment:
ccan we create hidden Kconfig option like `STM32F0L0G0_HAVE_ADC_OVERSAMPLE`
and select this under `STM32F0L0G0_STM32L0` and `STM32F0L0G0_STM32G0` ?
##########
arch/arm/src/stm32f0l0g0/stm32_adc.c:
##########
@@ -1132,6 +1139,16 @@ static void adc_common_cfg(struct stm32_dev_s *priv)
uint32_t clrbits = 0;
uint32_t setbits = 0;
+#if defined(CONFIG_STM32F0L0G0_STM32G0)
+
+ /* G0 series maps CCR inside ADC1; access directly */
+
+ clrbits |= ADC_CCR_PRESC_MASK | ADC_CCR_VREFEN | \
+ ADC_CCR_TSEN | ADC_CCR_VBATEN;
+ setbits |= ADC_CCR_PRESC_4 | ADC_CCR_VREFEN;
Review Comment:
why hardcode PRESC_4 and always enable VREFEN? Can we select these
automatically like in stm32h7 or stm32h5?
##########
arch/arm/src/stm32f0l0g0/stm32_adc.c:
##########
@@ -2028,6 +2124,14 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd,
unsigned long arg)
break;
}
+#if defined(CONFIG_STM32F0L0G0_STM32G0)
Review Comment:
ifdef CONFIG_STM32F0L0G0_ADC_OVERSAMPLE
##########
arch/arm/src/stm32f0l0g0/stm32_adc.c:
##########
@@ -1392,6 +1434,10 @@ static int adc_setup(struct adc_dev_s *dev)
adc_configure(dev);
+#if defined(CONFIG_STM32F0L0G0_ADC_OVERSAMPLE)
Review Comment:
ifdef
##########
arch/arm/src/stm32f0l0g0/Kconfig:
##########
@@ -3152,6 +3152,45 @@ config STM32F0L0G0_ADC1_DMA_CFG
---help---
0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode
+config STM32F0L0G0_ADC_OVERSAMPLE
+ bool "Enable ADC hardware oversampling support"
+ depends on STM32F0L0G0_ADC1 && (STM32F0L0G0_STM32L0 || STM32F0L0G0_STM32G0)
Review Comment:
STM32C0 also support ADC oversampling
##########
arch/arm/src/stm32f0l0g0/stm32_adc.c:
##########
@@ -1858,6 +1904,55 @@ static int adc_ioc_change_ints(struct adc_dev_s *dev,
int cmd, bool arg)
return ret;
}
+#if defined(CONFIG_STM32F0L0G0_STM32G0) || defined(CONFIG_STM32F0L0G0_STM32L0)
Review Comment:
ifdef CONFIG_STM32F0L0G0_ADC_OVERSAMPLE
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