patacongo commented on a change in pull request #1613:
URL: https://github.com/apache/incubator-nuttx/pull/1613#discussion_r474232745
##########
File path: arch/xtensa/src/esp32/hardware/esp32_soc.h
##########
@@ -371,4 +372,162 @@
/* Other interrupt numbers should be managed by the user */
+#define DR_REG_APB_CTRL_BASE 0x3ff66000 /* Old name for
SYSCON, to be removed */
+#define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x0)
+#define APB_CTRL_XTAL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x4)
+
+/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+
+#define APB_CTRL_PRE_DIV_CNT 0x000003FF
+#define APB_CTRL_PRE_DIV_CNT_M
((APB_CTRL_PRE_DIV_CNT_V)<<(APB_CTRL_PRE_DIV_CNT_S))
+#define APB_CTRL_PRE_DIV_CNT_V 0x3FF
+#define APB_CTRL_PRE_DIV_CNT_S 0
+
+#define I2C_BBPLL_IR_CAL_DELAY 0
+#define I2C_BBPLL_IR_CAL_EXT_CAP 1
+#define I2C_BBPLL_OC_ENB_FCAL 4
+#define I2C_BBPLL_OC_ENB_VCON 10
+#define I2C_BBPLL_BBADC_CAL_7_0 12
+
+#define I2C_BBPLL_OC_LREF 2
+#define I2C_BBPLL_OC_LREF_MSB 7
+#define I2C_BBPLL_OC_LREF_LSB 7
+
+#define I2C_BBPLL_OC_DIV_7_0 3
+#define I2C_BBPLL_OC_DIV_7_0_MSB 7
+#define I2C_BBPLL_OC_DIV_7_0_LSB 0
+
+#define I2C_BBPLL_BBADC_DSMP 9
+#define I2C_BBPLL_BBADC_DSMP_MSB 7
+#define I2C_BBPLL_BBADC_DSMP_LSB 4
+
+#define I2C_BBPLL_OC_DCUR 5
+#define I2C_BBPLL_OC_DCUR_MSB 2
+#define I2C_BBPLL_OC_DCUR_LSB 0
+
+#define I2C_BBPLL_ENDIV5 11
+
+#define I2C_BBPLL 0x66
+#define I2C_BBPLL_HOSTID 4
+
+extern int rom_i2c_writeReg(int block, int block_id, int reg_add,
+ int indata);
+
+#define I2C_WRITEREG_RTC(block, reg_add, indata) \
+ rom_i2c_writeReg(block, block##_HOSTID, reg_add, indata)
+
+/* BBPLL configuration values */
+
+#define BBPLL_ENDIV5_VAL_320M 0x43
+#define BBPLL_BBADC_DSMP_VAL_320M 0x84
+#define BBPLL_ENDIV5_VAL_480M 0xc3
+#define BBPLL_BBADC_DSMP_VAL_480M 0x74
+
+#define BBPLL_IR_CAL_DELAY_VAL 0x18
+#define BBPLL_IR_CAL_EXT_CAP_VAL 0x20
+#define BBPLL_OC_ENB_FCAL_VAL 0x9a
+#define BBPLL_OC_ENB_VCON_VAL 0x00
+#define BBPLL_BBADC_CAL_7_0_VAL 0x00
+
+#define EFUSE_BLK0_RDATA5_REG (DR_REG_EFUSE_BASE + 0x014)
+#define EFUSE_RD_VOL_LEVEL_HP_INV 0x03
+#define EFUSE_RD_VOL_LEVEL_HP_INV_S 22
+
+#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + i*0x1000)
+#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x0068)
+
+#define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0)
+#define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0xb4)
+
+#define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG
+#define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x7c)
+
+#define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x70)
+
+#define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x30)
+
+#define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0xb0)
+#define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG
Review comment:
Please align the above.
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