patacongo commented on a change in pull request #1613:
URL: https://github.com/apache/incubator-nuttx/pull/1613#discussion_r474234390
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File path: arch/xtensa/src/esp32/esp32_clockconfig.c
##########
@@ -52,13 +46,278 @@ enum xtal_freq_e
XTAL_AUTO = 0
};
-enum xtal_freq_e
+enum cpu_freq_e
{
- CPU_80M = 1,
- CPU_160M = 2,
- CPU_240M = 3,
+ CPU_80M = 0,
+ CPU_160M = 1,
+ CPU_240M = 2,
};
-#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+extern void ets_delay_us(int delay_us);
+
+/****************************************************************************
+ * Name: esp32_set_cpu_freq
+ *
+ * Description:
+ * Switch to one of PLL-based frequencies.
+ * Current frequency can be XTAL or PLL.
+ *
+ * Input Parameters:
+ * cpu_freq_mhz - new CPU frequency
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void esp32_set_cpu_freq(int cpu_freq_mhz)
+{
+ int dbias = DIG_DBIAS_80M_160M;
+ int per_conf;
+ uint32_t value;
+
+ switch (cpu_freq_mhz)
+ {
+ case 160:
+ per_conf = CPU_160M;
+ break;
+ case 240:
+ dbias = DIG_DBIAS_240M;
+ per_conf = CPU_240M;
+ break;
+ case 80:
+ per_conf = CPU_80M;
+ default:
+ break;
+ }
+
+ value = (((80 * MHZ) >> 12) & UINT16_MAX)
+ | ((((80 * MHZ) >> 12) & UINT16_MAX) << 16);
+ putreg32(value, RTC_APB_FREQ_REG);
+ putreg32(per_conf, DPORT_CPU_PER_CONF_REG);
+ REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, dbias);
+ REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL,
+ RTC_CNTL_SOC_CLK_SEL_PLL);
+}
+
+/****************************************************************************
+ * Name: esp32_bbpll_configure
+ *
+ * Description:
+ * Configure main XTAL frequency values according to pll_freq.
+ *
+ * Input Parameters:
+ * xtal_freq - XTAL frequency values
+ * pll_freq - PLL frequency values
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void esp32_bbpll_configure(enum xtal_freq_e xtal_freq, int pll_freq)
+{
+ uint8_t div_ref;
+ uint8_t div7_0;
+ uint8_t div10_8;
+ uint8_t lref;
+ uint8_t dcur;
+ uint8_t bw;
+ uint8_t i2c_bbpll_lref;
+ uint8_t i2c_bbpll_div_7_0;
+ uint8_t i2c_bbpll_dcur;
+
+ if (pll_freq == RTC_PLL_FREQ_320M)
+ {
+ /* Raise the voltage, if needed */
+
+ REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK,
+ DIG_DBIAS_80M_160M);
+
+ /* Configure 320M PLL */
+
+ switch (xtal_freq)
+ {
+ case XTAL_40M:
+ div_ref = 0;
+ div7_0 = 32;
+ div10_8 = 0;
+ lref = 0;
+ dcur = 6;
+ bw = 3;
+ break;
+ case XTAL_26M:
Review comment:
Again, typically there is a blank line between break; and case
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