RB-tel commented on a change in pull request #1622:
URL: https://github.com/apache/incubator-nuttx/pull/1622#discussion_r478377814
##########
File path: arch/renesas/src/rx65n/rx65n_definitions.h
##########
@@ -585,6 +592,162 @@
#define RX65N_SBRAM_BASE 0x000a4000
+/* RIIC related definitions */
+
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_DRIVER)
+ #define HAVE_RIIC_DRIVER 1
+#endif
+
+#define RX65N_RIIC0_BASE (uint32_t)&RIIC0
+#define RX65N_RIIC1_BASE (uint32_t)&RIIC1
+#define RX65N_RIIC2_BASE (uint32_t)&RIIC2
+
+#define RX65N_RIIC_ICCR1_OFFSET (0x0000)
+#define RX65N_RIIC_ICCR2_OFFSET (0x0001)
+#define RX65N_RIIC_ICMR1_OFFSET (0x0002)
+#define RX65N_RIIC_ICMR2_OFFSET (0x0003)
+#define RX65N_RIIC_ICMR3_OFFSET (0x0004)
+#define RX65N_RIIC_ICFER_OFFSET (0x0005)
+#define RX65N_RIIC_ICSER_OFFSET (0x0006)
+#define RX65N_RIIC_ICIER_OFFSET (0x0007)
+#define RX65N_RIIC_ICSR1_OFFSET (0x0008)
+#define RX65N_RIIC_ICSR2_OFFSET (0x0009)
+#define RX65N_RIIC_SARL0_OFFSET (0x000a)
+#define RX65N_RIIC_SARU0_OFFSET (0x000b)
+#define RX65N_RIIC_SARL1_OFFSET (0x000c)
+#define RX65N_RIIC_SARU1_OFFSET (0x000d)
+#define RX65N_RIIC_SARL2_OFFSET (0x000e)
+#define RX65N_RIIC_SARU2_OFFSET (0x000f)
+#define RX65N_RIIC_ICBRL_OFFSET (0x0010)
+#define RX65N_RIIC_ICBRH_OFFSET (0x0011)
+#define RX65N_RIIC_ICDRT_OFFSET (0x0012)
+#define RX65N_RIIC_ICDRR_OFFSET (0x0013)
+
+#define RX65N_RIIC0_ICCR1 (RX65N_RIIC0_BASE + RX65N_RIIC_ICCR1_OFFSET)
Review comment:
corrected the alignment
##########
File path: arch/renesas/src/rx65n/rx65n_definitions.h
##########
@@ -585,6 +592,162 @@
#define RX65N_SBRAM_BASE 0x000a4000
+/* RIIC related definitions */
+
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_DRIVER)
+ #define HAVE_RIIC_DRIVER 1
+#endif
+
+#define RX65N_RIIC0_BASE (uint32_t)&RIIC0
+#define RX65N_RIIC1_BASE (uint32_t)&RIIC1
+#define RX65N_RIIC2_BASE (uint32_t)&RIIC2
+
+#define RX65N_RIIC_ICCR1_OFFSET (0x0000)
+#define RX65N_RIIC_ICCR2_OFFSET (0x0001)
+#define RX65N_RIIC_ICMR1_OFFSET (0x0002)
+#define RX65N_RIIC_ICMR2_OFFSET (0x0003)
+#define RX65N_RIIC_ICMR3_OFFSET (0x0004)
+#define RX65N_RIIC_ICFER_OFFSET (0x0005)
+#define RX65N_RIIC_ICSER_OFFSET (0x0006)
+#define RX65N_RIIC_ICIER_OFFSET (0x0007)
+#define RX65N_RIIC_ICSR1_OFFSET (0x0008)
+#define RX65N_RIIC_ICSR2_OFFSET (0x0009)
+#define RX65N_RIIC_SARL0_OFFSET (0x000a)
+#define RX65N_RIIC_SARU0_OFFSET (0x000b)
+#define RX65N_RIIC_SARL1_OFFSET (0x000c)
+#define RX65N_RIIC_SARU1_OFFSET (0x000d)
+#define RX65N_RIIC_SARL2_OFFSET (0x000e)
+#define RX65N_RIIC_SARU2_OFFSET (0x000f)
+#define RX65N_RIIC_ICBRL_OFFSET (0x0010)
+#define RX65N_RIIC_ICBRH_OFFSET (0x0011)
+#define RX65N_RIIC_ICDRT_OFFSET (0x0012)
+#define RX65N_RIIC_ICDRR_OFFSET (0x0013)
+
+#define RX65N_RIIC0_ICCR1 (RX65N_RIIC0_BASE + RX65N_RIIC_ICCR1_OFFSET)
+#define RX65N_RIIC0_ICCR2 (RX65N_RIIC0_BASE + RX65N_RIIC_ICCR2_OFFSET)
+#define RX65N_RIIC0_ICMR1 (RX65N_RIIC0_BASE + RX65N_RIIC_ICMR1_OFFSET)
+#define RX65N_RIIC0_ICMR2 (RX65N_RIIC0_BASE + RX65N_RIIC_ICMR2_OFFSET)
+#define RX65N_RIIC0_ICMR3 (RX65N_RIIC0_BASE + RX65N_RIIC_ICMR3_OFFSET)
+#define RX65N_RIIC0_ICFER (RX65N_RIIC0_BASE + RX65N_RIIC_ICFER_OFFSET)
+#define RX65N_RIIC0_ICSER (RX65N_RIIC0_BASE + RX65N_RIIC_ICSER_OFFSET)
+#define RX65N_RIIC0_ICIER (RX65N_RIIC0_BASE + RX65N_RIIC_ICIER_OFFSET)
+#define RX65N_RIIC0_ICSR1 (RX65N_RIIC0_BASE + RX65N_RIIC_ICSR1_OFFSET)
+#define RX65N_RIIC0_ICSR2 (RX65N_RIIC0_BASE + RX65N_RIIC_ICSR2_OFFSET)
+#define RX65N_RIIC0_SARL0 (RX65N_RIIC0_BASE + RX65N_RIIC_SARL0_OFFSET)
+#define RX65N_RIIC0_SARU0 (RX65N_RIIC0_BASE + RX65N_RIIC_SARU0_OFFSET)
+#define RX65N_RIIC0_SARL1 (RX65N_RIIC0_BASE + RX65N_RIIC_SARL1_OFFSET)
+#define RX65N_RIIC0_SARU1 (RX65N_RIIC0_BASE + RX65N_RIIC_SARU1_OFFSET)
+#define RX65N_RIIC0_SARL2 (RX65N_RIIC0_BASE + RX65N_RIIC_SARL2_OFFSET)
+#define RX65N_RIIC0_SARU2 (RX65N_RIIC0_BASE + RX65N_RIIC_SARU2_OFFSET)
+#define RX65N_RIIC0_ICBRL (RX65N_RIIC0_BASE + RX65N_RIIC_ICBRL_OFFSET)
+#define RX65N_RIIC0_ICBRH (RX65N_RIIC0_BASE + RX65N_RIIC_ICBRH_OFFSET)
+#define RX65N_RIIC0_ICDRT (RX65N_RIIC0_BASE + RX65N_RIIC_ICDRT_OFFSET)
+#define RX65N_RIIC0_ICDRR (RX65N_RIIC0_BASE + RX65N_RIIC_ICDRR_OFFSET)
+
+#define RX65N_RIIC1_ICCR1 (RX65N_RIIC1_BASE + RX65N_RIIC_ICCR1_OFFSET)
+#define RX65N_RIIC1_ICCR2 (RX65N_RIIC1_BASE + RX65N_RIIC_ICCR2_OFFSET)
+#define RX65N_RIIC1_ICMR1 (RX65N_RIIC1_BASE + RX65N_RIIC_ICMR1_OFFSET)
+#define RX65N_RIIC1_ICMR2 (RX65N_RIIC1_BASE + RX65N_RIIC_ICMR2_OFFSET)
+#define RX65N_RIIC1_ICMR3 (RX65N_RIIC1_BASE + RX65N_RIIC_ICMR3_OFFSET)
+#define RX65N_RIIC1_ICFER (RX65N_RIIC1_BASE + RX65N_RIIC_ICFER_OFFSET)
+#define RX65N_RIIC1_ICSER (RX65N_RIIC1_BASE + RX65N_RIIC_ICSER_OFFSET)
+#define RX65N_RIIC1_ICIER (RX65N_RIIC1_BASE + RX65N_RIIC_ICIER_OFFSET)
+#define RX65N_RIIC1_ICSR1 (RX65N_RIIC1_BASE + RX65N_RIIC_ICSR1_OFFSET)
+#define RX65N_RIIC1_ICSR2 (RX65N_RIIC1_BASE + RX65N_RIIC_ICSR2_OFFSET)
+#define RX65N_RIIC1_SARL0 (RX65N_RIIC1_BASE + RX65N_RIIC_SARL0_OFFSET)
+#define RX65N_RIIC1_SARU0 (RX65N_RIIC1_BASE + RX65N_RIIC_SARU0_OFFSET)
+#define RX65N_RIIC1_SARL1 (RX65N_RIIC1_BASE + RX65N_RIIC_SARL1_OFFSET)
+#define RX65N_RIIC1_SARU1 (RX65N_RIIC1_BASE + RX65N_RIIC_SARU1_OFFSET)
+#define RX65N_RIIC1_SARL2 (RX65N_RIIC1_BASE + RX65N_RIIC_SARL2_OFFSET)
+#define RX65N_RIIC1_SARU2 (RX65N_RIIC1_BASE + RX65N_RIIC_SARU2_OFFSET)
+#define RX65N_RIIC1_ICBRL (RX65N_RIIC1_BASE + RX65N_RIIC_ICBRL_OFFSET)
+#define RX65N_RIIC1_ICBRH (RX65N_RIIC1_BASE + RX65N_RIIC_ICBRH_OFFSET)
+#define RX65N_RIIC1_ICDRT (RX65N_RIIC1_BASE + RX65N_RIIC_ICDRT_OFFSET)
+#define RX65N_RIIC1_ICDRR (RX65N_RIIC1_BASE + RX65N_RIIC_ICDRR_OFFSET)
+
+#define RX65N_RIIC2_ICCR1 (RX65N_RIIC2_BASE + RX65N_RIIC_ICCR1_OFFSET)
+#define RX65N_RIIC2_ICCR2 (RX65N_RIIC2_BASE + RX65N_RIIC_ICCR2_OFFSET)
+#define RX65N_RIIC2_ICMR1 (RX65N_RIIC2_BASE + RX65N_RIIC_ICMR1_OFFSET)
+#define RX65N_RIIC2_ICMR2 (RX65N_RIIC2_BASE + RX65N_RIIC_ICMR2_OFFSET)
+#define RX65N_RIIC2_ICMR3 (RX65N_RIIC2_BASE + RX65N_RIIC_ICMR3_OFFSET)
+#define RX65N_RIIC2_ICFER (RX65N_RIIC2_BASE + RX65N_RIIC_ICFER_OFFSET)
+#define RX65N_RIIC2_ICSER (RX65N_RIIC2_BASE + RX65N_RIIC_ICSER_OFFSET)
+#define RX65N_RIIC2_ICIER (RX65N_RIIC2_BASE + RX65N_RIIC_ICIER_OFFSET)
+#define RX65N_RIIC2_ICSR1 (RX65N_RIIC2_BASE + RX65N_RIIC_ICSR1_OFFSET)
+#define RX65N_RIIC2_ICSR2 (RX65N_RIIC2_BASE + RX65N_RIIC_ICSR2_OFFSET)
+#define RX65N_RIIC2_SARL0 (RX65N_RIIC2_BASE + RX65N_RIIC_SARL0_OFFSET)
+#define RX65N_RIIC2_SARU0 (RX65N_RIIC2_BASE + RX65N_RIIC_SARU0_OFFSET)
+#define RX65N_RIIC2_SARL1 (RX65N_RIIC2_BASE + RX65N_RIIC_SARL1_OFFSET)
+#define RX65N_RIIC2_SARU1 (RX65N_RIIC2_BASE + RX65N_RIIC_SARU1_OFFSET)
+#define RX65N_RIIC2_SARL2 (RX65N_RIIC2_BASE + RX65N_RIIC_SARL2_OFFSET)
+#define RX65N_RIIC2_SARU2 (RX65N_RIIC2_BASE + RX65N_RIIC_SARU2_OFFSET)
+#define RX65N_RIIC2_ICBRL (RX65N_RIIC2_BASE + RX65N_RIIC_ICBRL_OFFSET)
+#define RX65N_RIIC2_ICBRH (RX65N_RIIC2_BASE + RX65N_RIIC_ICBRH_OFFSET)
+#define RX65N_RIIC2_ICDRT (RX65N_RIIC2_BASE + RX65N_RIIC_ICDRT_OFFSET)
+#define RX65N_RIIC2_ICDRR (RX65N_RIIC2_BASE + RX65N_RIIC_ICDRR_OFFSET)
+
+#define RX65N_RIIC_ICCR1_ICE_RST (0x7f)
+#define RX65N_RIIC_ICCR1_IICRST_SET (0x40)
+
+#define RX65N_RIIC_ICCR2_ST_SET (0x02)
+#define RX65N_RIIC_ICCR2_SP_SET (0x08)
Review comment:
corrected the alignment
##########
File path: arch/renesas/src/rx65n/rx65n_definitions.h
##########
@@ -585,6 +592,162 @@
#define RX65N_SBRAM_BASE 0x000a4000
+/* RIIC related definitions */
+
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_DRIVER)
+ #define HAVE_RIIC_DRIVER 1
+#endif
+
+#define RX65N_RIIC0_BASE (uint32_t)&RIIC0
+#define RX65N_RIIC1_BASE (uint32_t)&RIIC1
+#define RX65N_RIIC2_BASE (uint32_t)&RIIC2
+
+#define RX65N_RIIC_ICCR1_OFFSET (0x0000)
+#define RX65N_RIIC_ICCR2_OFFSET (0x0001)
+#define RX65N_RIIC_ICMR1_OFFSET (0x0002)
+#define RX65N_RIIC_ICMR2_OFFSET (0x0003)
+#define RX65N_RIIC_ICMR3_OFFSET (0x0004)
+#define RX65N_RIIC_ICFER_OFFSET (0x0005)
+#define RX65N_RIIC_ICSER_OFFSET (0x0006)
+#define RX65N_RIIC_ICIER_OFFSET (0x0007)
+#define RX65N_RIIC_ICSR1_OFFSET (0x0008)
+#define RX65N_RIIC_ICSR2_OFFSET (0x0009)
+#define RX65N_RIIC_SARL0_OFFSET (0x000a)
+#define RX65N_RIIC_SARU0_OFFSET (0x000b)
+#define RX65N_RIIC_SARL1_OFFSET (0x000c)
+#define RX65N_RIIC_SARU1_OFFSET (0x000d)
+#define RX65N_RIIC_SARL2_OFFSET (0x000e)
+#define RX65N_RIIC_SARU2_OFFSET (0x000f)
+#define RX65N_RIIC_ICBRL_OFFSET (0x0010)
+#define RX65N_RIIC_ICBRH_OFFSET (0x0011)
+#define RX65N_RIIC_ICDRT_OFFSET (0x0012)
+#define RX65N_RIIC_ICDRR_OFFSET (0x0013)
+
+#define RX65N_RIIC0_ICCR1 (RX65N_RIIC0_BASE + RX65N_RIIC_ICCR1_OFFSET)
+#define RX65N_RIIC0_ICCR2 (RX65N_RIIC0_BASE + RX65N_RIIC_ICCR2_OFFSET)
+#define RX65N_RIIC0_ICMR1 (RX65N_RIIC0_BASE + RX65N_RIIC_ICMR1_OFFSET)
+#define RX65N_RIIC0_ICMR2 (RX65N_RIIC0_BASE + RX65N_RIIC_ICMR2_OFFSET)
+#define RX65N_RIIC0_ICMR3 (RX65N_RIIC0_BASE + RX65N_RIIC_ICMR3_OFFSET)
+#define RX65N_RIIC0_ICFER (RX65N_RIIC0_BASE + RX65N_RIIC_ICFER_OFFSET)
+#define RX65N_RIIC0_ICSER (RX65N_RIIC0_BASE + RX65N_RIIC_ICSER_OFFSET)
+#define RX65N_RIIC0_ICIER (RX65N_RIIC0_BASE + RX65N_RIIC_ICIER_OFFSET)
+#define RX65N_RIIC0_ICSR1 (RX65N_RIIC0_BASE + RX65N_RIIC_ICSR1_OFFSET)
+#define RX65N_RIIC0_ICSR2 (RX65N_RIIC0_BASE + RX65N_RIIC_ICSR2_OFFSET)
+#define RX65N_RIIC0_SARL0 (RX65N_RIIC0_BASE + RX65N_RIIC_SARL0_OFFSET)
+#define RX65N_RIIC0_SARU0 (RX65N_RIIC0_BASE + RX65N_RIIC_SARU0_OFFSET)
+#define RX65N_RIIC0_SARL1 (RX65N_RIIC0_BASE + RX65N_RIIC_SARL1_OFFSET)
+#define RX65N_RIIC0_SARU1 (RX65N_RIIC0_BASE + RX65N_RIIC_SARU1_OFFSET)
+#define RX65N_RIIC0_SARL2 (RX65N_RIIC0_BASE + RX65N_RIIC_SARL2_OFFSET)
+#define RX65N_RIIC0_SARU2 (RX65N_RIIC0_BASE + RX65N_RIIC_SARU2_OFFSET)
+#define RX65N_RIIC0_ICBRL (RX65N_RIIC0_BASE + RX65N_RIIC_ICBRL_OFFSET)
+#define RX65N_RIIC0_ICBRH (RX65N_RIIC0_BASE + RX65N_RIIC_ICBRH_OFFSET)
+#define RX65N_RIIC0_ICDRT (RX65N_RIIC0_BASE + RX65N_RIIC_ICDRT_OFFSET)
+#define RX65N_RIIC0_ICDRR (RX65N_RIIC0_BASE + RX65N_RIIC_ICDRR_OFFSET)
+
+#define RX65N_RIIC1_ICCR1 (RX65N_RIIC1_BASE + RX65N_RIIC_ICCR1_OFFSET)
+#define RX65N_RIIC1_ICCR2 (RX65N_RIIC1_BASE + RX65N_RIIC_ICCR2_OFFSET)
+#define RX65N_RIIC1_ICMR1 (RX65N_RIIC1_BASE + RX65N_RIIC_ICMR1_OFFSET)
+#define RX65N_RIIC1_ICMR2 (RX65N_RIIC1_BASE + RX65N_RIIC_ICMR2_OFFSET)
+#define RX65N_RIIC1_ICMR3 (RX65N_RIIC1_BASE + RX65N_RIIC_ICMR3_OFFSET)
+#define RX65N_RIIC1_ICFER (RX65N_RIIC1_BASE + RX65N_RIIC_ICFER_OFFSET)
+#define RX65N_RIIC1_ICSER (RX65N_RIIC1_BASE + RX65N_RIIC_ICSER_OFFSET)
+#define RX65N_RIIC1_ICIER (RX65N_RIIC1_BASE + RX65N_RIIC_ICIER_OFFSET)
+#define RX65N_RIIC1_ICSR1 (RX65N_RIIC1_BASE + RX65N_RIIC_ICSR1_OFFSET)
+#define RX65N_RIIC1_ICSR2 (RX65N_RIIC1_BASE + RX65N_RIIC_ICSR2_OFFSET)
+#define RX65N_RIIC1_SARL0 (RX65N_RIIC1_BASE + RX65N_RIIC_SARL0_OFFSET)
+#define RX65N_RIIC1_SARU0 (RX65N_RIIC1_BASE + RX65N_RIIC_SARU0_OFFSET)
+#define RX65N_RIIC1_SARL1 (RX65N_RIIC1_BASE + RX65N_RIIC_SARL1_OFFSET)
+#define RX65N_RIIC1_SARU1 (RX65N_RIIC1_BASE + RX65N_RIIC_SARU1_OFFSET)
+#define RX65N_RIIC1_SARL2 (RX65N_RIIC1_BASE + RX65N_RIIC_SARL2_OFFSET)
+#define RX65N_RIIC1_SARU2 (RX65N_RIIC1_BASE + RX65N_RIIC_SARU2_OFFSET)
+#define RX65N_RIIC1_ICBRL (RX65N_RIIC1_BASE + RX65N_RIIC_ICBRL_OFFSET)
+#define RX65N_RIIC1_ICBRH (RX65N_RIIC1_BASE + RX65N_RIIC_ICBRH_OFFSET)
+#define RX65N_RIIC1_ICDRT (RX65N_RIIC1_BASE + RX65N_RIIC_ICDRT_OFFSET)
+#define RX65N_RIIC1_ICDRR (RX65N_RIIC1_BASE + RX65N_RIIC_ICDRR_OFFSET)
+
+#define RX65N_RIIC2_ICCR1 (RX65N_RIIC2_BASE + RX65N_RIIC_ICCR1_OFFSET)
+#define RX65N_RIIC2_ICCR2 (RX65N_RIIC2_BASE + RX65N_RIIC_ICCR2_OFFSET)
+#define RX65N_RIIC2_ICMR1 (RX65N_RIIC2_BASE + RX65N_RIIC_ICMR1_OFFSET)
+#define RX65N_RIIC2_ICMR2 (RX65N_RIIC2_BASE + RX65N_RIIC_ICMR2_OFFSET)
+#define RX65N_RIIC2_ICMR3 (RX65N_RIIC2_BASE + RX65N_RIIC_ICMR3_OFFSET)
+#define RX65N_RIIC2_ICFER (RX65N_RIIC2_BASE + RX65N_RIIC_ICFER_OFFSET)
+#define RX65N_RIIC2_ICSER (RX65N_RIIC2_BASE + RX65N_RIIC_ICSER_OFFSET)
+#define RX65N_RIIC2_ICIER (RX65N_RIIC2_BASE + RX65N_RIIC_ICIER_OFFSET)
+#define RX65N_RIIC2_ICSR1 (RX65N_RIIC2_BASE + RX65N_RIIC_ICSR1_OFFSET)
+#define RX65N_RIIC2_ICSR2 (RX65N_RIIC2_BASE + RX65N_RIIC_ICSR2_OFFSET)
+#define RX65N_RIIC2_SARL0 (RX65N_RIIC2_BASE + RX65N_RIIC_SARL0_OFFSET)
+#define RX65N_RIIC2_SARU0 (RX65N_RIIC2_BASE + RX65N_RIIC_SARU0_OFFSET)
+#define RX65N_RIIC2_SARL1 (RX65N_RIIC2_BASE + RX65N_RIIC_SARL1_OFFSET)
+#define RX65N_RIIC2_SARU1 (RX65N_RIIC2_BASE + RX65N_RIIC_SARU1_OFFSET)
+#define RX65N_RIIC2_SARL2 (RX65N_RIIC2_BASE + RX65N_RIIC_SARL2_OFFSET)
+#define RX65N_RIIC2_SARU2 (RX65N_RIIC2_BASE + RX65N_RIIC_SARU2_OFFSET)
+#define RX65N_RIIC2_ICBRL (RX65N_RIIC2_BASE + RX65N_RIIC_ICBRL_OFFSET)
+#define RX65N_RIIC2_ICBRH (RX65N_RIIC2_BASE + RX65N_RIIC_ICBRH_OFFSET)
+#define RX65N_RIIC2_ICDRT (RX65N_RIIC2_BASE + RX65N_RIIC_ICDRT_OFFSET)
+#define RX65N_RIIC2_ICDRR (RX65N_RIIC2_BASE + RX65N_RIIC_ICDRR_OFFSET)
+
+#define RX65N_RIIC_ICCR1_ICE_RST (0x7f)
+#define RX65N_RIIC_ICCR1_IICRST_SET (0x40)
+
+#define RX65N_RIIC_ICCR2_ST_SET (0x02)
+#define RX65N_RIIC_ICCR2_SP_SET (0x08)
+#define RX65N_RIIC_ICCR2_RS_SET (0x04)
+
+#define RX65N_RIIC_ICSR2_STOP_SET (0x08)
Review comment:
corrected the alignment
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