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commit 8397881df4a1a662f36149682893170627353414 Author: raiden00pl <[email protected]> AuthorDate: Tue Jun 9 14:46:55 2026 +0200 !arch/stm32h7: unify non-standard hardware definition prefixes BREAKING CHANGE: STM32H7 non-standard hardware definition macros (IRQ, peripheral-count, SRAM and related) were renamed to the common STM32_* prefix. Out-of-tree code must update the affected references. Signed-off-by: raiden00pl <[email protected]> --- arch/arm/include/stm32h7/chip.h | 192 +++++++++++------------ arch/arm/src/stm32h7/hardware/stm32_qspi.h | 4 +- arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h | 22 +-- arch/arm/src/stm32h7/hardware/stm32h7x3xx_i2c.h | 8 +- arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h | 12 +- arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h | 16 +- arch/arm/src/stm32h7/stm32_allocateheap.c | 12 +- arch/arm/src/stm32h7/stm32_bbsram.c | 10 +- arch/arm/src/stm32h7/stm32_bbsram.h | 8 +- arch/arm/src/stm32h7/stm32_capture_lowerhalf.c | 62 ++++---- arch/arm/src/stm32h7/stm32_ethernet.c | 106 ++++++------- arch/arm/src/stm32h7/stm32_ethernet.h | 6 +- arch/arm/src/stm32h7/stm32_gpio.c | 30 ++-- arch/arm/src/stm32h7/stm32_gpio.h | 24 +-- arch/arm/src/stm32h7/stm32_mpuinit.c | 2 +- arch/arm/src/stm32h7/stm32_otg.h | 2 +- arch/arm/src/stm32h7/stm32_sdmmc.c | 4 +- arch/arm/src/stm32h7/stm32_serial.c | 6 +- arch/arm/src/stm32h7/stm32_uart.h | 16 +- arch/arm/src/stm32h7/stm32h7x3xx_rcc.c | 22 +-- arch/arm/src/stm32h7/stm32h7x7xx_rcc.c | 22 +-- 21 files changed, 293 insertions(+), 293 deletions(-) diff --git a/arch/arm/include/stm32h7/chip.h b/arch/arm/include/stm32h7/chip.h index b97a8659e6c..2aa62e17e93 100644 --- a/arch/arm/include/stm32h7/chip.h +++ b/arch/arm/include/stm32h7/chip.h @@ -95,154 +95,154 @@ /* Memory */ # ifdef CONFIG_STM32H7_STM32H72XXX_OR_STM32H73XXX -# define STM32H7_SRAM_SIZE (320*1024) /* 320Kb SRAM on AXI bus Matrix (D1) */ -# define STM32H7_SRAM1_SIZE (16*1024) /* 16Kb SRAM1 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM3_SIZE (0*1024) /* No SRAM3 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM123_SIZE (32*1024) /* 32Kb SRAM123 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM4_SIZE (16*1024) /* 16Kb SRAM4 on AHB bus Matrix (D3) */ +# define STM32_SRAM_SIZE (320*1024) /* 320Kb SRAM on AXI bus Matrix (D1) */ +# define STM32_SRAM1_SIZE (16*1024) /* 16Kb SRAM1 on AHB bus Matrix (D2) */ +# define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix (D2) */ +# define STM32_SRAM3_SIZE (0*1024) /* No SRAM3 on AHB bus Matrix (D2) */ +# define STM32_SRAM123_SIZE (32*1024) /* 32Kb SRAM123 on AHB bus Matrix (D2) */ +# define STM32_SRAM4_SIZE (16*1024) /* 16Kb SRAM4 on AHB bus Matrix (D3) */ # else /* STM32H74XXX or STM32H75XXX with full SRAM configuration */ -# define STM32H7_SRAM_SIZE (512*1024) /* 512Kb SRAM on AXI bus Matrix (D1) */ -# define STM32H7_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM2_SIZE (128*1024) /* 128Kb SRAM2 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM3_SIZE (32*1024) /* 32Kb SRAM3 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM123_SIZE (288*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM4_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D3) */ +# define STM32_SRAM_SIZE (512*1024) /* 512Kb SRAM on AXI bus Matrix (D1) */ +# define STM32_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix (D2) */ +# define STM32_SRAM2_SIZE (128*1024) /* 128Kb SRAM2 on AHB bus Matrix (D2) */ +# define STM32_SRAM3_SIZE (32*1024) /* 32Kb SRAM3 on AHB bus Matrix (D2) */ +# define STM32_SRAM123_SIZE (288*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */ +# define STM32_SRAM4_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D3) */ # endif /* STM32H72XXX or STM32H73XXX / STM32H74XXX or STM32H75XXX */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) -# define STM32H7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ # else -# define STM32H7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ # endif # if defined(CONFIG_ARMV7M_HAVE_ITCM) -# define STM32H7_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */ # else -# define STM32H7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ # endif /* Peripherals */ # if defined(CONFIG_STM32H7_IO_CONFIG_A) -# define STM32H7_NGPIO (10) /* GPIOA-GPIOJ */ +# define STM32_NGPIO (10) /* GPIOA-GPIOJ */ # elif defined(CONFIG_STM32H7_IO_CONFIG_B) -# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */ +# define STM32_NGPIO (11) /* GPIOA-GPIOK */ # elif defined(CONFIG_STM32H7_IO_CONFIG_I) -# define STM32H7_NGPIO (9) /* GPIOA-GPIOI */ +# define STM32_NGPIO (9) /* GPIOA-GPIOI */ # elif defined(CONFIG_STM32H7_IO_CONFIG_V) -# define STM32H7_NGPIO (8) /* GPIOA-GPIOH, missing GPIOF-GPIOG */ +# define STM32_NGPIO (8) /* GPIOA-GPIOH, missing GPIOF-GPIOG */ # elif defined(CONFIG_STM32H7_IO_CONFIG_X) -# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */ +# define STM32_NGPIO (11) /* GPIOA-GPIOK */ # elif defined(CONFIG_STM32H7_IO_CONFIG_Z) -# define STM32H7_NGPIO (8) /* GPIOA-GPIOH */ +# define STM32_NGPIO (8) /* GPIOA-GPIOH */ # else # error CONFIG_STM32H7_IO_CONFIG_x Not Set # endif -# define STM32H7_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */ -# define STM32H7_NADC (3) /* (3) ADC1-3*/ -# define STM32H7_NDAC (2) /* (2) DAC1-2*/ -# define STM32H7_NCMP (2) /* (2) ultra-low power comparators */ -# define STM32H7_NPGA (2) /* (2) Operational amplifiers: OPAMP */ -# define STM32H7_NDFSDM (1) /* (1) digital filters for sigma delta modulator */ -# define STM32H7_NUSART (4) /* (4) USART1-3, 6 */ -# define STM32H7_NSPI (6) /* (6) SPI1-6 */ -# define STM32H7_NI2S (3) /* (3) I2S1-3 */ -# define STM32H7_NUART (4) /* (4) UART4-5, 7-8 */ -# define STM32H7_NI2C (4) /* (4) I2C1-4 */ -# define STM32H7_NSAI (4) /* (4) SAI1-4*/ -# define STM32H7_NCAN (2) /* (2) CAN1-2 */ -# define STM32H7_NSDIO (2) /* (2) SDIO */ +# define STM32_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */ +# define STM32_NADC (3) /* (3) ADC1-3*/ +# define STM32_NDAC (2) /* (2) DAC1-2*/ +# define STM32_NCMP (2) /* (2) ultra-low power comparators */ +# define STM32_NPGA (2) /* (2) Operational amplifiers: OPAMP */ +# define STM32_NDFSDM (1) /* (1) digital filters for sigma delta modulator */ +# define STM32_NUSART (4) /* (4) USART1-3, 6 */ +# define STM32_NSPI (6) /* (6) SPI1-6 */ +# define STM32_NI2S (3) /* (3) I2S1-3 */ +# define STM32_NUART (4) /* (4) UART4-5, 7-8 */ +# define STM32_NI2C (4) /* (4) I2C1-4 */ +# define STM32_NSAI (4) /* (4) SAI1-4*/ +# define STM32_NCAN (2) /* (2) CAN1-2 */ +# define STM32_NSDIO (2) /* (2) SDIO */ #elif defined(CONFIG_STM32H7_STM32H7B3XX) /* Memory */ -# define STM32H7_SRAM_SIZE (1024*1024) /* 1024Kb SRAM on AXI bus Matrix (D1) */ -# define STM32H7_SRAM1_SIZE (64*1024) /* 64Kb SRAM1 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM3_SIZE (0*1024) /* No SRAM3 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM123_SIZE (128*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM4_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix (D3) */ +# define STM32_SRAM_SIZE (1024*1024) /* 1024Kb SRAM on AXI bus Matrix (D1) */ +# define STM32_SRAM1_SIZE (64*1024) /* 64Kb SRAM1 on AHB bus Matrix (D2) */ +# define STM32_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D2) */ +# define STM32_SRAM3_SIZE (0*1024) /* No SRAM3 on AHB bus Matrix (D2) */ +# define STM32_SRAM123_SIZE (128*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */ +# define STM32_SRAM4_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix (D3) */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) -# define STM32H7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ # else -# define STM32H7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ # endif # if defined(CONFIG_ARMV7M_HAVE_ITCM) -# define STM32H7_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */ # else -# define STM32H7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ # endif /* Peripherals */ # if defined(CONFIG_STM32H7_IO_CONFIG_A) -# define STM32H7_NGPIO (10) /* GPIOA-GPIOJ */ +# define STM32_NGPIO (10) /* GPIOA-GPIOJ */ # elif defined(CONFIG_STM32H7_IO_CONFIG_B) -# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */ +# define STM32_NGPIO (11) /* GPIOA-GPIOK */ # elif defined(CONFIG_STM32H7_IO_CONFIG_I) -# define STM32H7_NGPIO (9) /* GPIOA-GPIOI */ +# define STM32_NGPIO (9) /* GPIOA-GPIOI */ # elif defined(CONFIG_STM32H7_IO_CONFIG_L) -# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */ +# define STM32_NGPIO (11) /* GPIOA-GPIOK */ # elif defined(CONFIG_STM32H7_IO_CONFIG_V) -# define STM32H7_NGPIO (8) /* GPIOA-GPIOH, missing GPIOF-GPIOG */ +# define STM32_NGPIO (8) /* GPIOA-GPIOH, missing GPIOF-GPIOG */ # elif defined(CONFIG_STM32H7_IO_CONFIG_X) -# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */ +# define STM32_NGPIO (11) /* GPIOA-GPIOK */ # elif defined(CONFIG_STM32H7_IO_CONFIG_Z) -# define STM32H7_NGPIO (8) /* GPIOA-GPIOH */ +# define STM32_NGPIO (8) /* GPIOA-GPIOH */ # else # error CONFIG_STM32H7_IO_CONFIG_x Not Set # endif -# define STM32H7_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */ -# define STM32H7_NADC (3) /* (3) ADC1-3*/ -# define STM32H7_NDAC (2) /* (2) DAC1-2*/ -# define STM32H7_NCMP (2) /* (2) ultra-low power comparators */ -# define STM32H7_NPGA (2) /* (2) Operational amplifiers: OPAMP */ -# define STM32H7_NDFSDM (1) /* (1) digital filters for sigma delta modulator */ -# define STM32H7_NUSART (4) /* (4) USART1-3, 6 */ -# define STM32H7_NSPI (6) /* (6) SPI1-6 */ -# define STM32H7_NI2S (3) /* (3) I2S1-3 */ -# define STM32H7_NUART (4) /* (4) UART4-5, 7-8 */ -# define STM32H7_NI2C (4) /* (4) I2C1-4 */ -# define STM32H7_NSAI (4) /* (4) SAI1-4*/ -# define STM32H7_NCAN (2) /* (2) CAN1-2 */ -# define STM32H7_NSDIO (2) /* (2) SDIO */ +# define STM32_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */ +# define STM32_NADC (3) /* (3) ADC1-3*/ +# define STM32_NDAC (2) /* (2) DAC1-2*/ +# define STM32_NCMP (2) /* (2) ultra-low power comparators */ +# define STM32_NPGA (2) /* (2) Operational amplifiers: OPAMP */ +# define STM32_NDFSDM (1) /* (1) digital filters for sigma delta modulator */ +# define STM32_NUSART (4) /* (4) USART1-3, 6 */ +# define STM32_NSPI (6) /* (6) SPI1-6 */ +# define STM32_NI2S (3) /* (3) I2S1-3 */ +# define STM32_NUART (4) /* (4) UART4-5, 7-8 */ +# define STM32_NI2C (4) /* (4) I2C1-4 */ +# define STM32_NSAI (4) /* (4) SAI1-4*/ +# define STM32_NCAN (2) /* (2) CAN1-2 */ +# define STM32_NSDIO (2) /* (2) SDIO */ #elif defined(CONFIG_STM32H7_STM32H7X7XX) /* Memory */ -# define STM32H7_SRAM_SIZE (512*1024) /* 512Kb SRAM on AXI bus Matrix (D1) */ -# define STM32H7_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM2_SIZE (128*1024) /* 128Kb SRAM2 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM3_SIZE (32*1024) /* 32Kb SRAM3 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM123_SIZE (288*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM4_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D3) */ +# define STM32_SRAM_SIZE (512*1024) /* 512Kb SRAM on AXI bus Matrix (D1) */ +# define STM32_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix (D2) */ +# define STM32_SRAM2_SIZE (128*1024) /* 128Kb SRAM2 on AHB bus Matrix (D2) */ +# define STM32_SRAM3_SIZE (32*1024) /* 32Kb SRAM3 on AHB bus Matrix (D2) */ +# define STM32_SRAM123_SIZE (288*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */ +# define STM32_SRAM4_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D3) */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) -# define STM32H7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ # else -# define STM32H7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ # endif # if defined(CONFIG_ARMV7M_HAVE_ITCM) -# define STM32H7_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */ # else -# define STM32H7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ # endif /* Peripherals */ -# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */ -# define STM32H7_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */ -# define STM32H7_NADC (3) /* (3) ADC1-3*/ -# define STM32H7_NDAC (2) /* (2) DAC1-2*/ -# define STM32H7_NCMP (2) /* (2) ultra-low power comparators */ -# define STM32H7_NPGA (2) /* (2) Operational amplifiers: OPAMP */ -# define STM32H7_NDFSDM (1) /* (1) digital filters for sigma delta modulator */ -# define STM32H7_NUSART (4) /* (4) USART1-3, 6 */ -# define STM32H7_NSPI (6) /* (6) SPI1-6 */ -# define STM32H7_NI2S (3) /* (3) I2S1-3 */ -# define STM32H7_NUART (4) /* (4) UART4-5, 7-8 */ -# define STM32H7_NI2C (4) /* (4) I2C1-4 */ -# define STM32H7_NSAI (4) /* (4) SAI1-4*/ -# define STM32H7_NCAN (2) /* (2) CAN1-2 */ -# define STM32H7_NSDIO (2) /* (2) SDIO */ +# define STM32_NGPIO (11) /* GPIOA-GPIOK */ +# define STM32_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */ +# define STM32_NADC (3) /* (3) ADC1-3*/ +# define STM32_NDAC (2) /* (2) DAC1-2*/ +# define STM32_NCMP (2) /* (2) ultra-low power comparators */ +# define STM32_NPGA (2) /* (2) Operational amplifiers: OPAMP */ +# define STM32_NDFSDM (1) /* (1) digital filters for sigma delta modulator */ +# define STM32_NUSART (4) /* (4) USART1-3, 6 */ +# define STM32_NSPI (6) /* (6) SPI1-6 */ +# define STM32_NI2S (3) /* (3) I2S1-3 */ +# define STM32_NUART (4) /* (4) UART4-5, 7-8 */ +# define STM32_NI2C (4) /* (4) I2C1-4 */ +# define STM32_NSAI (4) /* (4) SAI1-4*/ +# define STM32_NCAN (2) /* (2) CAN1-2 */ +# define STM32_NSDIO (2) /* (2) SDIO */ #else # error STM32 H7 chip Family not identified #endif @@ -260,15 +260,15 @@ /* Diversification based on Family and package */ #if defined(CONFIG_STM32H7_HAVE_ETHERNET) -# define STM32H7_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ #else -# define STM32H7_NETHERNET 0 /* No 100/100 Ethernet MAC */ +# define STM32_NETHERNET 0 /* No 100/100 Ethernet MAC */ #endif #if defined(CONFIG_STM32H7_HAVE_FMC) -# define STM32H7_NFMC 1 /* Have FMC memory controller */ +# define STM32_NFMC 1 /* Have FMC memory controller */ #else -# define STM32H7_NFMC 0 /* No FMC memory controller */ +# define STM32_NFMC 0 /* No FMC memory controller */ #endif /* NVIC priority levels *****************************************************/ diff --git a/arch/arm/src/stm32h7/hardware/stm32_qspi.h b/arch/arm/src/stm32h7/hardware/stm32_qspi.h index dcc4e882cdf..a66957eac89 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_qspi.h +++ b/arch/arm/src/stm32h7/hardware/stm32_qspi.h @@ -38,8 +38,8 @@ /* General Characteristics **************************************************/ -#define STM32H7_QSPI_MINBITS 8 /* Minimum word width */ -#define STM32H7_QSPI_MAXBITS 32 /* Maximum word width */ +#define STM32_QSPI_MINBITS 8 /* Minimum word width */ +#define STM32_QSPI_MAXBITS 32 /* Maximum word width */ /* QSPI register offsets ****************************************************/ diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h index e052e88da45..c38ff4666e2 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h @@ -55,7 +55,7 @@ /* Register Addresses *******************************************************/ -#if STM32H7_NGPIO > 0 +#if STM32_NGPIO > 0 # define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -68,7 +68,7 @@ # define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 1 +#if STM32_NGPIO > 1 # define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -81,7 +81,7 @@ # define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 2 +#if STM32_NGPIO > 2 # define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -94,7 +94,7 @@ # define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 3 +#if STM32_NGPIO > 3 # define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -107,7 +107,7 @@ # define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 4 +#if STM32_NGPIO > 4 # define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -120,7 +120,7 @@ # define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if (STM32H7_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) +#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) # define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -133,7 +133,7 @@ # define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if (STM32H7_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) +#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) # define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -146,7 +146,7 @@ # define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 7 +#if STM32_NGPIO > 7 # define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -159,7 +159,7 @@ # define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 8 +#if STM32_NGPIO > 8 # define STM32_GPIOI_MODER (STM32_GPIOI_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -172,7 +172,7 @@ # define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 9 +#if STM32_NGPIO > 9 # define STM32_GPIOJ_MODER (STM32_GPIOJ_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOJ_OTYPER (STM32_GPIOJ_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOJ_OSPEED (STM32_GPIOJ_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -185,7 +185,7 @@ # define STM32_GPIOJ_AFRH (STM32_GPIOJ_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 10 +#if STM32_NGPIO > 10 # define STM32_GPIOK_MODER (STM32_GPIOK_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOK_OTYPER (STM32_GPIOK_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOK_OSPEED (STM32_GPIOK_BASE+STM32_GPIO_OSPEED_OFFSET) diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_i2c.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_i2c.h index bd2e3590407..944b1f0ef2c 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_i2c.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_i2c.h @@ -43,7 +43,7 @@ /* Register Addresses *******************************************************/ -#if STM32H7_NI2C > 0 +#if STM32_NI2C > 0 # define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET) @@ -57,7 +57,7 @@ # define STM32_I2C1_TXDR (STM32_I2C1_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32H7_NI2C > 1 +#if STM32_NI2C > 1 # define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET) @@ -71,7 +71,7 @@ # define STM32_I2C2_TXDR (STM32_I2C2_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32H7_NI2C > 2 +#if STM32_NI2C > 2 # define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET) @@ -85,7 +85,7 @@ # define STM32_I2C3_TXDR (STM32_I2C3_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32H7_NI2C > 3 +#if STM32_NI2C > 3 # define STM32_I2C4_CR1 (STM32_I2C4_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C4_CR2 (STM32_I2C4_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C4_OAR1 (STM32_I2C4_BASE+STM32_I2C_OAR1_OFFSET) diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h index 2e00669d7d4..fa7c71d92bf 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h @@ -62,7 +62,7 @@ /* Register Addresses *******************************************************/ -#if STM32H7_NSPI > 0 +#if STM32_NSPI > 0 # define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI1_CFG1 (STM32_SPI1_BASE+STM32_SPI_CFG1_OFFSET) @@ -79,7 +79,7 @@ # define STM32_SPI1_I2SCFGR (STM32_SPI1_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H7_NSPI > 1 +#if STM32_NSPI > 1 # define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI2_CFG1 (STM32_SPI2_BASE+STM32_SPI_CFG1_OFFSET) @@ -96,7 +96,7 @@ # define STM32_SPI2_I2SCFGR (STM32_SPI2_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H7_NSPI > 2 +#if STM32_NSPI > 2 # define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI3_CFG1 (STM32_SPI3_BASE+STM32_SPI_CFG1_OFFSET) @@ -113,7 +113,7 @@ # define STM32_SPI3_I2SCFGR (STM32_SPI3_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H7_NSPI > 3 +#if STM32_NSPI > 3 # define STM32_SPI4_CR1 (STM32_SPI4_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI4_CR2 (STM32_SPI4_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI4_CFG1 (STM32_SPI4_BASE+STM32_SPI_CFG1_OFFSET) @@ -130,7 +130,7 @@ # define STM32_SPI4_I2SCFGR (STM32_SPI4_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H7_NSPI > 4 +#if STM32_NSPI > 4 # define STM32_SPI5_CR1 (STM32_SPI5_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI5_CR2 (STM32_SPI5_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI5_CFG1 (STM32_SPI5_BASE+STM32_SPI_CFG1_OFFSET) @@ -147,7 +147,7 @@ # define STM32_SPI5_I2SCFGR (STM32_SPI5_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H7_NSPI > 5 +#if STM32_NSPI > 5 # define STM32_SPI6_CR1 (STM32_SPI6_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI6_CR2 (STM32_SPI6_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI6_CFG1 (STM32_SPI6_BASE+STM32_SPI_CFG1_OFFSET) diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h index e5785ef1c16..7bab6c142c4 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h @@ -58,7 +58,7 @@ /* Register Addresses *******************************************************/ -#if STM32H7_NUSART > 0 +#if STM32_NUSART > 0 # define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET) @@ -74,7 +74,7 @@ # define STM32_USART1_PRESC (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H7_NUSART > 1 +#if STM32_NUSART > 1 # define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET) @@ -90,7 +90,7 @@ # define STM32_USART2_PRESC (STM32_USART2_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H7_NUSART > 2 +#if STM32_NUSART > 2 # define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET) @@ -106,7 +106,7 @@ # define STM32_USART3_PRESC (STM32_USART3_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H7_NUSART > 3 +#if STM32_NUSART > 3 # define STM32_USART6_CR1 (STM32_USART6_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART6_CR2 (STM32_USART6_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART6_CR3 (STM32_USART6_BASE + STM32_USART_CR3_OFFSET) @@ -122,7 +122,7 @@ # define STM32_USART6_PRESC (STM32_USART6_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H7_NUART > 0 +#if STM32_NUART > 0 # define STM32_UART4_CR1 (STM32_UART4_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART4_CR2 (STM32_UART4_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART4_CR3 (STM32_UART4_BASE + STM32_USART_CR3_OFFSET) @@ -137,7 +137,7 @@ # define STM32_UART4_TDR (STM32_UART4_BASE + STM32_USART_TDR_OFFSET) #endif -#if STM32H7_NUART > 1 +#if STM32_NUART > 1 # define STM32_UART5_CR1 (STM32_UART5_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART5_CR2 (STM32_UART5_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART5_CR3 (STM32_UART5_BASE + STM32_USART_CR3_OFFSET) @@ -152,7 +152,7 @@ # define STM32_UART5_TDR (STM32_UART5_BASE + STM32_USART_TDR_OFFSET) #endif -#if STM32H7_NUART > 2 +#if STM32_NUART > 2 # define STM32_UART7_CR1 (STM32_UART7_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART7_CR2 (STM32_UART7_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART7_CR3 (STM32_UART7_BASE + STM32_USART_CR3_OFFSET) @@ -167,7 +167,7 @@ # define STM32_UART7_TDR (STM32_UART7_BASE + STM32_USART_TDR_OFFSET) #endif -#if STM32H7_NUART > 3 +#if STM32_NUART > 3 # define STM32_UART8_CR1 (STM32_UART8_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART8_CR2 (STM32_UART8_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART8_CR3 (STM32_UART8_BASE + STM32_USART_CR3_OFFSET) diff --git a/arch/arm/src/stm32h7/stm32_allocateheap.c b/arch/arm/src/stm32h7/stm32_allocateheap.c index cec7d503b3b..3b64acba794 100644 --- a/arch/arm/src/stm32h7/stm32_allocateheap.c +++ b/arch/arm/src/stm32h7/stm32_allocateheap.c @@ -111,10 +111,10 @@ /* Set the start and end of the SRAMs */ # define SRAM_START STM32_AXISRAM_BASE -# define SRAM_END (SRAM_START + STM32H7_SRAM_SIZE) +# define SRAM_END (SRAM_START + STM32_SRAM_SIZE) # define SRAM123_START STM32_SRAM123_BASE -# define SRAM123_END (SRAM123_START + STM32H7_SRAM123_SIZE) +# define SRAM123_END (SRAM123_START + STM32_SRAM123_SIZE) #elif defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ defined(CONFIG_STM32H7_CORTEXM4_ENABLED) @@ -122,7 +122,7 @@ /* Configuration for M7 core when M4 core support enabled */ # define SRAM_START STM32_AXISRAM_BASE -# define SRAM_END (SRAM_START + STM32H7_SRAM_SIZE) +# define SRAM_END (SRAM_START + STM32_SRAM_SIZE) /* Exclude SRAM123 */ @@ -134,8 +134,8 @@ /* Configuration for M4 core support enabled */ # define SRAM_START STM32_SRAM123_BASE -# define SRAM_END (SRAM_START + STM32H7_SRAM123_SIZE - \ - STM32H7_SRAM3_SIZE) +# define SRAM_END (SRAM_START + STM32_SRAM123_SIZE - \ + STM32_SRAM3_SIZE) #endif #undef HAVE_SRAM4 @@ -143,7 +143,7 @@ # define HAVE_SRAM4 1 # define SRAM4_START ((uint32_t)(STM32_SRAM4_BASE)) -# define SRAM4_END ((uint32_t)(SRAM4_START + STM32H7_SRAM4_SIZE)) +# define SRAM4_END ((uint32_t)(SRAM4_START + STM32_SRAM4_SIZE)) # define SRAM4_HEAP_START ((uint32_t)_sram4_heap_start) #endif diff --git a/arch/arm/src/stm32h7/stm32_bbsram.c b/arch/arm/src/stm32h7/stm32_bbsram.c index a4666960d31..8f27740c1aa 100644 --- a/arch/arm/src/stm32h7/stm32_bbsram.c +++ b/arch/arm/src/stm32h7/stm32_bbsram.c @@ -151,7 +151,7 @@ static int stm32_bbsram_unlink(struct inode *inode); ****************************************************************************/ #if defined(CONFIG_BBSRAM_DEBUG) -static uint8_t debug[STM32H7_BBSRAM_SIZE]; +static uint8_t debug[STM32_BBSRAM_SIZE]; #endif static const struct file_operations g_stm32_bbsram_fops = @@ -591,7 +591,7 @@ static int stm32_bbsram_ioctl(struct file *filep, int cmd, DEBUGASSERT(inode->i_private); bbr = inode->i_private; - if (cmd == STM32H7_BBSRAM_GETDESC_IOCTL) + if (cmd == STM32_BBSRAM_GETDESC_IOCTL) { struct bbsramd_s *bbrr = (struct bbsramd_s *)((uintptr_t)arg); @@ -688,7 +688,7 @@ static int stm32_bbsram_probe(int *ent, struct stm32_bbsram_s pdev[]) * after reset due to the ECC behavior. */ - avail = STM32H7_BBSRAM_SIZE; + avail = STM32_BBSRAM_SIZE; for (i = 0; (i < CONFIG_STM32H7_BBSRAM_FILES) && ent[i] && (avail > 0); i++) @@ -793,9 +793,9 @@ int stm32_bbsraminitialize(char *devpath, int *sizes) */ # if defined(CONFIG_BUILD_PROTECTED) - mpu_peripheral(STM32_BBSRAM_BASE, STM32H7_BBSRAM_SIZE); + mpu_peripheral(STM32_BBSRAM_BASE, STM32_BBSRAM_SIZE); # else - mpu_user_peripheral(STM32_BBSRAM_BASE, STM32H7_BBSRAM_SIZE); + mpu_user_peripheral(STM32_BBSRAM_BASE, STM32_BBSRAM_SIZE); mpu_control(true, true, true); # endif #endif diff --git a/arch/arm/src/stm32h7/stm32_bbsram.h b/arch/arm/src/stm32h7/stm32_bbsram.h index c9d41f73cc2..08421e22571 100644 --- a/arch/arm/src/stm32h7/stm32_bbsram.h +++ b/arch/arm/src/stm32h7/stm32_bbsram.h @@ -46,17 +46,17 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32H7_BBSRAM_SIZE 4096 +#define STM32_BBSRAM_SIZE 4096 #if !defined(CONFIG_STM32H7_BBSRAM_FILES) # define CONFIG_STM32H7_BBSRAM_FILES 4 #endif -/* REVISIT: What guarantees that STM32H7_BBSRAM_GETDESC_IOCTL has a unique +/* REVISIT: What guarantees that STM32_BBSRAM_GETDESC_IOCTL has a unique * value among all over _DIOC() values? */ -#define STM32H7_BBSRAM_GETDESC_IOCTL _DIOC(0x0010) /* Returns a bbsramd_s */ +#define STM32_BBSRAM_GETDESC_IOCTL _DIOC(0x0010) /* Returns a bbsramd_s */ /**************************************************************************** * Public Types @@ -126,7 +126,7 @@ int stm32_bbsraminitialize(char *devpath, int *sizes); * Saves the panic context in a previously allocated BBSRAM file * * Parameters: -* fileno - the value returned by the ioctl STM32H7_BBSRAM_GETDESC_IOCTL +* fileno - the value returned by the ioctl STM32_BBSRAM_GETDESC_IOCTL * context - Pointer to a any array of bytes to save * length - The length of the data pointed to byt context * diff --git a/arch/arm/src/stm32h7/stm32_capture_lowerhalf.c b/arch/arm/src/stm32h7/stm32_capture_lowerhalf.c index 6bdf846cfb0..c1a1e71517d 100644 --- a/arch/arm/src/stm32h7/stm32_capture_lowerhalf.c +++ b/arch/arm/src/stm32h7/stm32_capture_lowerhalf.c @@ -47,35 +47,35 @@ /* 32-Bit Timers ************************************************************/ -#define STM32H7_TIM2_RES 32 -#define STM32H7_TIM5_RES 32 +#define STM32_TIM2_RES 32 +#define STM32_TIM5_RES 32 /* 16-Bit Timers ************************************************************/ /* Advanced-Control Timers */ -#define STM32H7_TIM1_RES 16 -#define STM32H7_TIM8_RES 16 +#define STM32_TIM1_RES 16 +#define STM32_TIM8_RES 16 /* General-Purpose Timers */ -#define STM32H7_TIM3_RES 16 -#define STM32H7_TIM4_RES 16 -#define STM32H7_TIM12_RES 16 -#define STM32H7_TIM13_RES 16 -#define STM32H7_TIM14_RES 16 -#define STM32H7_TIM15_RES 16 -#define STM32H7_TIM16_RES 16 -#define STM32H7_TIM17_RES 16 +#define STM32_TIM3_RES 16 +#define STM32_TIM4_RES 16 +#define STM32_TIM12_RES 16 +#define STM32_TIM13_RES 16 +#define STM32_TIM14_RES 16 +#define STM32_TIM15_RES 16 +#define STM32_TIM16_RES 16 +#define STM32_TIM17_RES 16 /* Basic Timers */ -#define STM32H7_TIM6_RES 16 -#define STM32H7_TIM7_RES 16 +#define STM32_TIM6_RES 16 +#define STM32_TIM7_RES 16 /* Low-Power Timers */ -#define STM32H7_LPTIM1_RES 16 -#define STM32H7_LPTIM2_RES 16 -#define STM32H7_LPTIM3_RES 16 -#define STM32H7_LPTIM4_RES 16 -#define STM32H7_LPTIM5_RES 16 +#define STM32_LPTIM1_RES 16 +#define STM32_LPTIM2_RES 16 +#define STM32_LPTIM3_RES 16 +#define STM32_LPTIM4_RES 16 +#define STM32_LPTIM5_RES 16 /**************************************************************************** * Private Types @@ -129,7 +129,7 @@ static const struct cap_ops_s g_cap_ops = static struct stm32_lowerhalf_s g_cap1_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM1_RES, + .resolution = STM32_TIM1_RES, .channel = CONFIG_STM32H7_TIM1_CHANNEL, .clock = CONFIG_STM32H7_TIM1_CLOCK, }; @@ -139,7 +139,7 @@ static struct stm32_lowerhalf_s g_cap1_lowerhalf = static struct stm32_lowerhalf_s g_cap2_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM2_RES, + .resolution = STM32_TIM2_RES, .channel = CONFIG_STM32H7_TIM2_CHANNEL, .clock = CONFIG_STM32H7_TIM2_CLOCK, }; @@ -149,7 +149,7 @@ static struct stm32_lowerhalf_s g_cap2_lowerhalf = static struct stm32_lowerhalf_s g_cap3_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM3_RES, + .resolution = STM32_TIM3_RES, .channel = CONFIG_STM32H7_TIM3_CHANNEL, .clock = CONFIG_STM32H7_TIM3_CLOCK, }; @@ -159,7 +159,7 @@ static struct stm32_lowerhalf_s g_cap3_lowerhalf = static struct stm32_lowerhalf_s g_cap4_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM4_RES, + .resolution = STM32_TIM4_RES, .channel = CONFIG_STM32H7_TIM4_CHANNEL, .clock = CONFIG_STM32H7_TIM4_CLOCK, }; @@ -169,7 +169,7 @@ static struct stm32_lowerhalf_s g_cap4_lowerhalf = static struct stm32_lowerhalf_s g_cap5_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM5_RES, + .resolution = STM32_TIM5_RES, .channel = CONFIG_STM32H7_TIM5_CHANNEL, .clock = CONFIG_STM32H7_TIM5_CLOCK, }; @@ -179,7 +179,7 @@ static struct stm32_lowerhalf_s g_cap5_lowerhalf = static struct stm32_lowerhalf_s g_cap8_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM8_RES, + .resolution = STM32_TIM8_RES, .channel = CONFIG_STM32H7_TIM8_CHANNEL, .clock = CONFIG_STM32H7_TIM8_CLOCK, }; @@ -189,7 +189,7 @@ static struct stm32_lowerhalf_s g_cap8_lowerhalf = static struct stm32_lowerhalf_s g_cap12_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM12_RES, + .resolution = STM32_TIM12_RES, .channel = CONFIG_STM32H7_TIM12_CHANNEL, .clock = CONFIG_STM32H7_TIM12_CLOCK, }; @@ -199,7 +199,7 @@ static struct stm32_lowerhalf_s g_cap12_lowerhalf = static struct stm32_lowerhalf_s g_cap13_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM13_RES, + .resolution = STM32_TIM13_RES, .channel = CONFIG_STM32H7_TIM13_CHANNEL, .clock = CONFIG_STM32H7_TIM13_CLOCK, }; @@ -209,7 +209,7 @@ static struct stm32_lowerhalf_s g_cap13_lowerhalf = static struct stm32_lowerhalf_s g_cap14_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM14_RES, + .resolution = STM32_TIM14_RES, .channel = CONFIG_STM32H7_TIM14_CHANNEL, .clock = CONFIG_STM32H7_TIM14_CLOCK, }; @@ -219,7 +219,7 @@ static struct stm32_lowerhalf_s g_cap14_lowerhalf = static struct stm32_lowerhalf_s g_cap15_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM15_RES, + .resolution = STM32_TIM15_RES, .channel = CONFIG_STM32H7_TIM15_CHANNEL, .clock = CONFIG_STM32H7_TIM15_CLOCK, }; @@ -229,7 +229,7 @@ static struct stm32_lowerhalf_s g_cap15_lowerhalf = static struct stm32_lowerhalf_s g_cap16_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM16_RES, + .resolution = STM32_TIM16_RES, .channel = CONFIG_STM32H7_TIM16_CHANNEL, .clock = CONFIG_STM32H7_TIM16_CLOCK, }; @@ -239,7 +239,7 @@ static struct stm32_lowerhalf_s g_cap16_lowerhalf = static struct stm32_lowerhalf_s g_cap17_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM17_RES, + .resolution = STM32_TIM17_RES, .channel = CONFIG_STM32H7_TIM17_CHANNEL, .clock = CONFIG_STM32H7_TIM17_CLOCK, }; diff --git a/arch/arm/src/stm32h7/stm32_ethernet.c b/arch/arm/src/stm32h7/stm32_ethernet.c index 2787c840596..9cd6b485b88 100644 --- a/arch/arm/src/stm32h7/stm32_ethernet.c +++ b/arch/arm/src/stm32h7/stm32_ethernet.c @@ -68,12 +68,12 @@ #include <arch/board/board.h> -/* STM32H7_NETHERNET determines the number of physical interfaces that can +/* STM32_NETHERNET determines the number of physical interfaces that can * be supported by the hardware. CONFIG_STM32H7_ETHMAC will defined if * any STM32H7 Ethernet support is enabled in the configuration. */ -#if STM32H7_NETHERNET > 0 && defined(CONFIG_STM32H7_ETHMAC) +#if STM32_NETHERNET > 0 && defined(CONFIG_STM32H7_ETHMAC) /**************************************************************************** * Pre-processor Definitions @@ -81,7 +81,7 @@ /* Configuration ************************************************************/ -#if STM32H7_NETHERNET > 1 +#if STM32_NETHERNET > 1 # error "Logic to support multiple Ethernet interfaces is incomplete" #endif @@ -105,59 +105,59 @@ #endif #if defined(CONFIG_ETH0_PHY_AM79C874) -# define STM32H7_PHYID1 MII_PHYID1_AM79C874 -# define STM32H7_PHYID2 MII_PHYID2_AM79C874 +# define STM32_PHYID1 MII_PHYID1_AM79C874 +# define STM32_PHYID2 MII_PHYID2_AM79C874 #elif defined(CONFIG_ETH0_PHY_AR8031) -# define STM32H7_PHYID1 MII_PHYID1_AR8031 -# define STM32H7_PHYID2 MII_PHYID2_AR8031 +# define STM32_PHYID1 MII_PHYID1_AR8031 +# define STM32_PHYID2 MII_PHYID2_AR8031 #elif defined(CONFIG_ETH0_PHY_KS8721) -# define STM32H7_PHYID1 MII_PHYID1_KS8721 -# define STM32H7_PHYID2 MII_PHYID2_KS8721 +# define STM32_PHYID1 MII_PHYID1_KS8721 +# define STM32_PHYID2 MII_PHYID2_KS8721 #elif defined(CONFIG_ETH0_PHY_KSZ8041) -# define STM32H7_PHYID1 MII_PHYID1_KSZ8041 -# define STM32H7_PHYID2 MII_PHYID2_KSZ8041 +# define STM32_PHYID1 MII_PHYID1_KSZ8041 +# define STM32_PHYID2 MII_PHYID2_KSZ8041 #elif defined(CONFIG_ETH0_PHY_KSZ8051) -# define STM32H7_PHYID1 MII_PHYID1_KSZ8051 -# define STM32H7_PHYID2 MII_PHYID2_KSZ8051 +# define STM32_PHYID1 MII_PHYID1_KSZ8051 +# define STM32_PHYID2 MII_PHYID2_KSZ8051 #elif defined(CONFIG_ETH0_PHY_KSZ8061) -# define STM32H7_PHYID1 MII_PHYID1_KSZ8061 -# define STM32H7_PHYID2 MII_PHYID2_KSZ8061 +# define STM32_PHYID1 MII_PHYID1_KSZ8061 +# define STM32_PHYID2 MII_PHYID2_KSZ8061 #elif defined(CONFIG_ETH0_PHY_KSZ8081) -# define STM32H7_PHYID1 MII_PHYID1_KSZ8081 -# define STM32H7_PHYID2 MII_PHYID2_KSZ8081 +# define STM32_PHYID1 MII_PHYID1_KSZ8081 +# define STM32_PHYID2 MII_PHYID2_KSZ8081 #elif defined(CONFIG_ETH0_PHY_DP83848C) -# define STM32H7_PHYID1 MII_PHYID1_DP83848C -# define STM32H7_PHYID2 MII_PHYID2_DP83848C +# define STM32_PHYID1 MII_PHYID1_DP83848C +# define STM32_PHYID2 MII_PHYID2_DP83848C #elif defined(CONFIG_ETH0_PHY_DP83825I) -# define STM32H7_PHYID1 MII_PHYID1_DP83825I -# define STM32H7_PHYID2 MII_PHYID2_DP83825I +# define STM32_PHYID1 MII_PHYID1_DP83825I +# define STM32_PHYID2 MII_PHYID2_DP83825I #elif defined(CONFIG_ETH0_PHY_TJA1100) -# define STM32H7_PHYID1 MII_PHYID1_TJA1100 -# define STM32H7_PHYID2 MII_PHYID2_TJA1100 +# define STM32_PHYID1 MII_PHYID1_TJA1100 +# define STM32_PHYID2 MII_PHYID2_TJA1100 #elif defined(CONFIG_ETH0_PHY_TJA1101) -# define STM32H7_PHYID1 MII_PHYID1_TJA1101 -# define STM32H7_PHYID2 MII_PHYID2_TJA1101 +# define STM32_PHYID1 MII_PHYID1_TJA1101 +# define STM32_PHYID2 MII_PHYID2_TJA1101 #elif defined(CONFIG_ETH0_PHY_TJA1103) -# define STM32H7_PHYID1 MII_PHYID1_TJA1103 -# define STM32H7_PHYID2 MII_PHYID2_TJA1103 +# define STM32_PHYID1 MII_PHYID1_TJA1103 +# define STM32_PHYID2 MII_PHYID2_TJA1103 #elif defined(CONFIG_ETH0_PHY_LAN8720) -# define STM32H7_PHYID1 MII_PHYID1_LAN8720 -# define STM32H7_PHYID2 MII_PHYID2_LAN8720 +# define STM32_PHYID1 MII_PHYID1_LAN8720 +# define STM32_PHYID2 MII_PHYID2_LAN8720 #elif defined(CONFIG_ETH0_PHY_LAN8740) -# define STM32H7_PHYID1 MII_PHYID1_LAN8740 -# define STM32H7_PHYID2 MII_PHYID2_LAN8740 +# define STM32_PHYID1 MII_PHYID1_LAN8740 +# define STM32_PHYID2 MII_PHYID2_LAN8740 #elif defined(CONFIG_ETH0_PHY_LAN8740A) -# define STM32H7_PHYID1 MII_PHYID1_LAN8740A -# define STM32H7_PHYID2 MII_PHYID2_LAN8740A +# define STM32_PHYID1 MII_PHYID1_LAN8740A +# define STM32_PHYID2 MII_PHYID2_LAN8740A #elif defined(CONFIG_ETH0_PHY_LAN8742A) -# define STM32H7_PHYID1 MII_PHYID1_LAN8742A -# define STM32H7_PHYID2 MII_PHYID2_LAN8742A +# define STM32_PHYID1 MII_PHYID1_LAN8742A +# define STM32_PHYID2 MII_PHYID2_LAN8742A #elif defined(CONFIG_ETH0_PHY_DM9161) -# define STM32H7_PHYID1 MII_PHYID1_DM9161 -# define STM32H7_PHYID2 MII_PHYID2_DM9161 +# define STM32_PHYID1 MII_PHYID1_DM9161 +# define STM32_PHYID2 MII_PHYID2_DM9161 #elif defined(CONFIG_ETH0_PHY_YT8512) -# define STM32H7_PHYID1 MII_PHYID1_YT8512 -# define STM32H7_PHYID2 MII_PHYID2_YT8512 +# define STM32_PHYID1 MII_PHYID1_YT8512 +# define STM32_PHYID2 MII_PHYID2_YT8512 #else # warning "No PHY specified!" #endif @@ -289,14 +289,14 @@ #define DESC_PADSIZE DMA_ALIGN_UP(DESC_SIZE) #define ALIGNED_BUFSIZE DMA_ALIGN_UP(ETH_BUFSIZE) -#define RXTABLE_SIZE (STM32H7_NETHERNET * CONFIG_STM32H7_ETH_NRXDESC) -#define TXTABLE_SIZE (STM32H7_NETHERNET * CONFIG_STM32H7_ETH_NTXDESC) +#define RXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32H7_ETH_NRXDESC) +#define TXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32H7_ETH_NTXDESC) #define RXBUFFER_SIZE (CONFIG_STM32H7_ETH_NRXDESC * ALIGNED_BUFSIZE) -#define RXBUFFER_ALLOC (STM32H7_NETHERNET * RXBUFFER_SIZE) +#define RXBUFFER_ALLOC (STM32_NETHERNET * RXBUFFER_SIZE) #define TXBUFFER_SIZE (STM32_ETH_NFREEBUFFERS * ALIGNED_BUFSIZE) -#define TXBUFFER_ALLOC (STM32H7_NETHERNET * TXBUFFER_SIZE) +#define TXBUFFER_ALLOC (STM32_NETHERNET * TXBUFFER_SIZE) /* Extremely detailed register debug that you would normally never want * enabled. @@ -723,7 +723,7 @@ aligned_data(ARMV7M_DCACHE_LINESIZE); /* These are the pre-allocated Ethernet device structures */ -static struct stm32_ethmac_s g_stm32ethmac[STM32H7_NETHERNET]; +static struct stm32_ethmac_s g_stm32ethmac[STM32_NETHERNET]; /**************************************************************************** * Private Function Prototypes @@ -3279,10 +3279,10 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) return ret; } - if (phyval != STM32H7_PHYID1) + if (phyval != STM32_PHYID1) { nerr("ERROR: Incorrect PHYID1: %u expected: %u\n", - phyval, STM32H7_PHYID1); + phyval, STM32_PHYID1); return -ENXIO; } @@ -3297,10 +3297,10 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) return ret; } - if ((phyval & 0xfff0) != (STM32H7_PHYID2 & 0xfff0)) + if ((phyval & 0xfff0) != (STM32_PHYID2 & 0xfff0)) { nerr("ERROR: Incorrect PHYID2: %u expected: %u\n", - phyval, STM32H7_PHYID2); + phyval, STM32_PHYID2); return -ENXIO; } @@ -4120,7 +4120,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv) * ****************************************************************************/ -#if STM32H7_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) int stm32_ethinitialize(int intf) #else static inline int stm32_ethinitialize(int intf) @@ -4135,7 +4135,7 @@ static inline int stm32_ethinitialize(int intf) /* Get the interface structure associated with this interface number. */ - DEBUGASSERT(intf < STM32H7_NETHERNET); + DEBUGASSERT(intf < STM32_NETHERNET); priv = &g_stm32ethmac[intf]; /* Initialize the driver structure */ @@ -4216,7 +4216,7 @@ static inline int stm32_ethinitialize(int intf) * * Description: * This is the "standard" network initialization logic called from the - * low-level initialization logic in arm_initialize.c. If STM32H7_NETHERNET + * low-level initialization logic in arm_initialize.c. If STM32_NETHERNET * greater than one, then board specific logic will have to supply a * version of arm_netinitialize() that calls stm32_ethinitialize() with * the appropriate interface number. @@ -4231,11 +4231,11 @@ static inline int stm32_ethinitialize(int intf) * ****************************************************************************/ -#if STM32H7_NETHERNET == 1 && !defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET == 1 && !defined(CONFIG_NETDEV_LATEINIT) void arm_netinitialize(void) { stm32_ethinitialize(0); } #endif -#endif /* STM32H7_NETHERNET > 0 && CONFIG_STM32H7_ETHMAC */ +#endif /* STM32_NETHERNET > 0 && CONFIG_STM32H7_ETHMAC */ diff --git a/arch/arm/src/stm32h7/stm32_ethernet.h b/arch/arm/src/stm32h7/stm32_ethernet.h index 6f7026bacac..8faf17694ca 100644 --- a/arch/arm/src/stm32h7/stm32_ethernet.h +++ b/arch/arm/src/stm32h7/stm32_ethernet.h @@ -31,7 +31,7 @@ #include "hardware/stm32_ethernet.h" -#if STM32H7_NETHERNET > 0 +#if STM32_NETHERNET > 0 #ifndef __ASSEMBLY__ /**************************************************************************** @@ -67,7 +67,7 @@ extern "C" * ****************************************************************************/ -#if STM32H7_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) int stm32_ethinitialize(int intf); #endif @@ -102,5 +102,5 @@ int stm32_phy_boardinitialize(int intf); #endif #endif /* __ASSEMBLY__ */ -#endif /* STM32H7_NETHERNET > 0 */ +#endif /* STM32_NETHERNET > 0 */ #endif /* __ARCH_ARM_SRC_STM32H7_STM32_ETHERNET_H */ diff --git a/arch/arm/src/stm32h7/stm32_gpio.c b/arch/arm/src/stm32h7/stm32_gpio.c index 8f59ef8b8a8..8723b1d4b5f 100644 --- a/arch/arm/src/stm32h7/stm32_gpio.c +++ b/arch/arm/src/stm32h7/stm32_gpio.c @@ -62,47 +62,47 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; /* Base addresses for each GPIO block */ -const uint32_t g_gpiobase[STM32H7_NGPIO] = +const uint32_t g_gpiobase[STM32_NGPIO] = { -#if STM32H7_NGPIO > 0 +#if STM32_NGPIO > 0 STM32_GPIOA_BASE, #endif -#if STM32H7_NGPIO > 1 +#if STM32_NGPIO > 1 STM32_GPIOB_BASE, #endif -#if STM32H7_NGPIO > 2 +#if STM32_NGPIO > 2 STM32_GPIOC_BASE, #endif -#if STM32H7_NGPIO > 3 +#if STM32_NGPIO > 3 STM32_GPIOD_BASE, #endif -#if STM32H7_NGPIO > 4 +#if STM32_NGPIO > 4 STM32_GPIOE_BASE, #endif -#if STM32H7_NGPIO > 5 +#if STM32_NGPIO > 5 # if defined(CONFIG_STM32H7_HAVE_GPIOF) STM32_GPIOF_BASE, # else 0, # endif #endif -#if STM32H7_NGPIO > 6 +#if STM32_NGPIO > 6 # if defined(CONFIG_STM32H7_HAVE_GPIOG) STM32_GPIOG_BASE, # else 0, # endif #endif -#if STM32H7_NGPIO > 7 +#if STM32_NGPIO > 7 STM32_GPIOH_BASE, #endif -#if STM32H7_NGPIO > 8 +#if STM32_NGPIO > 8 STM32_GPIOI_BASE, #endif -#if STM32H7_NGPIO > 9 +#if STM32_NGPIO > 9 STM32_GPIOJ_BASE, #endif -#if STM32H7_NGPIO > 10 +#if STM32_NGPIO > 10 STM32_GPIOK_BASE, #endif }; @@ -163,7 +163,7 @@ int stm32_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32H7_NGPIO) + if (port >= STM32_NGPIO) { return -EINVAL; } @@ -443,7 +443,7 @@ void stm32_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32H7_NGPIO) + if (port < STM32_NGPIO) { /* Get the port base address */ @@ -485,7 +485,7 @@ bool stm32_gpioread(uint32_t pinset) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32H7_NGPIO) + if (port < STM32_NGPIO) { /* Get the port base address */ diff --git a/arch/arm/src/stm32h7/stm32_gpio.h b/arch/arm/src/stm32h7/stm32_gpio.h index 02a644c3290..ab46e15a402 100644 --- a/arch/arm/src/stm32h7/stm32_gpio.h +++ b/arch/arm/src/stm32h7/stm32_gpio.h @@ -184,37 +184,37 @@ #define GPIO_PORT_SHIFT (4) /* Bit 4-7: Port number */ #define GPIO_PORT_MASK (15 << GPIO_PORT_SHIFT) -#if STM32H7_NGPIO > 0 +#if STM32_NGPIO > 0 # define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */ #endif -#if STM32H7_NGPIO > 1 +#if STM32_NGPIO > 1 # define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */ #endif -#if STM32H7_NGPIO > 2 +#if STM32_NGPIO > 2 # define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */ #endif -#if STM32H7_NGPIO > 3 +#if STM32_NGPIO > 3 # define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */ #endif -#if STM32H7_NGPIO > 4 +#if STM32_NGPIO > 4 # define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */ #endif -#if (STM32H7_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) +#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) # define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */ #endif -#if (STM32H7_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) +#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) # define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */ #endif -#if STM32H7_NGPIO > 7 +#if STM32_NGPIO > 7 # define GPIO_PORTH (7 << GPIO_PORT_SHIFT) /* GPIOH */ #endif -#if STM32H7_NGPIO > 8 +#if STM32_NGPIO > 8 # define GPIO_PORTI (8 << GPIO_PORT_SHIFT) /* GPIOI */ #endif -#if STM32H7_NGPIO > 9 +#if STM32_NGPIO > 9 # define GPIO_PORTJ (9 << GPIO_PORT_SHIFT) /* GPIOJ */ #endif -#if STM32H7_NGPIO > 10 +#if STM32_NGPIO > 10 # define GPIO_PORTK (10 << GPIO_PORT_SHIFT) /* GPIOK */ #endif @@ -262,7 +262,7 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32H7_NGPIO]; +EXTERN const uint32_t g_gpiobase[STM32_NGPIO]; /**************************************************************************** * Public Function Prototypes diff --git a/arch/arm/src/stm32h7/stm32_mpuinit.c b/arch/arm/src/stm32h7/stm32_mpuinit.c index 91d78295bb8..625e7eb2a5f 100644 --- a/arch/arm/src/stm32h7/stm32_mpuinit.c +++ b/arch/arm/src/stm32h7/stm32_mpuinit.c @@ -46,7 +46,7 @@ #ifdef CONFIG_RPTUN # ifdef CONFIG_STM32H7_SHMEM_SRAM3 # define STM32_SHMEM_BASE STM32_SRAM3_BASE -# define STM32_SHMEM_SIZE STM32H7_SRAM3_SIZE +# define STM32_SHMEM_SIZE STM32_SRAM3_SIZE # else # error missing shmem MPU configuration # endif diff --git a/arch/arm/src/stm32h7/stm32_otg.h b/arch/arm/src/stm32h7/stm32_otg.h index 131be78c428..43208d091f9 100644 --- a/arch/arm/src/stm32h7/stm32_otg.h +++ b/arch/arm/src/stm32h7/stm32_otg.h @@ -42,7 +42,7 @@ #if (STM32_RCC_D2CCIP2R_USBSRC == RCC_D2CCIP2R_USBSEL_HSI48) && \ !defined(CONFIG_STM32H7_HSI48) # error board.h selected HSI48 as USB clock source, but HSI48 is not \ - enabled. Enable STM32H7_HSI48 + enabled. Enable STM32_HSI48 #endif #if defined(CONFIG_STM32H7_OTGHS) && !defined(CONFIG_STM32H7_OTGHS_FS) && \ diff --git a/arch/arm/src/stm32h7/stm32_sdmmc.c b/arch/arm/src/stm32h7/stm32_sdmmc.c index 414e6c5dbdd..cfddcb3be49 100644 --- a/arch/arm/src/stm32h7/stm32_sdmmc.c +++ b/arch/arm/src/stm32h7/stm32_sdmmc.c @@ -135,9 +135,9 @@ # warning "Large Non-DMA transfer may result in RX overrun failures" #elif defined(CONFIG_STM32H7_SDMMC1) # define SRAM123_START STM32_SRAM123_BASE -# define SRAM123_END (SRAM123_START + STM32H7_SRAM123_SIZE) +# define SRAM123_END (SRAM123_START + STM32_SRAM123_SIZE) # define SRAM4_START STM32_SRAM4_BASE -# define SRAM4_END (SRAM4_START + STM32H7_SRAM4_SIZE) +# define SRAM4_END (SRAM4_START + STM32_SRAM4_SIZE) #endif #if !defined(CONFIG_SCHED_WORKQUEUE) || !defined(CONFIG_SCHED_HPWORK) diff --git a/arch/arm/src/stm32h7/stm32_serial.c b/arch/arm/src/stm32h7/stm32_serial.c index 7860667a245..e7442fe452c 100644 --- a/arch/arm/src/stm32h7/stm32_serial.c +++ b/arch/arm/src/stm32h7/stm32_serial.c @@ -65,7 +65,7 @@ /* Total number of possible serial devices */ -#define STM32_NSERIAL (STM32H7_NUSART + STM32H7_NUART) +#define STM32_NSERIAL (STM32_NUSART + STM32_NUART) /* DMA configuration */ @@ -1952,7 +1952,7 @@ static void up_pm_setsuspend(bool suspend) g_serialpm.serial_suspended = suspend; - for (n = 0; n < STM32H7_NUSART + STM32H7_NUART; n++) + for (n = 0; n < STM32_NUSART + STM32_NUART; n++) { struct up_dev_s *priv = g_uart_devs[n]; @@ -3761,7 +3761,7 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain, * buffers. */ - for (n = 0; n < STM32H7_NUSART + STM32H7_NUART; n++) + for (n = 0; n < STM32_NUSART + STM32_NUART; n++) { struct up_dev_s *priv = g_uart_devs[n]; diff --git a/arch/arm/src/stm32h7/stm32_uart.h b/arch/arm/src/stm32h7/stm32_uart.h index 92234cb4c45..ea171109805 100644 --- a/arch/arm/src/stm32h7/stm32_uart.h +++ b/arch/arm/src/stm32h7/stm32_uart.h @@ -40,29 +40,29 @@ * device. */ -#if STM32H7_NUART < 4 +#if STM32_NUART < 4 # undef CONFIG_STM32H7_UART8 #endif -#if STM32H7_NUART < 3 +#if STM32_NUART < 3 # undef CONFIG_STM32H7_UART7 #endif -#if STM32H7_NUART < 2 +#if STM32_NUART < 2 # undef CONFIG_STM32H7_UART5 #endif -#if STM32H7_NUART < 1 +#if STM32_NUART < 1 # undef CONFIG_STM32H7_UART4 #endif -#if STM32H7_NUSART < 4 +#if STM32_NUSART < 4 # undef CONFIG_STM32H7_USART6 #endif -#if STM32H7_NUSART < 3 +#if STM32_NUSART < 3 # undef CONFIG_STM32H7_USART3 #endif -#if STM32H7_NUSART < 2 +#if STM32_NUSART < 2 # undef CONFIG_STM32H7_USART2 #endif -#if STM32H7_NUSART < 1 +#if STM32_NUSART < 1 # undef CONFIG_STM32H7_USART1 #endif diff --git a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c index a1ce272975b..5fb2cae9f94 100644 --- a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c +++ b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c @@ -408,36 +408,36 @@ static inline void rcc_enableahb4(void) /* Enable GPIO, GPIOB, ... GPIOK */ -#if STM32H7_NGPIO > 0 +#if STM32_NGPIO > 0 regval |= (RCC_AHB4ENR_GPIOAEN -#if STM32H7_NGPIO > 1 +#if STM32_NGPIO > 1 | RCC_AHB4ENR_GPIOBEN #endif -#if STM32H7_NGPIO > 2 +#if STM32_NGPIO > 2 | RCC_AHB4ENR_GPIOCEN #endif -#if STM32H7_NGPIO > 3 +#if STM32_NGPIO > 3 | RCC_AHB4ENR_GPIODEN #endif -#if STM32H7_NGPIO > 4 +#if STM32_NGPIO > 4 | RCC_AHB4ENR_GPIOEEN #endif -#if (STM32H7_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) +#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) | RCC_AHB4ENR_GPIOFEN #endif -#if (STM32H7_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) +#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) | RCC_AHB4ENR_GPIOGEN #endif -#if STM32H7_NGPIO > 7 +#if STM32_NGPIO > 7 | RCC_AHB4ENR_GPIOHEN #endif -#if STM32H7_NGPIO > 8 +#if STM32_NGPIO > 8 | RCC_AHB4ENR_GPIOIEN #endif -#if STM32H7_NGPIO > 9 +#if STM32_NGPIO > 9 | RCC_AHB4ENR_GPIOJEN #endif -#if STM32H7_NGPIO > 10 +#if STM32_NGPIO > 10 | RCC_AHB4ENR_GPIOKEN #endif ); diff --git a/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c index 2a032086236..481183e8ea5 100644 --- a/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c +++ b/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c @@ -383,36 +383,36 @@ static inline void rcc_enableahb4(void) /* Enable GPIO, GPIOB, ... GPIOK */ -#if STM32H7_NGPIO > 0 +#if STM32_NGPIO > 0 regval |= (RCC_AHB4ENR_GPIOAEN -#if STM32H7_NGPIO > 1 +#if STM32_NGPIO > 1 | RCC_AHB4ENR_GPIOBEN #endif -#if STM32H7_NGPIO > 2 +#if STM32_NGPIO > 2 | RCC_AHB4ENR_GPIOCEN #endif -#if STM32H7_NGPIO > 3 +#if STM32_NGPIO > 3 | RCC_AHB4ENR_GPIODEN #endif -#if STM32H7_NGPIO > 4 +#if STM32_NGPIO > 4 | RCC_AHB4ENR_GPIOEEN #endif -#if (STM32H7_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) +#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) | RCC_AHB4ENR_GPIOFEN #endif -#if (STM32H7_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) +#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) | RCC_AHB4ENR_GPIOGEN #endif -#if STM32H7_NGPIO > 7 +#if STM32_NGPIO > 7 | RCC_AHB4ENR_GPIOHEN #endif -#if STM32H7_NGPIO > 8 +#if STM32_NGPIO > 8 | RCC_AHB4ENR_GPIOIEN #endif -#if STM32H7_NGPIO > 9 +#if STM32_NGPIO > 9 | RCC_AHB4ENR_GPIOJEN #endif -#if STM32H7_NGPIO > 10 +#if STM32_NGPIO > 10 | RCC_AHB4ENR_GPIOKEN #endif );
