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commit 4982f5016e7cb56a1456945a70f7f7844c5b7e1a Author: raiden00pl <[email protected]> AuthorDate: Tue Jun 9 14:46:55 2026 +0200 !arch/stm32f7: unify non-standard hardware definition prefixes BREAKING CHANGE: STM32F7 non-standard hardware definition macros (IRQ, peripheral-count, SRAM and related) were renamed to the common STM32_* prefix. Out-of-tree code must update the affected references. Signed-off-by: raiden00pl <[email protected]> --- arch/arm/include/stm32f7/chip.h | 142 ++++++++++----------- arch/arm/src/stm32f7/hardware/stm32_qspi.h | 4 +- arch/arm/src/stm32f7/hardware/stm32_sai.h | 112 ++++++++-------- arch/arm/src/stm32f7/hardware/stm32f72xx73xx_adc.h | 6 +- .../arm/src/stm32f7/hardware/stm32f72xx73xx_gpio.h | 22 ++-- arch/arm/src/stm32f7/hardware/stm32f72xx73xx_spi.h | 12 +- arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h | 28 ++-- .../arm/src/stm32f7/hardware/stm32f72xx73xx_uart.h | 16 +-- .../arm/src/stm32f7/hardware/stm32f74xx75xx_gpio.h | 22 ++-- arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h | 28 ++-- arch/arm/src/stm32f7/hardware/stm32f74xx77xx_adc.h | 6 +- arch/arm/src/stm32f7/hardware/stm32f74xx77xx_i2c.h | 8 +- arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h | 12 +- .../arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h | 16 +-- .../arm/src/stm32f7/hardware/stm32f76xx77xx_gpio.h | 22 ++-- arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h | 28 ++-- arch/arm/src/stm32f7/stm32_allocateheap.c | 4 +- arch/arm/src/stm32f7/stm32_bbsram.c | 6 +- arch/arm/src/stm32f7/stm32_bbsram.h | 8 +- arch/arm/src/stm32f7/stm32_can.h | 2 +- arch/arm/src/stm32f7/stm32_can_sock.c | 2 +- arch/arm/src/stm32f7/stm32_config.h | 30 ++--- arch/arm/src/stm32f7/stm32_dma.c | 10 +- arch/arm/src/stm32f7/stm32_dumpgpio.c | 28 ++-- arch/arm/src/stm32f7/stm32_ethernet.c | 26 ++-- arch/arm/src/stm32f7/stm32_ethernet.h | 6 +- arch/arm/src/stm32f7/stm32_foc.c | 24 ++-- arch/arm/src/stm32f7/stm32_gpio.c | 30 ++--- arch/arm/src/stm32f7/stm32_gpio.h | 2 +- arch/arm/src/stm32f7/stm32_i2s.c | 18 +-- arch/arm/src/stm32f7/stm32_sai.c | 90 ++++++------- arch/arm/src/stm32f7/stm32_serial.c | 6 +- arch/arm/src/stm32f7/stm32_uart.h | 16 +-- arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c | 22 ++-- arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c | 22 ++-- arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c | 22 ++-- boards/arm/stm32f7/common/src/stm32_spitest.c | 6 +- boards/arm/stm32f7/nucleo-f722ze/src/stm32_adc.c | 6 +- .../arm/stm32f7/nucleo-f722ze/src/stm32_bbsram.c | 6 +- boards/arm/stm32f7/nucleo-f746zg/src/stm32_adc.c | 6 +- .../arm/stm32f7/nucleo-f746zg/src/stm32_bbsram.c | 6 +- boards/arm/stm32f7/nucleo-f767zi/src/stm32_adc.c | 6 +- .../arm/stm32f7/nucleo-f767zi/src/stm32_bbsram.c | 6 +- .../arm/stm32f7/stm32f746g-disco/include/board.h | 4 +- .../stm32f7/stm32f746g-disco/src/stm32_extmem.c | 2 +- .../stm32f7/stm32f769i-disco/src/stm32_extmem.c | 2 +- .../stm32f7/stm32f777zit6-meadow/include/board.h | 4 +- .../stm32f777zit6-meadow/src/stm32_extmem.c | 2 +- 48 files changed, 457 insertions(+), 457 deletions(-) diff --git a/arch/arm/include/stm32f7/chip.h b/arch/arm/include/stm32f7/chip.h index 5b2eb34fc1f..99047dd9757 100644 --- a/arch/arm/include/stm32f7/chip.h +++ b/arch/arm/include/stm32f7/chip.h @@ -265,43 +265,43 @@ /* Size SRAM */ #if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) -# define STM32F7_SRAM1_SIZE (176*1024) /* 176Kb SRAM1 on AHB bus Matrix */ -# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ +# define STM32_SRAM1_SIZE (176*1024) /* 176Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) -# define STM32F7_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM interface */ # else -# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ # endif # if defined(CONFIG_ARMV7M_HAVE_ITCM) -# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ # else -# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ # endif #elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) -# define STM32F7_SRAM1_SIZE (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */ -# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ +# define STM32_SRAM1_SIZE (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) -# define STM32F7_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM interface */ # else -# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ # endif # if defined(CONFIG_ARMV7M_HAVE_ITCM) -# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ # else -# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ # endif #elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) -# define STM32F7_SRAM1_SIZE (368*1024) /* 368Kb SRAM1 on AHB bus Matrix */ -# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ +# define STM32_SRAM1_SIZE (368*1024) /* 368Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) -# define STM32F7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ # else -# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ # endif # if defined(CONFIG_ARMV7M_HAVE_ITCM) -# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ # else -# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ # endif #else # error STM32 F7 chip Family not identified @@ -310,33 +310,33 @@ /* Common to all Advanced (vs Foundation) Family members */ #if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) -# define STM32F7_NSPDIFRX 0 /* Not supported */ -# define STM32F7_NGPIO 9 /* 9 GPIO ports, GPIOA-I */ -# define STM32F7_NI2C 3 /* I2C1-3 */ +# define STM32_NSPDIFRX 0 /* Not supported */ +# define STM32_NGPIO 9 /* 9 GPIO ports, GPIOA-I */ +# define STM32_NI2C 3 /* I2C1-3 */ #else -# define STM32F7_NSPDIFRX 4 /* 4 SPDIFRX inputs */ -# define STM32F7_NGPIO 11 /* 11 GPIO ports, GPIOA-K */ -# define STM32F7_NI2C 4 /* I2C1-4 */ +# define STM32_NSPDIFRX 4 /* 4 SPDIFRX inputs */ +# define STM32_NGPIO 11 /* 11 GPIO ports, GPIOA-K */ +# define STM32_NI2C 4 /* I2C1-4 */ #endif /* Common to all Family members */ -# define STM32F7_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32F7_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ -# define STM32F7_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ -# define STM32F7_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32F7_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32F7_NUART 4 /* UART 4-5 and 7-8 */ -# define STM32F7_NUSART 4 /* USART1-3 and 6 */ -# define STM32F7_NI2S 3 /* I2S1-2 (multiplexed with SPI1-3) */ -# define STM32F7_NUSBOTGFS 1 /* USB OTG FS */ -# define STM32F7_NUSBOTGHS 1 /* USB OTG HS */ -# define STM32F7_NSAI 2 /* SAI1-2 */ -# define STM32F7_NDMA 2 /* DMA1-2 */ -# define STM32F7_NADC 3 /* 12-bit ADC1-3, number of channels vary */ -# define STM32F7_NDAC 2 /* 12-bit DAC1-2 */ -# define STM32F7_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32F7_NCRC 1 /* CRC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NUART 4 /* UART 4-5 and 7-8 */ +# define STM32_NUSART 4 /* USART1-3 and 6 */ +# define STM32_NI2S 3 /* I2S1-2 (multiplexed with SPI1-3) */ +# define STM32_NUSBOTGFS 1 /* USB OTG FS */ +# define STM32_NUSBOTGHS 1 /* USB OTG HS */ +# define STM32_NSAI 2 /* SAI1-2 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NADC 3 /* 12-bit ADC1-3, number of channels vary */ +# define STM32_NDAC 2 /* 12-bit DAC1-2 */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ /* TBD FPU Configuration */ @@ -351,82 +351,82 @@ /* Diversification based on Family and package */ #if defined(CONFIG_STM32F7_HAVE_FMC) -# define STM32F7_NFMC 1 /* Have FMC memory controller */ +# define STM32_NFMC 1 /* Have FMC memory controller */ #else -# define STM32F7_NFMC 0 /* No FMC memory controller */ +# define STM32_NFMC 0 /* No FMC memory controller */ #endif #if defined(CONFIG_STM32F7_HAVE_ETHRNET) -# define STM32F7_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ #else -# define STM32F7_NETHERNET 0 /* No 100/100 Ethernet MAC */ +# define STM32_NETHERNET 0 /* No 100/100 Ethernet MAC */ #endif #if defined(CONFIG_STM32F7_HAVE_RNG) -# define STM32F7_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ #else -# define STM32F7_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ #endif #if defined(CONFIG_STM32F7_HAVE_SPI5) && defined(CONFIG_STM32F7_HAVE_SPI6) -# define STM32F7_NSPI 6 /* SPI1-6 (Advanced Family Except V series) */ +# define STM32_NSPI 6 /* SPI1-6 (Advanced Family Except V series) */ #elif defined(CONFIG_STM32F7_HAVE_SPI5) -# define STM32F7_NSPI 5 /* SPI1-5 (Foundation Family Except V & R series) */ +# define STM32_NSPI 5 /* SPI1-5 (Foundation Family Except V & R series) */ #elif defined(CONFIG_STM32F7_HAVE_SPI4) -# define STM32F7_NSPI 4 /* SPI1-4 V series */ +# define STM32_NSPI 4 /* SPI1-4 V series */ #else -# define STM32F7_NSPI 3 /* SPI1-3 R series */ +# define STM32_NSPI 3 /* SPI1-3 R series */ #endif #if defined(CONFIG_STM32F7_HAVE_SDMMC2) -# define STM32F7_NSDMMC 2 /* 2 SDMMC interfaces */ +# define STM32_NSDMMC 2 /* 2 SDMMC interfaces */ #else -# define STM32F7_NSDMMC 1 /* 1 SDMMC interface */ +# define STM32_NSDMMC 1 /* 1 SDMMC interface */ #endif #if defined(CONFIG_STM32F7_HAVE_CAN3) -# define STM32F7_NCAN 3 /* CAN1-3 */ +# define STM32_NCAN 3 /* CAN1-3 */ #elif defined(CONFIG_STM32F7_HAVE_CAN2) -# define STM32F7_NCAN 2 /* CAN1-2 */ +# define STM32_NCAN 2 /* CAN1-2 */ #else -# define STM32F7_NCAN 1 /* CAN1 only */ +# define STM32_NCAN 1 /* CAN1 only */ #endif #if defined(CONFIG_STM32F7_HAVE_DCMI) -# define STM32F7_NDCMI 1 /* Digital camera interface (DCMI) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ #else -# define STM32F7_NDCMI 0 /* No Digital camera interface (DCMI) */ +# define STM32_NDCMI 0 /* No Digital camera interface (DCMI) */ #endif #if defined(CONFIG_STM32F7_HAVE_DSIHOST) -# define STM32F7_NDSIHOST 1 /* Have MIPI DSI Host */ +# define STM32_NDSIHOST 1 /* Have MIPI DSI Host */ #else -# define STM32F7_NDSIHOST 0 /* No MIPI DSI Host */ +# define STM32_NDSIHOST 0 /* No MIPI DSI Host */ #endif #if defined (CONFIG_STM32F7_HAVE_LTDC) -# define STM32F7_NLCDTFT 1 /* One LCD-TFT */ +# define STM32_NLCDTFT 1 /* One LCD-TFT */ #else -# define STM32F7_NLCDTFT 0 /* No LCD-TFT */ +# define STM32_NLCDTFT 0 /* No LCD-TFT */ #endif #if defined(CONFIG_STM32F7_HAVE_DMA2D) /* bf20171107 Swapped defines they were reversed. */ -# define STM32F7_NDMA2D 1 /* DChrom-ART Accelerator™ (DMA2D) */ +# define STM32_NDMA2D 1 /* DChrom-ART Accelerator™ (DMA2D) */ #else -# define STM32F7_NDMA2D 0 /* No DChrom-ART Accelerator™ (DMA2D) */ +# define STM32_NDMA2D 0 /* No DChrom-ART Accelerator™ (DMA2D) */ #endif #if defined(CONFIG_STM32F7_HAVE_JPEG) -#define STM32F7_NJPEG 1 /* One JPEG Converter */ +#define STM32_NJPEG 1 /* One JPEG Converter */ #else -#define STM32F7_NJPEG 0 /* No JPEG Converter */ +#define STM32_NJPEG 0 /* No JPEG Converter */ #endif #if defined(CONFIG_STM32F7_HAVE_CRYP) -#define STM32F7_NCRYP 1 /* One CRYP engine */ +#define STM32_NCRYP 1 /* One CRYP engine */ #else -#define STM32F7_NCRYP 0 /* No CRYP engine */ +#define STM32_NCRYP 0 /* No CRYP engine */ #endif #if defined(CONFIG_STM32F7_HAVE_HASH) -#define STM32F7_NHASH 1 /* One HASH engine */ +#define STM32_NHASH 1 /* One HASH engine */ #else -#define STM32F7_NHASH 0 /* No HASH engine */ +#define STM32_NHASH 0 /* No HASH engine */ #endif #if defined(CONFIG_STM32F7_HAVE_DFSDM) -#define STM32F7_NDFSDM 4 /* One set of 4 Digital filters */ +#define STM32_NDFSDM 4 /* One set of 4 Digital filters */ #else -#define STM32F7_NDFSDM 0 /* No Digital filters */ +#define STM32_NDFSDM 0 /* No Digital filters */ #endif /* NVIC priority levels *****************************************************/ diff --git a/arch/arm/src/stm32f7/hardware/stm32_qspi.h b/arch/arm/src/stm32f7/hardware/stm32_qspi.h index 31cf04e8534..b857ca463b5 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_qspi.h +++ b/arch/arm/src/stm32f7/hardware/stm32_qspi.h @@ -38,8 +38,8 @@ /* General Characteristics **************************************************/ -#define STM32F7_QSPI_MINBITS 8 /* Minimum word width */ -#define STM32F7_QSPI_MAXBITS 32 /* Maximum word width */ +#define STM32_QSPI_MINBITS 8 /* Minimum word width */ +#define STM32_QSPI_MAXBITS 32 /* Maximum word width */ /* QSPI register offsets ****************************************************/ diff --git a/arch/arm/src/stm32f7/hardware/stm32_sai.h b/arch/arm/src/stm32f7/hardware/stm32_sai.h index c71d7adc87f..b9378498902 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_sai.h +++ b/arch/arm/src/stm32f7/hardware/stm32_sai.h @@ -36,67 +36,67 @@ /* Register Offsets *********************************************************/ -#define STM32F7_SAI_GCR_OFFSET 0x0000 /* SAI Global Configuration Register */ +#define STM32_SAI_GCR_OFFSET 0x0000 /* SAI Global Configuration Register */ -#define STM32F7_SAI_A_OFFSET 0x0004 -#define STM32F7_SAI_B_OFFSET 0x0024 +#define STM32_SAI_A_OFFSET 0x0004 +#define STM32_SAI_B_OFFSET 0x0024 -#define STM32F7_SAI_CR1_OFFSET 0x0000 /* SAI Configuration Register 1 A */ -#define STM32F7_SAI_CR2_OFFSET 0x0004 /* SAI Configuration Register 2 A */ -#define STM32F7_SAI_FRCR_OFFSET 0x0008 /* SAI Frame Configuration Register A */ -#define STM32F7_SAI_SLOTR_OFFSET 0x000c /* SAI Slot Register A */ -#define STM32F7_SAI_IM_OFFSET 0x0010 /* SAI Interrupt Mask Register 2 A */ -#define STM32F7_SAI_SR_OFFSET 0x0014 /* SAI Status Register A */ -#define STM32F7_SAI_CLRFR_OFFSET 0x0018 /* SAI Clear Flag Register A */ -#define STM32F7_SAI_DR_OFFSET 0x001c /* SAI Data Register A */ +#define STM32_SAI_CR1_OFFSET 0x0000 /* SAI Configuration Register 1 A */ +#define STM32_SAI_CR2_OFFSET 0x0004 /* SAI Configuration Register 2 A */ +#define STM32_SAI_FRCR_OFFSET 0x0008 /* SAI Frame Configuration Register A */ +#define STM32_SAI_SLOTR_OFFSET 0x000c /* SAI Slot Register A */ +#define STM32_SAI_IM_OFFSET 0x0010 /* SAI Interrupt Mask Register 2 A */ +#define STM32_SAI_SR_OFFSET 0x0014 /* SAI Status Register A */ +#define STM32_SAI_CLRFR_OFFSET 0x0018 /* SAI Clear Flag Register A */ +#define STM32_SAI_DR_OFFSET 0x001c /* SAI Data Register A */ /* Register Addresses *******************************************************/ -#define STM32F7_SAI1_GCR (STM32_SAI1_BASE+STM32F7_SAI_GCR_OFFSET) - -#define STM32F7_SAI1_A_BASE (STM32_SAI1_BASE+STM32F7_SAI_A_OFFSET) -#define STM32F7_SAI1_B_BASE (STM32_SAI1_BASE+STM32F7_SAI_B_OFFSET) - -#define STM32F7_SAI1_ACR1 (STM32F7_SAI1_A_BASE+STM32F7_SAI_CR1_OFFSET) -#define STM32F7_SAI1_ACR2 (STM32F7_SAI1_A_BASE+STM32F7_SAI_CR2_OFFSET) -#define STM32F7_SAI1_AFRCR (STM32F7_SAI1_A_BASE+STM32F7_SAI_FRCR_OFFSET) -#define STM32F7_SAI1_ASLOTR (STM32F7_SAI1_A_BASE+STM32F7_SAI_SLOTR_OFFSET) -#define STM32F7_SAI1_AIM (STM32F7_SAI1_A_BASE+STM32F7_SAI_IM_OFFSET) -#define STM32F7_SAI1_ASR (STM32F7_SAI1_A_BASE+STM32F7_SAI_SR_OFFSET) -#define STM32F7_SAI1_ACLRFR (STM32F7_SAI1_A_BASE+STM32F7_SAI_CLRFR_OFFSET) -#define STM32F7_SAI1_ADR (STM32F7_SAI1_A_BASE+STM32F7_SAI_DR_OFFSET) - -#define STM32F7_SAI1_BCR1 (STM32F7_SAI1_B_BASE+STM32F7_SAI_CR1_OFFSET) -#define STM32F7_SAI1_BCR2 (STM32F7_SAI1_B_BASE+STM32F7_SAI_CR2_OFFSET) -#define STM32F7_SAI1_BFRCR (STM32F7_SAI1_B_BASE+STM32F7_SAI_FRCR_OFFSET) -#define STM32F7_SAI1_BSLOTR (STM32F7_SAI1_B_BASE+STM32F7_SAI_SLOTR_OFFSET) -#define STM32F7_SAI1_BIM (STM32F7_SAI1_B_BASE+STM32F7_SAI_IM_OFFSET) -#define STM32F7_SAI1_BSR (STM32F7_SAI1_B_BASE+STM32F7_SAI_SR_OFFSET) -#define STM32F7_SAI1_BCLRFR (STM32F7_SAI1_B_BASE+STM32F7_SAI_CLRFR_OFFSET) -#define STM32F7_SAI1_BDR (STM32F7_SAI1_B_BASE+STM32F7_SAI_DR_OFFSET) - -#define STM32F7_SAI2_GCR (STM32_SAI2_BASE+STM32F7_SAI_GCR_OFFSET) - -#define STM32F7_SAI2_A_BASE (STM32_SAI2_BASE+STM32F7_SAI_A_OFFSET) -#define STM32F7_SAI2_B_BASE (STM32_SAI2_BASE+STM32F7_SAI_B_OFFSET) - -#define STM32F7_SAI2_ACR1 (STM32F7_SAI2_A_BASE+STM32F7_SAI_CR1_OFFSET) -#define STM32F7_SAI2_ACR2 (STM32F7_SAI2_A_BASE+STM32F7_SAI_CR2_OFFSET) -#define STM32F7_SAI2_AFRCR (STM32F7_SAI2_A_BASE+STM32F7_SAI_FRCR_OFFSET) -#define STM32F7_SAI2_ASLOTR (STM32F7_SAI2_A_BASE+STM32F7_SAI_SLOTR_OFFSET) -#define STM32F7_SAI2_AIM (STM32F7_SAI2_A_BASE+STM32F7_SAI_IM_OFFSET) -#define STM32F7_SAI2_ASR (STM32F7_SAI2_A_BASE+STM32F7_SAI_SR_OFFSET) -#define STM32F7_SAI2_ACLRFR (STM32F7_SAI2_A_BASE+STM32F7_SAI_CLRFR_OFFSET) -#define STM32F7_SAI2_ADR (STM32F7_SAI2_A_BASE+STM32F7_SAI_DR_OFFSET) - -#define STM32F7_SAI2_BCR1 (STM32F7_SAI2_B_BASE+STM32F7_SAI_CR1_OFFSET) -#define STM32F7_SAI2_BCR2 (STM32F7_SAI2_B_BASE+STM32F7_SAI_CR2_OFFSET) -#define STM32F7_SAI2_BFRCR (STM32F7_SAI2_B_BASE+STM32F7_SAI_FRCR_OFFSET) -#define STM32F7_SAI2_BSLOTR (STM32F7_SAI2_B_BASE+STM32F7_SAI_SLOTR_OFFSET) -#define STM32F7_SAI2_BIM (STM32F7_SAI2_B_BASE+STM32F7_SAI_IM_OFFSET) -#define STM32F7_SAI2_BSR (STM32F7_SAI2_B_BASE+STM32F7_SAI_SR_OFFSET) -#define STM32F7_SAI2_BCLRFR (STM32F7_SAI2_B_BASE+STM32F7_SAI_CLRFR_OFFSET) -#define STM32F7_SAI2_BDR (STM32F7_SAI2_B_BASE+STM32F7_SAI_DR_OFFSET) +#define STM32_SAI1_GCR (STM32_SAI1_BASE+STM32_SAI_GCR_OFFSET) + +#define STM32_SAI1_A_BASE (STM32_SAI1_BASE+STM32_SAI_A_OFFSET) +#define STM32_SAI1_B_BASE (STM32_SAI1_BASE+STM32_SAI_B_OFFSET) + +#define STM32_SAI1_ACR1 (STM32_SAI1_A_BASE+STM32_SAI_CR1_OFFSET) +#define STM32_SAI1_ACR2 (STM32_SAI1_A_BASE+STM32_SAI_CR2_OFFSET) +#define STM32_SAI1_AFRCR (STM32_SAI1_A_BASE+STM32_SAI_FRCR_OFFSET) +#define STM32_SAI1_ASLOTR (STM32_SAI1_A_BASE+STM32_SAI_SLOTR_OFFSET) +#define STM32_SAI1_AIM (STM32_SAI1_A_BASE+STM32_SAI_IM_OFFSET) +#define STM32_SAI1_ASR (STM32_SAI1_A_BASE+STM32_SAI_SR_OFFSET) +#define STM32_SAI1_ACLRFR (STM32_SAI1_A_BASE+STM32_SAI_CLRFR_OFFSET) +#define STM32_SAI1_ADR (STM32_SAI1_A_BASE+STM32_SAI_DR_OFFSET) + +#define STM32_SAI1_BCR1 (STM32_SAI1_B_BASE+STM32_SAI_CR1_OFFSET) +#define STM32_SAI1_BCR2 (STM32_SAI1_B_BASE+STM32_SAI_CR2_OFFSET) +#define STM32_SAI1_BFRCR (STM32_SAI1_B_BASE+STM32_SAI_FRCR_OFFSET) +#define STM32_SAI1_BSLOTR (STM32_SAI1_B_BASE+STM32_SAI_SLOTR_OFFSET) +#define STM32_SAI1_BIM (STM32_SAI1_B_BASE+STM32_SAI_IM_OFFSET) +#define STM32_SAI1_BSR (STM32_SAI1_B_BASE+STM32_SAI_SR_OFFSET) +#define STM32_SAI1_BCLRFR (STM32_SAI1_B_BASE+STM32_SAI_CLRFR_OFFSET) +#define STM32_SAI1_BDR (STM32_SAI1_B_BASE+STM32_SAI_DR_OFFSET) + +#define STM32_SAI2_GCR (STM32_SAI2_BASE+STM32_SAI_GCR_OFFSET) + +#define STM32_SAI2_A_BASE (STM32_SAI2_BASE+STM32_SAI_A_OFFSET) +#define STM32_SAI2_B_BASE (STM32_SAI2_BASE+STM32_SAI_B_OFFSET) + +#define STM32_SAI2_ACR1 (STM32_SAI2_A_BASE+STM32_SAI_CR1_OFFSET) +#define STM32_SAI2_ACR2 (STM32_SAI2_A_BASE+STM32_SAI_CR2_OFFSET) +#define STM32_SAI2_AFRCR (STM32_SAI2_A_BASE+STM32_SAI_FRCR_OFFSET) +#define STM32_SAI2_ASLOTR (STM32_SAI2_A_BASE+STM32_SAI_SLOTR_OFFSET) +#define STM32_SAI2_AIM (STM32_SAI2_A_BASE+STM32_SAI_IM_OFFSET) +#define STM32_SAI2_ASR (STM32_SAI2_A_BASE+STM32_SAI_SR_OFFSET) +#define STM32_SAI2_ACLRFR (STM32_SAI2_A_BASE+STM32_SAI_CLRFR_OFFSET) +#define STM32_SAI2_ADR (STM32_SAI2_A_BASE+STM32_SAI_DR_OFFSET) + +#define STM32_SAI2_BCR1 (STM32_SAI2_B_BASE+STM32_SAI_CR1_OFFSET) +#define STM32_SAI2_BCR2 (STM32_SAI2_B_BASE+STM32_SAI_CR2_OFFSET) +#define STM32_SAI2_BFRCR (STM32_SAI2_B_BASE+STM32_SAI_FRCR_OFFSET) +#define STM32_SAI2_BSLOTR (STM32_SAI2_B_BASE+STM32_SAI_SLOTR_OFFSET) +#define STM32_SAI2_BIM (STM32_SAI2_B_BASE+STM32_SAI_IM_OFFSET) +#define STM32_SAI2_BSR (STM32_SAI2_B_BASE+STM32_SAI_SR_OFFSET) +#define STM32_SAI2_BCLRFR (STM32_SAI2_B_BASE+STM32_SAI_CLRFR_OFFSET) +#define STM32_SAI2_BDR (STM32_SAI2_B_BASE+STM32_SAI_DR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_adc.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_adc.h index e02cfef5ecf..0c529af4b75 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_adc.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_adc.h @@ -64,7 +64,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NADC > 0 +#if STM32_NADC > 0 # define STM32_ADC1_SR (STM32_ADC1_BASE+STM32_ADC_SR_OFFSET) # define STM32_ADC1_CR1 (STM32_ADC1_BASE+STM32_ADC_CR1_OFFSET) # define STM32_ADC1_CR2 (STM32_ADC1_BASE+STM32_ADC_CR2_OFFSET) @@ -87,7 +87,7 @@ # define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET) #endif -#if STM32F7_NADC > 1 +#if STM32_NADC > 1 # define STM32_ADC2_SR (STM32_ADC2_BASE+STM32_ADC_SR_OFFSET) # define STM32_ADC2_CR1 (STM32_ADC2_BASE+STM32_ADC_CR1_OFFSET) # define STM32_ADC2_CR2 (STM32_ADC2_BASE+STM32_ADC_CR2_OFFSET) @@ -110,7 +110,7 @@ # define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET) #endif -#if STM32F7_NADC > 2 +#if STM32_NADC > 2 # define STM32_ADC3_SR (STM32_ADC3_BASE+STM32_ADC_SR_OFFSET) # define STM32_ADC3_CR1 (STM32_ADC3_BASE+STM32_ADC_CR1_OFFSET) # define STM32_ADC3_CR2 (STM32_ADC3_BASE+STM32_ADC_CR2_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_gpio.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_gpio.h index 07752be9bf5..bdb8128244c 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_gpio.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_gpio.h @@ -51,7 +51,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 # define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -64,7 +64,7 @@ # define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 # define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -77,7 +77,7 @@ # define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 # define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -90,7 +90,7 @@ # define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 # define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -103,7 +103,7 @@ # define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 # define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -116,7 +116,7 @@ # define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 # define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -129,7 +129,7 @@ # define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 # define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -142,7 +142,7 @@ # define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 # define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -155,7 +155,7 @@ # define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 # define STM32_GPIOI_MODER (STM32_GPIOI_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -168,7 +168,7 @@ # define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 # define STM32_GPIOJ_MODER (STM32_GPIOJ_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOJ_OTYPER (STM32_GPIOJ_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOJ_OSPEED (STM32_GPIOJ_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -181,7 +181,7 @@ # define STM32_GPIOJ_AFRH (STM32_GPIOJ_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 # define STM32_GPIOK_MODER (STM32_GPIOK_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOK_OTYPER (STM32_GPIOK_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOK_OSPEED (STM32_GPIOK_BASE+STM32_GPIO_OSPEED_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_spi.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_spi.h index cbcba08dbf4..00fe52c6f7c 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_spi.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_spi.h @@ -54,7 +54,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NSPI > 0 +#if STM32_NSPI > 0 # define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI1_SR (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET) @@ -64,7 +64,7 @@ # define STM32_SPI1_TXCRCR (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET) #endif -#if STM32F7_NSPI > 1 +#if STM32_NSPI > 1 # define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI2_SR (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET) @@ -76,7 +76,7 @@ # define STM32_SPI2_I2SPR (STM32_SPI2_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 2 +#if STM32_NSPI > 2 # define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI3_SR (STM32_SPI3_BASE+STM32_SPI_SR_OFFSET) @@ -88,7 +88,7 @@ # define STM32_SPI3_I2SPR (STM32_SPI3_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 3 +#if STM32_NSPI > 3 # define STM32_SPI4_CR1 (STM32_SPI4_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI4_CR2 (STM32_SPI4_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI4_SR (STM32_SPI4_BASE+STM32_SPI_SR_OFFSET) @@ -100,7 +100,7 @@ # define STM32_SPI4_I2SPR (STM32_SPI4_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 4 +#if STM32_NSPI > 4 # define STM32_SPI5_CR1 (STM32_SPI5_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI5_CR2 (STM32_SPI5_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI5_SR (STM32_SPI5_BASE+STM32_SPI_SR_OFFSET) @@ -112,7 +112,7 @@ # define STM32_SPI5_I2SPR (STM32_SPI5_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 5 +#if STM32_NSPI > 5 # define STM32_SPI6_CR1 (STM32_SPI6_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI6_CR2 (STM32_SPI6_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI6_SR (STM32_SPI6_BASE+STM32_SPI_SR_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h index d9d897fe1e3..5a3e8dbb1d4 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h @@ -97,7 +97,7 @@ /* Advanced Timers - TIM1 and TIM8 */ -#if STM32F7_NATIM > 0 +#if STM32_NATIM > 0 # define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET) # define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET) # define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET) @@ -123,7 +123,7 @@ # define STM32_TIM1_CCR6 (STM32_TIM1_BASE+STM32_ATIM_CCR6_OFFSET) #endif -#if STM32F7_NATIM > 1 +#if STM32_NATIM > 1 # define STM32_TIM8_CR1 (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET) # define STM32_TIM8_CR2 (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET) # define STM32_TIM8_SMCR (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET) @@ -153,7 +153,7 @@ * All timers are 16-bit except for TIM2 and 5 are 32-bit */ -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 0 +#if (STM32_NGTIM16+STM32_NGTIM32) > 0 # define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET) @@ -175,7 +175,7 @@ # define STM32_TIM2_OR (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 1 +#if (STM32_NGTIM16+STM32_NGTIM32) > 1 # define STM32_TIM3_CR1 (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM3_CR2 (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM3_SMCR (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET) @@ -196,7 +196,7 @@ # define STM32_TIM3_DMAR (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 2 +#if (STM32_NGTIM16+STM32_NGTIM32) > 2 # define STM32_TIM4_CR1 (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM4_CR2 (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM4_SMCR (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET) @@ -217,7 +217,7 @@ # define STM32_TIM4_DMAR (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 3 +#if (STM32_NGTIM16+STM32_NGTIM32) > 3 # define STM32_TIM5_CR1 (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM5_CR2 (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM5_SMCR (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET) @@ -244,7 +244,7 @@ * (2) TIM9 and TIM12 differ from the others. */ -#if STM32F7_NGTIMNDMA > 0 +#if STM32_NGTIMNDMA > 0 # define STM32_TIM9_CR1 (STM32_TIM9_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM9_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM9_DIER (STM32_TIM9_BASE+STM32_GTIM_DIER_OFFSET) @@ -259,7 +259,7 @@ # define STM32_TIM9_CCR2 (STM32_TIM9_BASE+STM32_GTIM_CCR2_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 1 +#if STM32_NGTIMNDMA > 1 # define STM32_TIM10_CR1 (STM32_TIM10_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM10_DIER (STM32_TIM10_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM10_SR (STM32_TIM10_BASE+STM32_GTIM_SR_OFFSET) @@ -272,7 +272,7 @@ # define STM32_TIM10_CCR1 (STM32_TIM10_BASE+STM32_GTIM_CCR1_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 2 +#if STM32_NGTIMNDMA > 2 # define STM32_TIM11_CR1 (STM32_TIM11_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM11_DIER (STM32_TIM11_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM11_SR (STM32_TIM11_BASE+STM32_GTIM_SR_OFFSET) @@ -286,7 +286,7 @@ # define STM32_TIM11_OR (STM32_TIM11_BASE+STM32_GTIM_OR_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 3 +#if STM32_NGTIMNDMA > 3 # define STM32_TIM12_CR1 (STM32_TIM12_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM12_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM12_DIER (STM32_TIM12_BASE+STM32_GTIM_DIER_OFFSET) @@ -301,7 +301,7 @@ # define STM32_TIM12_CCR2 (STM32_TIM12_BASE+STM32_GTIM_CCR2_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 4 +#if STM32_NGTIMNDMA > 4 # define STM32_TIM13_CR1 (STM32_TIM13_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM13_DIER (STM32_TIM13_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM13_SR (STM32_TIM13_BASE+STM32_GTIM_SR_OFFSET) @@ -314,7 +314,7 @@ # define STM32_TIM13_CCR1 (STM32_TIM13_BASE+STM32_GTIM_CCR1_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 5 +#if STM32_NGTIMNDMA > 5 # define STM32_TIM14_CR1 (STM32_TIM14_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM14_DIER (STM32_TIM14_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM14_SR (STM32_TIM14_BASE+STM32_GTIM_SR_OFFSET) @@ -329,7 +329,7 @@ /* Basic Timers - TIM6 and TIM7 */ -#if STM32F7_NBTIM > 0 +#if STM32_NBTIM > 0 # define STM32_TIM6_CR1 (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET) # define STM32_TIM6_CR2 (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET) # define STM32_TIM6_DIER (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET) @@ -340,7 +340,7 @@ # define STM32_TIM6_ARR (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET) #endif -#if STM32F7_NBTIM > 1 +#if STM32_NBTIM > 1 # define STM32_TIM7_CR1 (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET) # define STM32_TIM7_CR2 (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET) # define STM32_TIM7_DIER (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_uart.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_uart.h index 6473f22947b..5c73674d3d0 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_uart.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_uart.h @@ -51,7 +51,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NUSART > 0 +#if STM32_NUSART > 0 # define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) @@ -66,7 +66,7 @@ # define STM32_USART1_TDR (STM32_USART1_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUSART > 1 +#if STM32_NUSART > 1 # define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) @@ -81,7 +81,7 @@ # define STM32_USART2_TDR (STM32_USART2_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUSART > 2 +#if STM32_NUSART > 2 # define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) @@ -96,7 +96,7 @@ # define STM32_USART3_TDR (STM32_USART3_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUSART > 3 +#if STM32_NUSART > 3 # define STM32_USART6_CR1 (STM32_USART6_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART6_CR2 (STM32_USART6_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART6_CR3 (STM32_USART6_BASE+STM32_USART_CR3_OFFSET) @@ -111,7 +111,7 @@ # define STM32_USART6_TDR (STM32_USART6_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 0 +#if STM32_NUART > 0 # define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) @@ -126,7 +126,7 @@ # define STM32_UART4_TDR (STM32_UART4_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 1 +#if STM32_NUART > 1 # define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) @@ -141,7 +141,7 @@ # define STM32_UART5_TDR (STM32_UART5_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 2 +#if STM32_NUART > 2 # define STM32_UART7_CR1 (STM32_UART7_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART7_CR2 (STM32_UART7_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART7_CR3 (STM32_UART7_BASE+STM32_USART_CR3_OFFSET) @@ -156,7 +156,7 @@ # define STM32_UART7_TDR (STM32_UART7_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 3 +#if STM32_NUART > 3 # define STM32_UART8_CR1 (STM32_UART8_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART8_CR2 (STM32_UART8_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART8_CR3 (STM32_UART8_BASE+STM32_USART_CR3_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_gpio.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_gpio.h index 7d40fb94d08..eee436dc44f 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_gpio.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_gpio.h @@ -51,7 +51,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 # define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -64,7 +64,7 @@ # define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 # define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -77,7 +77,7 @@ # define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 # define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -90,7 +90,7 @@ # define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 # define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -103,7 +103,7 @@ # define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 # define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -116,7 +116,7 @@ # define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 # define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -129,7 +129,7 @@ # define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 # define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -142,7 +142,7 @@ # define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 # define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -155,7 +155,7 @@ # define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 # define STM32_GPIOI_MODER (STM32_GPIOI_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -168,7 +168,7 @@ # define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 # define STM32_GPIOJ_MODER (STM32_GPIOJ_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOJ_OTYPER (STM32_GPIOJ_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOJ_OSPEED (STM32_GPIOJ_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -181,7 +181,7 @@ # define STM32_GPIOJ_AFRH (STM32_GPIOJ_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 # define STM32_GPIOK_MODER (STM32_GPIOK_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOK_OTYPER (STM32_GPIOK_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOK_OSPEED (STM32_GPIOK_BASE+STM32_GPIO_OSPEED_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h index 44bea326903..f3144d3568d 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h @@ -97,7 +97,7 @@ /* Advanced Timers - TIM1 and TIM8 */ -#if STM32F7_NATIM > 0 +#if STM32_NATIM > 0 # define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET) # define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET) # define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET) @@ -123,7 +123,7 @@ # define STM32_TIM1_CCR6 (STM32_TIM1_BASE+STM32_ATIM_CCR6_OFFSET) #endif -#if STM32F7_NATIM > 1 +#if STM32_NATIM > 1 # define STM32_TIM8_CR1 (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET) # define STM32_TIM8_CR2 (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET) # define STM32_TIM8_SMCR (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET) @@ -153,7 +153,7 @@ * All timers are 16-bit except for TIM2 and 5 are 32-bit */ -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 0 +#if (STM32_NGTIM16+STM32_NGTIM32) > 0 # define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET) @@ -175,7 +175,7 @@ # define STM32_TIM2_OR (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 1 +#if (STM32_NGTIM16+STM32_NGTIM32) > 1 # define STM32_TIM3_CR1 (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM3_CR2 (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM3_SMCR (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET) @@ -196,7 +196,7 @@ # define STM32_TIM3_DMAR (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 2 +#if (STM32_NGTIM16+STM32_NGTIM32) > 2 # define STM32_TIM4_CR1 (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM4_CR2 (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM4_SMCR (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET) @@ -217,7 +217,7 @@ # define STM32_TIM4_DMAR (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 3 +#if (STM32_NGTIM16+STM32_NGTIM32) > 3 # define STM32_TIM5_CR1 (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM5_CR2 (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM5_SMCR (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET) @@ -244,7 +244,7 @@ * (2) TIM9 and TIM12 differ from the others. */ -#if STM32F7_NGTIMNDMA > 0 +#if STM32_NGTIMNDMA > 0 # define STM32_TIM9_CR1 (STM32_TIM9_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM9_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM9_DIER (STM32_TIM9_BASE+STM32_GTIM_DIER_OFFSET) @@ -259,7 +259,7 @@ # define STM32_TIM9_CCR2 (STM32_TIM9_BASE+STM32_GTIM_CCR2_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 1 +#if STM32_NGTIMNDMA > 1 # define STM32_TIM10_CR1 (STM32_TIM10_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM10_DIER (STM32_TIM10_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM10_SR (STM32_TIM10_BASE+STM32_GTIM_SR_OFFSET) @@ -272,7 +272,7 @@ # define STM32_TIM10_CCR1 (STM32_TIM10_BASE+STM32_GTIM_CCR1_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 2 +#if STM32_NGTIMNDMA > 2 # define STM32_TIM11_CR1 (STM32_TIM11_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM11_DIER (STM32_TIM11_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM11_SR (STM32_TIM11_BASE+STM32_GTIM_SR_OFFSET) @@ -286,7 +286,7 @@ # define STM32_TIM11_OR (STM32_TIM11_BASE+STM32_GTIM_OR_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 3 +#if STM32_NGTIMNDMA > 3 # define STM32_TIM12_CR1 (STM32_TIM12_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM12_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM12_DIER (STM32_TIM12_BASE+STM32_GTIM_DIER_OFFSET) @@ -301,7 +301,7 @@ # define STM32_TIM12_CCR2 (STM32_TIM12_BASE+STM32_GTIM_CCR2_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 4 +#if STM32_NGTIMNDMA > 4 # define STM32_TIM13_CR1 (STM32_TIM13_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM13_DIER (STM32_TIM13_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM13_SR (STM32_TIM13_BASE+STM32_GTIM_SR_OFFSET) @@ -314,7 +314,7 @@ # define STM32_TIM13_CCR1 (STM32_TIM13_BASE+STM32_GTIM_CCR1_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 5 +#if STM32_NGTIMNDMA > 5 # define STM32_TIM14_CR1 (STM32_TIM14_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM14_DIER (STM32_TIM14_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM14_SR (STM32_TIM14_BASE+STM32_GTIM_SR_OFFSET) @@ -329,7 +329,7 @@ /* Basic Timers - TIM6 and TIM7 */ -#if STM32F7_NBTIM > 0 +#if STM32_NBTIM > 0 # define STM32_TIM6_CR1 (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET) # define STM32_TIM6_CR2 (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET) # define STM32_TIM6_DIER (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET) @@ -340,7 +340,7 @@ # define STM32_TIM6_ARR (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET) #endif -#if STM32F7_NBTIM > 1 +#if STM32_NBTIM > 1 # define STM32_TIM7_CR1 (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET) # define STM32_TIM7_CR2 (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET) # define STM32_TIM7_DIER (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_adc.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_adc.h index 4d6e8e39878..8f2ede7053f 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_adc.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_adc.h @@ -64,7 +64,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NADC > 0 +#if STM32_NADC > 0 # define STM32_ADC1_SR (STM32_ADC1_BASE+STM32_ADC_SR_OFFSET) # define STM32_ADC1_CR1 (STM32_ADC1_BASE+STM32_ADC_CR1_OFFSET) # define STM32_ADC1_CR2 (STM32_ADC1_BASE+STM32_ADC_CR2_OFFSET) @@ -87,7 +87,7 @@ # define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET) #endif -#if STM32F7_NADC > 1 +#if STM32_NADC > 1 # define STM32_ADC2_SR (STM32_ADC2_BASE+STM32_ADC_SR_OFFSET) # define STM32_ADC2_CR1 (STM32_ADC2_BASE+STM32_ADC_CR1_OFFSET) # define STM32_ADC2_CR2 (STM32_ADC2_BASE+STM32_ADC_CR2_OFFSET) @@ -110,7 +110,7 @@ # define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET) #endif -#if STM32F7_NADC > 2 +#if STM32_NADC > 2 # define STM32_ADC3_SR (STM32_ADC3_BASE+STM32_ADC_SR_OFFSET) # define STM32_ADC3_CR1 (STM32_ADC3_BASE+STM32_ADC_CR1_OFFSET) # define STM32_ADC3_CR2 (STM32_ADC3_BASE+STM32_ADC_CR2_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_i2c.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_i2c.h index 0194d61ee74..a6417e0d4a8 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_i2c.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_i2c.h @@ -43,7 +43,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NI2C > 0 +#if STM32_NI2C > 0 # define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET) @@ -57,7 +57,7 @@ # define STM32_I2C1_TXDR (STM32_I2C1_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32F7_NI2C > 1 +#if STM32_NI2C > 1 # define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET) @@ -71,7 +71,7 @@ # define STM32_I2C2_TXDR (STM32_I2C2_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32F7_NI2C > 2 +#if STM32_NI2C > 2 # define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET) @@ -85,7 +85,7 @@ # define STM32_I2C3_TXDR (STM32_I2C3_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32F7_NI2C > 3 +#if STM32_NI2C > 3 # define STM32_I2C4_CR1 (STM32_I2C4_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C4_CR2 (STM32_I2C4_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C4_OAR1 (STM32_I2C4_BASE+STM32_I2C_OAR1_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h index dd0d8963188..946408d1916 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h @@ -58,7 +58,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NSPI > 0 +#if STM32_NSPI > 0 # define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI1_SR (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET) @@ -68,7 +68,7 @@ # define STM32_SPI1_TXCRCR (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET) #endif -#if STM32F7_NSPI > 1 +#if STM32_NSPI > 1 # define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI2_SR (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET) @@ -80,7 +80,7 @@ # define STM32_SPI2_I2SPR (STM32_SPI2_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 2 +#if STM32_NSPI > 2 # define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI3_SR (STM32_SPI3_BASE+STM32_SPI_SR_OFFSET) @@ -92,7 +92,7 @@ # define STM32_SPI3_I2SPR (STM32_SPI3_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 3 +#if STM32_NSPI > 3 # define STM32_SPI4_CR1 (STM32_SPI4_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI4_CR2 (STM32_SPI4_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI4_SR (STM32_SPI4_BASE+STM32_SPI_SR_OFFSET) @@ -104,7 +104,7 @@ # define STM32_SPI4_I2SPR (STM32_SPI4_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 4 +#if STM32_NSPI > 4 # define STM32_SPI5_CR1 (STM32_SPI5_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI5_CR2 (STM32_SPI5_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI5_SR (STM32_SPI5_BASE+STM32_SPI_SR_OFFSET) @@ -116,7 +116,7 @@ # define STM32_SPI5_I2SPR (STM32_SPI5_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 5 +#if STM32_NSPI > 5 # define STM32_SPI6_CR1 (STM32_SPI6_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI6_CR2 (STM32_SPI6_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI6_SR (STM32_SPI6_BASE+STM32_SPI_SR_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h index 6dfbba5177a..c996cd30768 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h @@ -52,7 +52,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NUSART > 0 +#if STM32_NUSART > 0 # define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) @@ -67,7 +67,7 @@ # define STM32_USART1_TDR (STM32_USART1_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUSART > 1 +#if STM32_NUSART > 1 # define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) @@ -82,7 +82,7 @@ # define STM32_USART2_TDR (STM32_USART2_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUSART > 2 +#if STM32_NUSART > 2 # define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) @@ -97,7 +97,7 @@ # define STM32_USART3_TDR (STM32_USART3_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUSART > 3 +#if STM32_NUSART > 3 # define STM32_USART6_CR1 (STM32_USART6_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART6_CR2 (STM32_USART6_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART6_CR3 (STM32_USART6_BASE+STM32_USART_CR3_OFFSET) @@ -112,7 +112,7 @@ # define STM32_USART6_TDR (STM32_USART6_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 0 +#if STM32_NUART > 0 # define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) @@ -127,7 +127,7 @@ # define STM32_UART4_TDR (STM32_UART4_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 1 +#if STM32_NUART > 1 # define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) @@ -142,7 +142,7 @@ # define STM32_UART5_TDR (STM32_UART5_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 2 +#if STM32_NUART > 2 # define STM32_UART7_CR1 (STM32_UART7_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART7_CR2 (STM32_UART7_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART7_CR3 (STM32_UART7_BASE+STM32_USART_CR3_OFFSET) @@ -157,7 +157,7 @@ # define STM32_UART7_TDR (STM32_UART7_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 3 +#if STM32_NUART > 3 # define STM32_UART8_CR1 (STM32_UART8_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART8_CR2 (STM32_UART8_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART8_CR3 (STM32_UART8_BASE+STM32_USART_CR3_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_gpio.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_gpio.h index dc769114062..370b090abd1 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_gpio.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_gpio.h @@ -51,7 +51,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 # define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -64,7 +64,7 @@ # define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 # define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -77,7 +77,7 @@ # define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 # define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -90,7 +90,7 @@ # define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 # define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -103,7 +103,7 @@ # define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 # define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -116,7 +116,7 @@ # define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 # define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -129,7 +129,7 @@ # define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 # define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -142,7 +142,7 @@ # define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 # define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -155,7 +155,7 @@ # define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 # define STM32_GPIOI_MODER (STM32_GPIOI_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -168,7 +168,7 @@ # define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 # define STM32_GPIOJ_MODER (STM32_GPIOJ_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOJ_OTYPER (STM32_GPIOJ_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOJ_OSPEED (STM32_GPIOJ_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -181,7 +181,7 @@ # define STM32_GPIOJ_AFRH (STM32_GPIOJ_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 # define STM32_GPIOK_MODER (STM32_GPIOK_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOK_OTYPER (STM32_GPIOK_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOK_OSPEED (STM32_GPIOK_BASE+STM32_GPIO_OSPEED_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h index fc2fa7bec81..b2586544aa4 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h @@ -99,7 +99,7 @@ /* Advanced Timers - TIM1 and TIM8 */ -#if STM32F7_NATIM > 0 +#if STM32_NATIM > 0 # define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET) # define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET) # define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET) @@ -127,7 +127,7 @@ # define STM32_TIM1_AF2 (STM32_TIM1_BASE+STM32_ATIM_AF2_OFFSET) #endif -#if STM32F7_NATIM > 1 +#if STM32_NATIM > 1 # define STM32_TIM8_CR1 (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET) # define STM32_TIM8_CR2 (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET) # define STM32_TIM8_SMCR (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET) @@ -159,7 +159,7 @@ * All timers are 16-bit except for TIM2 and 5 are 32-bit */ -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 0 +#if (STM32_NGTIM16+STM32_NGTIM32) > 0 # define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET) @@ -181,7 +181,7 @@ # define STM32_TIM2_OR (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 1 +#if (STM32_NGTIM16+STM32_NGTIM32) > 1 # define STM32_TIM3_CR1 (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM3_CR2 (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM3_SMCR (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET) @@ -202,7 +202,7 @@ # define STM32_TIM3_DMAR (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 2 +#if (STM32_NGTIM16+STM32_NGTIM32) > 2 # define STM32_TIM4_CR1 (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM4_CR2 (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM4_SMCR (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET) @@ -223,7 +223,7 @@ # define STM32_TIM4_DMAR (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 3 +#if (STM32_NGTIM16+STM32_NGTIM32) > 3 # define STM32_TIM5_CR1 (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM5_CR2 (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM5_SMCR (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET) @@ -250,7 +250,7 @@ * (2) TIM9 and TIM12 differ from the others. */ -#if STM32F7_NGTIMNDMA > 0 +#if STM32_NGTIMNDMA > 0 # define STM32_TIM9_CR1 (STM32_TIM9_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM9_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM9_DIER (STM32_TIM9_BASE+STM32_GTIM_DIER_OFFSET) @@ -265,7 +265,7 @@ # define STM32_TIM9_CCR2 (STM32_TIM9_BASE+STM32_GTIM_CCR2_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 1 +#if STM32_NGTIMNDMA > 1 # define STM32_TIM10_CR1 (STM32_TIM10_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM10_DIER (STM32_TIM10_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM10_SR (STM32_TIM10_BASE+STM32_GTIM_SR_OFFSET) @@ -278,7 +278,7 @@ # define STM32_TIM10_CCR1 (STM32_TIM10_BASE+STM32_GTIM_CCR1_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 2 +#if STM32_NGTIMNDMA > 2 # define STM32_TIM11_CR1 (STM32_TIM11_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM11_DIER (STM32_TIM11_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM11_SR (STM32_TIM11_BASE+STM32_GTIM_SR_OFFSET) @@ -292,7 +292,7 @@ # define STM32_TIM11_OR (STM32_TIM11_BASE+STM32_GTIM_OR_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 3 +#if STM32_NGTIMNDMA > 3 # define STM32_TIM12_CR1 (STM32_TIM12_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM12_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM12_DIER (STM32_TIM12_BASE+STM32_GTIM_DIER_OFFSET) @@ -307,7 +307,7 @@ # define STM32_TIM12_CCR2 (STM32_TIM12_BASE+STM32_GTIM_CCR2_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 4 +#if STM32_NGTIMNDMA > 4 # define STM32_TIM13_CR1 (STM32_TIM13_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM13_DIER (STM32_TIM13_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM13_SR (STM32_TIM13_BASE+STM32_GTIM_SR_OFFSET) @@ -320,7 +320,7 @@ # define STM32_TIM13_CCR1 (STM32_TIM13_BASE+STM32_GTIM_CCR1_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 5 +#if STM32_NGTIMNDMA > 5 # define STM32_TIM14_CR1 (STM32_TIM14_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM14_DIER (STM32_TIM14_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM14_SR (STM32_TIM14_BASE+STM32_GTIM_SR_OFFSET) @@ -335,7 +335,7 @@ /* Basic Timers - TIM6 and TIM7 */ -#if STM32F7_NBTIM > 0 +#if STM32_NBTIM > 0 # define STM32_TIM6_CR1 (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET) # define STM32_TIM6_CR2 (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET) # define STM32_TIM6_DIER (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET) @@ -346,7 +346,7 @@ # define STM32_TIM6_ARR (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET) #endif -#if STM32F7_NBTIM > 1 +#if STM32_NBTIM > 1 # define STM32_TIM7_CR1 (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET) # define STM32_TIM7_CR2 (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET) # define STM32_TIM7_DIER (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET) diff --git a/arch/arm/src/stm32f7/stm32_allocateheap.c b/arch/arm/src/stm32f7/stm32_allocateheap.c index 0991bcece13..47ac51b14ed 100644 --- a/arch/arm/src/stm32f7/stm32_allocateheap.c +++ b/arch/arm/src/stm32f7/stm32_allocateheap.c @@ -79,10 +79,10 @@ /* Set the start and end of SRAM1 and SRAM2 */ #define SRAM1_START STM32_SRAM1_BASE -#define SRAM1_END (SRAM1_START + STM32F7_SRAM1_SIZE) +#define SRAM1_END (SRAM1_START + STM32_SRAM1_SIZE) #define SRAM2_START STM32_SRAM2_BASE -#define SRAM2_END (SRAM2_START + STM32F7_SRAM2_SIZE) +#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) /* The STM32 F7 has DTCM memory */ diff --git a/arch/arm/src/stm32f7/stm32_bbsram.c b/arch/arm/src/stm32f7/stm32_bbsram.c index 36d92cc7de3..bdf2060127c 100644 --- a/arch/arm/src/stm32f7/stm32_bbsram.c +++ b/arch/arm/src/stm32f7/stm32_bbsram.c @@ -130,7 +130,7 @@ static int stm32_bbsram_unlink(struct inode *inode); ****************************************************************************/ #if defined(CONFIG_BBSRAM_DEBUG) -static uint8_t debug[STM32F7_BBSRAM_SIZE]; +static uint8_t debug[STM32_BBSRAM_SIZE]; #endif static const struct file_operations g_stm32_bbsram_fops = @@ -544,7 +544,7 @@ static int stm32_bbsram_ioctl(struct file *filep, int cmd, DEBUGASSERT(inode->i_private); bbr = inode->i_private; - if (cmd == STM32F7_BBSRAM_GETDESC_IOCTL) + if (cmd == STM32_BBSRAM_GETDESC_IOCTL) { struct bbsramd_s *bbrr = (struct bbsramd_s *)((uintptr_t)arg); @@ -627,7 +627,7 @@ static int stm32_bbsram_unlink(struct inode *inode) static int stm32_bbsram_probe(int *ent, struct stm32_bbsram_s pdev[]) { int i; - int avail = STM32F7_BBSRAM_SIZE; + int avail = STM32_BBSRAM_SIZE; int alloc; int size; int ret = -EFBIG; diff --git a/arch/arm/src/stm32f7/stm32_bbsram.h b/arch/arm/src/stm32f7/stm32_bbsram.h index 4d080578c4e..0eff55b26e1 100644 --- a/arch/arm/src/stm32f7/stm32_bbsram.h +++ b/arch/arm/src/stm32f7/stm32_bbsram.h @@ -46,7 +46,7 @@ #if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) -# define STM32F7_BBSRAM_SIZE 4096 +# define STM32_BBSRAM_SIZE 4096 #else # error "No backup SRAM on this STM32 Device" #endif @@ -55,11 +55,11 @@ # define CONFIG_STM32F7_BBSRAM_FILES 4 #endif -/* REVISIT: What guarantees that STM32F7_BBSRAM_GETDESC_IOCTL has a unique +/* REVISIT: What guarantees that STM32_BBSRAM_GETDESC_IOCTL has a unique * value among all over _DIOC() values? */ -#define STM32F7_BBSRAM_GETDESC_IOCTL _DIOC(0x0010) /* Returns a bbsramd_s */ +#define STM32_BBSRAM_GETDESC_IOCTL _DIOC(0x0010) /* Returns a bbsramd_s */ /**************************************************************************** * Public Types @@ -129,7 +129,7 @@ int stm32_bbsraminitialize(char *devpath, int *sizes); * Saves the panic context in a previously allocated BBSRAM file * * Parameters: - * fileno - the value returned by the ioctl STM32F7_BBSRAM_GETDESC_IOCTL + * fileno - the value returned by the ioctl STM32_BBSRAM_GETDESC_IOCTL * context - Pointer to a any array of bytes to save * length - The length of the data pointed to byt context * diff --git a/arch/arm/src/stm32f7/stm32_can.h b/arch/arm/src/stm32f7/stm32_can.h index 05dbe1e10c6..b9377f43389 100644 --- a/arch/arm/src/stm32f7/stm32_can.h +++ b/arch/arm/src/stm32f7/stm32_can.h @@ -151,4 +151,4 @@ int stm32_cansockinitialize(int port); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_CAN && (CONFIG_STM32_CAN1 || CONFIG_STM32_CAN2) */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_CAN_H */ +#endif /* __ARCH_ARM_SRC_STM32_STM32F7_CAN_H */ diff --git a/arch/arm/src/stm32f7/stm32_can_sock.c b/arch/arm/src/stm32f7/stm32_can_sock.c index c421e4c0e5e..e4e8f68da1d 100644 --- a/arch/arm/src/stm32f7/stm32_can_sock.c +++ b/arch/arm/src/stm32f7/stm32_can_sock.c @@ -729,7 +729,7 @@ static void stm32can_errint(struct stm32_can_s *priv, bool enable) } else { - regval &= ~STM32F7_CAN_ERRINT; + regval &= ~STM32_CAN_ERRINT; } stm32can_putreg(priv, STM32_CAN_IER_OFFSET, regval); diff --git a/arch/arm/src/stm32f7/stm32_config.h b/arch/arm/src/stm32f7/stm32_config.h index 9bec9e58704..c5a0cee3b6d 100644 --- a/arch/arm/src/stm32f7/stm32_config.h +++ b/arch/arm/src/stm32f7/stm32_config.h @@ -46,19 +46,19 @@ # undef CONFIG_STM32F7_GPIOE_IRQ #endif -#if STM32F7_NPORTS < 1 +#if STM32_NPORTS < 1 # undef CONFIG_STM32F7_GPIOA_IRQ #endif -#if STM32F7_NPORTS < 2 +#if STM32_NPORTS < 2 # undef CONFIG_STM32F7_GPIOB_IRQ #endif -#if STM32F7_NPORTS < 3 +#if STM32_NPORTS < 3 # undef CONFIG_STM32F7_GPIOC_IRQ #endif -#if STM32F7_NPORTS < 4 +#if STM32_NPORTS < 4 # undef CONFIG_STM32F7_GPIOD_IRQ #endif -#if STM32F7_NPORTS < 5 +#if STM32_NPORTS < 5 # undef CONFIG_STM32F7_GPIOE_IRQ #endif @@ -66,25 +66,25 @@ /* Don't enable UARTs not supported by the chip. */ -#if STM32F7_NUART < 1 +#if STM32_NUART < 1 # undef CONFIG_STM32F7_UART0 # undef CONFIG_STM32F7_UART1 # undef CONFIG_STM32F7_UART2 # undef CONFIG_STM32F7_UART3 # undef CONFIG_STM32F7_UART4 -#elif STM32F7_NUART < 2 +#elif STM32_NUART < 2 # undef CONFIG_STM32F7_UART1 # undef CONFIG_STM32F7_UART2 # undef CONFIG_STM32F7_UART3 # undef CONFIG_STM32F7_UART4 -#elif STM32F7_NUART < 3 +#elif STM32_NUART < 3 # undef CONFIG_STM32F7_UART2 # undef CONFIG_STM32F7_UART3 # undef CONFIG_STM32F7_UART4 -#elif STM32F7_NUART < 4 +#elif STM32_NUART < 4 # undef CONFIG_STM32F7_UART3 # undef CONFIG_STM32F7_UART4 -#elif STM32F7_NUART < 5 +#elif STM32_NUART < 5 # undef CONFIG_STM32F7_UART4 #endif @@ -115,14 +115,14 @@ /* Don't enable USARTs not supported by the chip. */ -#if STM32F7_NUSART < 1 +#if STM32_NUSART < 1 # undef CONFIG_STM32F7_USART0 # undef CONFIG_STM32F7_USART1 # undef CONFIG_STM32F7_USART2 -#elif STM32F7_NUSART < 2 +#elif STM32_NUSART < 2 # undef CONFIG_STM32F7_USART1 # undef CONFIG_STM32F7_USART2 -#elif STM32F7_NUSART < 3 +#elif STM32_NUSART < 3 # undef CONFIG_STM32F7_USART2 #endif @@ -158,8 +158,8 @@ /* Is there a serial console? There should be no more than one defined. * It could be on any: - * UARTn, n=1..STM32F7_NUART, or - * USARTn, n=1..STM32F7_NUSART + * UARTn, n=1..STM32_NUART, or + * USARTn, n=1..STM32_NUSART */ #undef HAVE_SERIAL_CONSOLE diff --git a/arch/arm/src/stm32f7/stm32_dma.c b/arch/arm/src/stm32f7/stm32_dma.c index 72e2d1f52d3..4b1df56c919 100644 --- a/arch/arm/src/stm32f7/stm32_dma.c +++ b/arch/arm/src/stm32f7/stm32_dma.c @@ -55,7 +55,7 @@ ****************************************************************************/ #define DMA1_NSTREAMS 8 -#if STM32F7_NDMA > 1 +#if STM32_NDMA > 1 # define DMA2_NSTREAMS 8 # define DMA_NSTREAMS (DMA1_NSTREAMS+DMA2_NSTREAMS) #else @@ -148,7 +148,7 @@ static struct stm32_dma_s g_dma[DMA_NSTREAMS] = .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(7), }, -#if STM32F7_NDMA > 1 +#if STM32_NDMA > 1 { .stream = 0, .irq = STM32_IRQ_DMA2S0, @@ -268,13 +268,13 @@ static inline struct stm32_dma_s *stm32_dmastream(unsigned int stream, { int index; - DEBUGASSERT(stream < DMA_NSTREAMS && controller < STM32F7_NDMA); + DEBUGASSERT(stream < DMA_NSTREAMS && controller < STM32_NDMA); /* Convert the controller + stream based on the fact that there are * 8 streams per controller. */ -#if STM32F7_NDMA > 1 +#if STM32_NDMA > 1 index = controller << 3 | stream; #else index = stream; @@ -376,7 +376,7 @@ static int stm32_dmainterrupt(int irq, void *context, void *arg) controller = DMA1; } else -#if STM32F7_NDMA > 1 +#if STM32_NDMA > 1 if (irq >= STM32_IRQ_DMA2S0 && irq <= STM32_IRQ_DMA2S4) { stream = irq - STM32_IRQ_DMA2S0; diff --git a/arch/arm/src/stm32f7/stm32_dumpgpio.c b/arch/arm/src/stm32f7/stm32_dumpgpio.c index bf70e68ec45..45820a0adca 100644 --- a/arch/arm/src/stm32f7/stm32_dumpgpio.c +++ b/arch/arm/src/stm32f7/stm32_dumpgpio.c @@ -54,31 +54,31 @@ /* Port letters for prettier debug output */ -static const char g_portchar[STM32F7_NGPIO] = +static const char g_portchar[STM32_NGPIO] = { -#if STM32F7_NGPIO > 11 +#if STM32_NGPIO > 11 # error "Additional support required for this number of GPIOs" -#elif STM32F7_NGPIO > 10 +#elif STM32_NGPIO > 10 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K' -#elif STM32F7_NGPIO > 9 +#elif STM32_NGPIO > 9 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J' -#elif STM32F7_NGPIO > 8 +#elif STM32_NGPIO > 8 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I' -#elif STM32F7_NGPIO > 7 +#elif STM32_NGPIO > 7 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' -#elif STM32F7_NGPIO > 6 +#elif STM32_NGPIO > 6 'A', 'B', 'C', 'D', 'E', 'F', 'G' -#elif STM32F7_NGPIO > 5 +#elif STM32_NGPIO > 5 'A', 'B', 'C', 'D', 'E', 'F' -#elif STM32F7_NGPIO > 4 +#elif STM32_NGPIO > 4 'A', 'B', 'C', 'D', 'E' -#elif STM32F7_NGPIO > 3 +#elif STM32_NGPIO > 3 'A', 'B', 'C', 'D' -#elif STM32F7_NGPIO > 2 +#elif STM32_NGPIO > 2 'A', 'B', 'C' -#elif STM32F7_NGPIO > 1 +#elif STM32_NGPIO > 1 'A', 'B' -#elif STM32F7_NGPIO > 0 +#elif STM32_NGPIO > 0 'A' #else # error "Bad number of GPIOs" @@ -112,7 +112,7 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg) flags = enter_critical_section(); - DEBUGASSERT(port < STM32F7_NGPIO); + DEBUGASSERT(port < STM32_NGPIO); gpioinfo("GPIO%c pinset: %08" PRIx32 " base: %08" PRIx32 " -- %s\n", g_portchar[port], pinset, base, msg); diff --git a/arch/arm/src/stm32f7/stm32_ethernet.c b/arch/arm/src/stm32f7/stm32_ethernet.c index 22c185ac8f8..668418a15ca 100644 --- a/arch/arm/src/stm32f7/stm32_ethernet.c +++ b/arch/arm/src/stm32f7/stm32_ethernet.c @@ -65,12 +65,12 @@ #include <arch/board/board.h> -/* STM32F7_NETHERNET determines the number of physical interfaces that can +/* STM32_NETHERNET determines the number of physical interfaces that can * be supported by the hardware. CONFIG_STM32F7_ETHMAC will defined if * any STM32F7 Ethernet support is enabled in the configuration. */ -#if STM32F7_NETHERNET > 0 && defined(CONFIG_STM32F7_ETHMAC) +#if STM32_NETHERNET > 0 && defined(CONFIG_STM32F7_ETHMAC) /**************************************************************************** * Pre-processor Definitions @@ -78,7 +78,7 @@ /* Configuration ************************************************************/ -#if STM32F7_NETHERNET > 1 +#if STM32_NETHERNET > 1 # error "Logic to support multiple Ethernet interfaces is incomplete" #endif @@ -243,14 +243,14 @@ #define TXDESC_PADSIZE DMA_ALIGN_UP(TXDESC_SIZE) #define ALIGNED_BUFSIZE DMA_ALIGN_UP(ETH_BUFSIZE) -#define RXTABLE_SIZE (STM32F7_NETHERNET * CONFIG_STM32F7_ETH_NRXDESC) -#define TXTABLE_SIZE (STM32F7_NETHERNET * CONFIG_STM32F7_ETH_NTXDESC) +#define RXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32F7_ETH_NRXDESC) +#define TXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32F7_ETH_NTXDESC) #define RXBUFFER_SIZE (CONFIG_STM32F7_ETH_NRXDESC * ALIGNED_BUFSIZE) -#define RXBUFFER_ALLOC (STM32F7_NETHERNET * RXBUFFER_SIZE) +#define RXBUFFER_ALLOC (STM32_NETHERNET * RXBUFFER_SIZE) #define TXBUFFER_SIZE (STM32_ETH_NFREEBUFFERS * ALIGNED_BUFSIZE) -#define TXBUFFER_ALLOC (STM32F7_NETHERNET * TXBUFFER_SIZE) +#define TXBUFFER_ALLOC (STM32_NETHERNET * TXBUFFER_SIZE) /* Extremely detailed register debug that you would normally never want * enabled. @@ -659,7 +659,7 @@ static uint8_t g_txbuffer[TXBUFFER_ALLOC] /* These are the pre-allocated Ethernet device structures */ -static struct stm32_ethmac_s g_stm32ethmac[STM32F7_NETHERNET]; +static struct stm32_ethmac_s g_stm32ethmac[STM32_NETHERNET]; /**************************************************************************** * Private Function Prototypes @@ -3899,7 +3899,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv) * ****************************************************************************/ -#if STM32F7_NETHERNET == 1 || defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET == 1 || defined(CONFIG_NETDEV_LATEINIT) static inline #endif int stm32_ethinitialize(int intf) @@ -3912,7 +3912,7 @@ int stm32_ethinitialize(int intf) /* Get the interface structure associated with this interface number. */ - DEBUGASSERT(intf < STM32F7_NETHERNET); + DEBUGASSERT(intf < STM32_NETHERNET); priv = &g_stm32ethmac[intf]; /* Initialize the driver structure */ @@ -3973,7 +3973,7 @@ int stm32_ethinitialize(int intf) * * Description: * This is the "standard" network initialization logic called from the - * low-level initialization logic in arm_initialize.c. If STM32F7_NETHERNET + * low-level initialization logic in arm_initialize.c. If STM32_NETHERNET * greater than one, then board specific logic will have to supply a * version of arm_netinitialize() that calls stm32_ethinitialize() with * the appropriate interface number. @@ -3988,11 +3988,11 @@ int stm32_ethinitialize(int intf) * ****************************************************************************/ -#if STM32F7_NETHERNET == 1 && !defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET == 1 && !defined(CONFIG_NETDEV_LATEINIT) void arm_netinitialize(void) { stm32_ethinitialize(0); } #endif -#endif /* STM32F7_NETHERNET > 0 && CONFIG_STM32F7_ETHMAC */ +#endif /* STM32_NETHERNET > 0 && CONFIG_STM32F7_ETHMAC */ diff --git a/arch/arm/src/stm32f7/stm32_ethernet.h b/arch/arm/src/stm32f7/stm32_ethernet.h index 26d0e98ab89..b33dd2a646d 100644 --- a/arch/arm/src/stm32f7/stm32_ethernet.h +++ b/arch/arm/src/stm32f7/stm32_ethernet.h @@ -31,7 +31,7 @@ #include "hardware/stm32_ethernet.h" -#if STM32F7_NETHERNET > 0 +#if STM32_NETHERNET > 0 #ifndef __ASSEMBLY__ /**************************************************************************** @@ -67,7 +67,7 @@ extern "C" * ****************************************************************************/ -#if STM32F7_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) int stm32_ethinitialize(int intf); #endif @@ -102,5 +102,5 @@ int stm32_phy_boardinitialize(int intf); #endif #endif /* __ASSEMBLY__ */ -#endif /* STM32F7_NETHERNET > 0 */ +#endif /* STM32_NETHERNET > 0 */ #endif /* __ARCH_ARM_SRC_STM32F7_STM32_ETHERNET_H */ diff --git a/arch/arm/src/stm32f7/stm32_foc.c b/arch/arm/src/stm32f7/stm32_foc.c index cddddee17d6..aeaea51aa19 100644 --- a/arch/arm/src/stm32f7/stm32_foc.c +++ b/arch/arm/src/stm32f7/stm32_foc.c @@ -376,9 +376,9 @@ /* ADC1 + ADC2 + ADC3 interrupt */ -#define STM32F7_IRQ_ADC1_FOC STM32_IRQ_ADC -#define STM32F7_IRQ_ADC2_FOC STM32_IRQ_ADC -#define STM32F7_IRQ_ADC3_FOC STM32_IRQ_ADC +#define STM32_IRQ_ADC1_FOC STM32_IRQ_ADC +#define STM32_IRQ_ADC2_FOC STM32_IRQ_ADC +#define STM32_IRQ_ADC3_FOC STM32_IRQ_ADC /* ADC common ***************************************************************/ @@ -392,38 +392,38 @@ #ifdef CONFIG_STM32F7_FOC_FOC0 # ifdef CONFIG_STM32F7_FOC_FOC0_ADC1 -# define FOC0_ADC_IRQ STM32F7_IRQ_ADC1_FOC +# define FOC0_ADC_IRQ STM32_IRQ_ADC1_FOC # define FOC0_ADC_CMN FOC_ADC1_CMN # endif # ifdef CONFIG_STM32F7_FOC_FOC0_ADC2 -# define FOC0_ADC_IRQ STM32F7_IRQ_ADC2_FOC +# define FOC0_ADC_IRQ STM32_IRQ_ADC2_FOC # define FOC0_ADC_CMN FOC_ADC2_CMN # endif # ifdef CONFIG_STM32F7_FOC_FOC0_ADC3 -# define FOC0_ADC_IRQ STM32F7_IRQ_ADC3_FOC +# define FOC0_ADC_IRQ STM32_IRQ_ADC3_FOC # define FOC0_ADC_CMN FOC_ADC3_CMN # endif # ifdef CONFIG_STM32F7_FOC_FOC0_ADC4 -# define FOC0_ADC_IRQ STM32F7_IRQ_ADC4_FOC +# define FOC0_ADC_IRQ STM32_IRQ_ADC4_FOC # define FOC0_ADC_CMN FOC_ADC4_CMN # endif #endif #ifdef CONFIG_STM32F7_FOC_FOC1 # ifdef CONFIG_STM32F7_FOC_FOC1_ADC1 -# define FOC1_ADC_IRQ STM32F7_IRQ_ADC1_FOC +# define FOC1_ADC_IRQ STM32_IRQ_ADC1_FOC # define FOC1_ADC_CMN FOC_ADC1_CMN # endif # ifdef CONFIG_STM32F7_FOC_FOC1_ADC2 -# define FOC1_ADC_IRQ STM32F7_IRQ_ADC2_FOC +# define FOC1_ADC_IRQ STM32_IRQ_ADC2_FOC # define FOC1_ADC_CMN FOC_ADC2_CMN # endif # ifdef CONFIG_STM32F7_FOC_FOC1_ADC3 -# define FOC1_ADC_IRQ STM32F7_IRQ_ADC3_FOC +# define FOC1_ADC_IRQ STM32_IRQ_ADC3_FOC # define FOC1_ADC_CMN FOC_ADC3_CMN # endif # ifdef CONFIG_STM32F7_FOC_FOC1_ADC4 -# define FOC1_ADC_IRQ STM32F7_IRQ_ADC4_FOC +# define FOC1_ADC_IRQ STM32_IRQ_ADC4_FOC # define FOC1_ADC_CMN FOC_ADC4_CMN # endif #endif @@ -772,7 +772,7 @@ void stm32_foc_sync_all(void) /* Store EGR register address */ - egr_reg[i] = foc_dev->pwm_base + STM32F7_GTIM_EGR_OFFSET; + egr_reg[i] = foc_dev->pwm_base + STM32_GTIM_EGR_OFFSET; } /* Write all registers at once */ diff --git a/arch/arm/src/stm32f7/stm32_gpio.c b/arch/arm/src/stm32f7/stm32_gpio.c index 0033faf47da..27455106e85 100644 --- a/arch/arm/src/stm32f7/stm32_gpio.c +++ b/arch/arm/src/stm32f7/stm32_gpio.c @@ -60,39 +60,39 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; /* Base addresses for each GPIO block */ -const uint32_t g_gpiobase[STM32F7_NGPIO] = +const uint32_t g_gpiobase[STM32_NGPIO] = { -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 STM32_GPIOA_BASE, #endif -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 STM32_GPIOB_BASE, #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 STM32_GPIOC_BASE, #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 STM32_GPIOD_BASE, #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 STM32_GPIOE_BASE, #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 STM32_GPIOF_BASE, #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 STM32_GPIOG_BASE, #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 STM32_GPIOH_BASE, #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 STM32_GPIOI_BASE, #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 STM32_GPIOJ_BASE, #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 STM32_GPIOK_BASE, #endif }; @@ -134,7 +134,7 @@ int stm32_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32F7_NGPIO) + if (port >= STM32_NGPIO) { return -EINVAL; } @@ -409,7 +409,7 @@ void stm32_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32F7_NGPIO) + if (port < STM32_NGPIO) { /* Get the port base address */ @@ -449,7 +449,7 @@ bool stm32_gpioread(uint32_t pinset) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32F7_NGPIO) + if (port < STM32_NGPIO) { /* Get the port base address */ diff --git a/arch/arm/src/stm32f7/stm32_gpio.h b/arch/arm/src/stm32f7/stm32_gpio.h index 00fee28b71a..97fcbc8dfaf 100644 --- a/arch/arm/src/stm32f7/stm32_gpio.h +++ b/arch/arm/src/stm32f7/stm32_gpio.h @@ -240,7 +240,7 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32F7_NGPIO]; +EXTERN const uint32_t g_gpiobase[STM32_NGPIO]; /**************************************************************************** * Public Function Prototypes diff --git a/arch/arm/src/stm32f7/stm32_i2s.c b/arch/arm/src/stm32f7/stm32_i2s.c index f6f6d0c0272..53b8e44da21 100644 --- a/arch/arm/src/stm32f7/stm32_i2s.c +++ b/arch/arm/src/stm32f7/stm32_i2s.c @@ -232,9 +232,9 @@ #endif #if CONFIG_STM32F7_I2S1_DATALEN == 8 -# define STM32F7_I2S1_DATAMASK 0 +# define STM32_I2S1_DATAMASK 0 #elif CONFIG_STM32F7_I2S1_DATALEN == 16 -# define STM32F7_I2S1_DATAMASK 1 +# define STM32_I2S1_DATAMASK 1 #elif CONFIG_STM32F7_I2S1_DATALEN < 8 || CONFIG_STM32F7_I2S1_DATALEN > 16 # error Invalid value for CONFIG_STM32F7_I2S1_DATALEN #else @@ -242,9 +242,9 @@ #endif #if CONFIG_STM32F7_I2S2_DATALEN == 8 -# define STM32F7_I2S2_DATAMASK 0 +# define STM32_I2S2_DATAMASK 0 #elif CONFIG_STM32F7_I2S2_DATALEN == 16 -# define STM32F7_I2S2_DATAMASK 1 +# define STM32_I2S2_DATAMASK 1 #elif CONFIG_STM32F7_I2S2_DATALEN < 8 || CONFIG_STM32F7_I2S2_DATALEN > 16 # error Invalid value for CONFIG_STM32F7_I2S2_DATALEN #else @@ -252,9 +252,9 @@ #endif #if CONFIG_STM32F7_I2S3_DATALEN == 8 -# define STM32F7_I2S3_DATAMASK 0 +# define STM32_I2S3_DATAMASK 0 #elif CONFIG_STM32F7_I2S3_DATALEN == 16 -# define STM32F7_I2S3_DATAMASK 1 +# define STM32_I2S3_DATAMASK 1 #elif CONFIG_STM32F7_I2S3_DATALEN < 8 || CONFIG_STM32F7_I2S3_DATALEN > 16 # error Invalid value for CONFIG_STM32F7_I2S3_DATALEN #else @@ -2486,7 +2486,7 @@ static void i2s1_configure(struct stm32_i2s_s *priv) priv->datalen = CONFIG_STM32F7_I2S1_DATALEN; #ifdef CONFIG_DEBUG - priv->align = STM32F7_I2S2_DATAMASK; + priv->align = STM32_I2S2_DATAMASK; #endif } #endif /* CONFIG_STM32F7_I2S1 */ @@ -2551,7 +2551,7 @@ static void i2s2_configure(struct stm32_i2s_s *priv) priv->datalen = CONFIG_STM32F7_I2S2_DATALEN; #ifdef CONFIG_DEBUG - priv->align = STM32F7_I2S2_DATAMASK; + priv->align = STM32_I2S2_DATAMASK; #endif } #endif /* CONFIG_STM32F7_I2S2 */ @@ -2616,7 +2616,7 @@ static void i2s3_configure(struct stm32_i2s_s *priv) priv->datalen = CONFIG_STM32F7_I2S3_DATALEN; #ifdef CONFIG_DEBUG - priv->align = STM32F7_I2S3_DATAMASK; + priv->align = STM32_I2S3_DATAMASK; #endif } #endif /* CONFIG_STM32F7_I2S3 */ diff --git a/arch/arm/src/stm32f7/stm32_sai.c b/arch/arm/src/stm32f7/stm32_sai.c index 3883278b6f3..c05e18fc7fe 100644 --- a/arch/arm/src/stm32f7/stm32_sai.c +++ b/arch/arm/src/stm32f7/stm32_sai.c @@ -107,14 +107,14 @@ #endif #ifdef CONFIG_STM32F7_SAI1 -#ifndef STM32F7_SAI1_FREQUENCY -# error "Please define STM32F7_SAI1_FREQUENCY in board.h" +#ifndef STM32_SAI1_FREQUENCY +# error "Please define STM32_SAI1_FREQUENCY in board.h" #endif #endif #ifdef CONFIG_STM32F7_SAI2 -#ifndef STM32F7_SAI2_FREQUENCY -# error "Please define STM32F7_SAI1_FREQUENCY in board.h" +#ifndef STM32_SAI2_FREQUENCY +# error "Please define STM32_SAI1_FREQUENCY in board.h" #endif #endif @@ -278,9 +278,9 @@ static const struct i2s_ops_s g_i2sops = static struct stm32f7_sai_s g_sai1a_priv = { .dev.ops = &g_i2sops, - .base = STM32F7_SAI1_A_BASE, + .base = STM32_SAI1_A_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32F7_SAI1_FREQUENCY, + .frequency = STM32_SAI1_FREQUENCY, #ifdef CONFIG_STM32F7_SAI1_A_SYNC_WITH_B .syncen = SAI_CR1_SYNCEN_INTERNAL, #else @@ -299,9 +299,9 @@ static struct stm32f7_sai_s g_sai1a_priv = static struct stm32f7_sai_s g_sai1b_priv = { .dev.ops = &g_i2sops, - .base = STM32F7_SAI1_B_BASE, + .base = STM32_SAI1_B_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32F7_SAI1_FREQUENCY, + .frequency = STM32_SAI1_FREQUENCY, #ifdef CONFIG_STM32F7_SAI1_B_SYNC_WITH_A .syncen = SAI_CR1_SYNCEN_INTERNAL, #else @@ -322,9 +322,9 @@ static struct stm32f7_sai_s g_sai1b_priv = static struct stm32f7_sai_s g_sai2a_priv = { .dev.ops = &g_i2sops, - .base = STM32F7_SAI2_A_BASE, + .base = STM32_SAI2_A_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32F7_SAI2_FREQUENCY, + .frequency = STM32_SAI2_FREQUENCY, #ifdef CONFIG_STM32F7_SAI2_A_SYNC_WITH_B .syncen = SAI_CR1_SYNCEN_INTERNAL, #else @@ -343,9 +343,9 @@ static struct stm32f7_sai_s g_sai2a_priv = static struct stm32f7_sai_s g_sai2b_priv = { .dev.ops = &g_i2sops, - .base = STM32F7_SAI2_B_BASE, + .base = STM32_SAI2_B_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32F7_SAI2_FREQUENCY, + .frequency = STM32_SAI2_FREQUENCY, #ifdef CONFIG_STM32F7_SAI2_B_SYNC_WITH_A .syncen = SAI_CR1_SYNCEN_INTERNAL, #else @@ -479,30 +479,30 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg) #if 0 i2sinfo("CR1:%08" PRIx32 " CR2:%08" PRIx32 " FRCR:%08" PRIx32 " SLOTR:%08" PRIx32 "\n", - sai_getreg(priv, STM32F7_SAI_CR1_OFFSET), - sai_getreg(priv, STM32F7_SAI_CR2_OFFSET), - sai_getreg(priv, STM32F7_SAI_FRCR_OFFSET), - sai_getreg(priv, STM32F7_SAI_SLOTR_OFFSET)); + sai_getreg(priv, STM32_SAI_CR1_OFFSET), + sai_getreg(priv, STM32_SAI_CR2_OFFSET), + sai_getreg(priv, STM32_SAI_FRCR_OFFSET), + sai_getreg(priv, STM32_SAI_SLOTR_OFFSET)); i2sinfo(" IM:%08" PRIx32 " SR:%08" PRIx32 " CLRFR:%08" PRIx32 "\n", - sai_getreg(priv, STM32F7_SAI_IM_OFFSET), - sai_getreg(priv, STM32F7_SAI_SR_OFFSET), - sai_getreg(priv, STM32F7_SAI_CLRFR_OFFSET)); + sai_getreg(priv, STM32_SAI_IM_OFFSET), + sai_getreg(priv, STM32_SAI_SR_OFFSET), + sai_getreg(priv, STM32_SAI_CLRFR_OFFSET)); #else /* GCR */ #ifdef CONFIG_STM32F7_SAI1 - uint32_t gcr = getreg32(STM32F7_SAI1_GCR); - i2sinfo("GCR: *%08x = %08" PRIx32 "\n", STM32F7_SAI1_GCR, gcr); + uint32_t gcr = getreg32(STM32_SAI1_GCR); + i2sinfo("GCR: *%08x = %08" PRIx32 "\n", STM32_SAI1_GCR, gcr); #else - uint32_t gcr = getreg32(STM32F7_SAI2_GCR); - i2sinfo("GCR: *%08x = %08" PRIx32 "\n", STM32F7_SAI2_GCR, gcr); + uint32_t gcr = getreg32(STM32_SAI2_GCR); + i2sinfo("GCR: *%08x = %08" PRIx32 "\n", STM32_SAI2_GCR, gcr); #endif /* CR1 */ - uint32_t cr1 = sai_getreg(priv, STM32F7_SAI_CR1_OFFSET); - i2sinfo("CR1: *%08" PRIx32 " = %08x\n", STM32F7_SAI_CR1_OFFSET, cr1); + uint32_t cr1 = sai_getreg(priv, STM32_SAI_CR1_OFFSET); + i2sinfo("CR1: *%08" PRIx32 " = %08x\n", STM32_SAI_CR1_OFFSET, cr1); uint32_t mode = (cr1 & SAI_CR1_MODE_MASK) >> SAI_CR1_MODE_SHIFT; const char *mode_string[] = @@ -584,8 +584,8 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg) /* CR2 */ - uint32_t cr2 = sai_getreg(priv, STM32F7_SAI_CR2_OFFSET); - i2sinfo("CR2: *%08x = %08" PRIx32 "\n", STM32F7_SAI_CR2_OFFSET, cr2); + uint32_t cr2 = sai_getreg(priv, STM32_SAI_CR2_OFFSET); + i2sinfo("CR2: *%08x = %08" PRIx32 "\n", STM32_SAI_CR2_OFFSET, cr2); uint32_t fth = (cr2 & SAI_CR2_FTH_MASK) >> SAI_CR2_FTH_SHIFT; const char *fth_string[] = { "FIFO empty", @@ -638,8 +638,8 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg) /* FRCR */ - uint32_t frcr = sai_getreg(priv, STM32F7_SAI_FRCR_OFFSET); - i2sinfo("FRCR: *%08x = %08" PRIx32 "\n", STM32F7_SAI_FRCR_OFFSET, frcr); + uint32_t frcr = sai_getreg(priv, STM32_SAI_FRCR_OFFSET); + i2sinfo("FRCR: *%08x = %08" PRIx32 "\n", STM32_SAI_FRCR_OFFSET, frcr); uint32_t frl = (frcr & SAI_FRCR_FRL_MASK) >> SAI_FRCR_FRL_SHIFT; i2sinfo("\t\tFRCR: FRL[7:0] = %d\n", frl); @@ -662,8 +662,8 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg) /* SLOTR */ - uint32_t slotr = sai_getreg(priv, STM32F7_SAI_SLOTR_OFFSET); - i2sinfo("SLOTR: *%08x = %08" PRIx32 "\n", STM32F7_SAI_SLOTR_OFFSET, slotr); + uint32_t slotr = sai_getreg(priv, STM32_SAI_SLOTR_OFFSET); + i2sinfo("SLOTR: *%08x = %08" PRIx32 "\n", STM32_SAI_SLOTR_OFFSET, slotr); uint32_t fboff = (slotr & SAI_SLOTR_FBOFF_MASK) >> SAI_SLOTR_FBOFF_SHIFT; i2sinfo("\t\tSLOTR: FBOFF[4:0] = %d\n", fboff); @@ -731,7 +731,7 @@ static void sai_mckdivider(struct stm32f7_sai_s *priv) mckdiv += 1; } - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_MCKDIV_MASK, + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MCKDIV_MASK, mckdiv << SAI_CR1_MCKDIV_SHIFT); } @@ -878,7 +878,7 @@ static int sai_dma_setup(struct stm32f7_sai_s *priv) DEBUGASSERT(ntransfers > 0); - stm32_dmasetup(priv->dma, priv->base + STM32F7_SAI_DR_OFFSET, + stm32_dmasetup(priv->dma, priv->base + STM32_SAI_DR_OFFSET, samp, ntransfers, priv->dma_ccr); /* Add the container to the list of active DMAs */ @@ -891,7 +891,7 @@ static int sai_dma_setup(struct stm32f7_sai_s *priv) /* Enable the transmitter */ - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); /* Start a watchdog to catch DMA timeouts */ @@ -1169,9 +1169,9 @@ static uint32_t sai_datawidth(struct i2s_dev_s *dev, int bits) return 0; } - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_DS_MASK, setbits); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_DS_MASK, setbits); - sai_modifyreg(priv, STM32F7_SAI_FRCR_OFFSET, + sai_modifyreg(priv, STM32_SAI_FRCR_OFFSET, SAI_FRCR_FSALL_MASK | SAI_FRCR_FRL_MASK, SAI_FRCR_FSALL(bits) | SAI_FRCR_FRL(bits * 2)); @@ -1244,7 +1244,7 @@ static int sai_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb, } mode = priv->syncen ? SAI_CR1_MODE_SLAVE_RX : SAI_CR1_MODE_MASTER_RX; - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); priv->rxenab = true; /* Add a reference to the audio buffer */ @@ -1344,7 +1344,7 @@ static int sai_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb, } mode = priv->syncen ? SAI_CR1_MODE_SLAVE_TX : SAI_CR1_MODE_MASTER_TX; - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); priv->txenab = true; /* Add a reference to the audio buffer */ @@ -1528,28 +1528,28 @@ static void sai_portinitialize(struct stm32f7_sai_s *priv) priv->dma = stm32_dmachannel(priv->dma_ch); DEBUGASSERT(priv->dma); - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, 0, SAI_CR1_DMAEN); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_DMAEN); #endif - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_SYNCEN_MASK, + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_SYNCEN_MASK, priv->syncen); - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, 0, SAI_CR1_OUTDRIV); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_OUTDRIV); - sai_modifyreg(priv, STM32F7_SAI_CR2_OFFSET, SAI_CR2_FTH_MASK, + sai_modifyreg(priv, STM32_SAI_CR2_OFFSET, SAI_CR2_FTH_MASK, SAI_CR2_FTH_1QF); - sai_modifyreg(priv, STM32F7_SAI_FRCR_OFFSET, + sai_modifyreg(priv, STM32_SAI_FRCR_OFFSET, SAI_FRCR_FSDEF | SAI_FRCR_FSPOL | SAI_FRCR_FSOFF, SAI_FRCR_FSDEF_CHID | SAI_FRCR_FSPOL_LOW | SAI_FRCR_FSOFF_BFB); - sai_modifyreg(priv, STM32F7_SAI_SLOTR_OFFSET, + sai_modifyreg(priv, STM32_SAI_SLOTR_OFFSET, SAI_SLOTR_NBSLOT_MASK | SAI_SLOTR_SLOTEN_MASK, SAI_SLOTR_NBSLOT(2) | SAI_SLOTR_SLOTEN_0 | SAI_SLOTR_SLOTEN_1); - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); sai_dump_regs(priv, "After initialization"); } diff --git a/arch/arm/src/stm32f7/stm32_serial.c b/arch/arm/src/stm32f7/stm32_serial.c index dd5a10c0ee0..c04b5eca680 100644 --- a/arch/arm/src/stm32f7/stm32_serial.c +++ b/arch/arm/src/stm32f7/stm32_serial.c @@ -64,7 +64,7 @@ /* Total number of possible serial devices */ -#define STM32_NSERIAL (STM32F7_NUSART + STM32F7_NUART) +#define STM32_NSERIAL (STM32_NUSART + STM32_NUART) /* DMA configuration */ @@ -1790,7 +1790,7 @@ static void up_pm_setsuspend(bool suspend) g_serialpm.serial_suspended = suspend; - for (n = 0; n < STM32F7_NUSART + STM32F7_NUART; n++) + for (n = 0; n < STM32_NUSART + STM32_NUART; n++) { struct up_dev_s *priv = g_uart_devs[n]; @@ -3565,7 +3565,7 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain, * buffers. */ - for (n = 0; n < STM32F7_NUSART + STM32F7_NUART; n++) + for (n = 0; n < STM32_NUSART + STM32_NUART; n++) { struct up_dev_s *priv = g_uart_devs[n]; diff --git a/arch/arm/src/stm32f7/stm32_uart.h b/arch/arm/src/stm32f7/stm32_uart.h index 447a020e51f..d65dbe36b2f 100644 --- a/arch/arm/src/stm32f7/stm32_uart.h +++ b/arch/arm/src/stm32f7/stm32_uart.h @@ -40,29 +40,29 @@ * device. */ -#if STM32F7_NUART < 4 +#if STM32_NUART < 4 # undef CONFIG_STM32F7_UART8 #endif -#if STM32F7_NUART < 3 +#if STM32_NUART < 3 # undef CONFIG_STM32F7_UART7 #endif -#if STM32F7_NUART < 2 +#if STM32_NUART < 2 # undef CONFIG_STM32F7_UART5 #endif -#if STM32F7_NUART < 1 +#if STM32_NUART < 1 # undef CONFIG_STM32F7_UART4 #endif -#if STM32F7_NUSART < 4 +#if STM32_NUSART < 4 # undef CONFIG_STM32F7_USART6 #endif -#if STM32F7_NUSART < 3 +#if STM32_NUSART < 3 # undef CONFIG_STM32F7_USART3 #endif -#if STM32F7_NUSART < 2 +#if STM32_NUSART < 2 # undef CONFIG_STM32F7_USART2 #endif -#if STM32F7_NUSART < 1 +#if STM32_NUSART < 1 # undef CONFIG_STM32F7_USART1 #endif diff --git a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c index 625c5917073..2633267d255 100644 --- a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c @@ -132,36 +132,36 @@ static inline void rcc_enableahb1(void) /* Enable GPIOA, GPIOB, .... GPIOI */ -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 regval |= (RCC_AHB1ENR_GPIOAEN -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 | RCC_AHB1ENR_GPIOBEN #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 | RCC_AHB1ENR_GPIOCEN #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 | RCC_AHB1ENR_GPIODEN #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 | RCC_AHB1ENR_GPIOEEN #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 | RCC_AHB1ENR_GPIOFEN #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 | RCC_AHB1ENR_GPIOGEN #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 | RCC_AHB1ENR_GPIOHEN #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 | RCC_AHB1ENR_GPIOIEN #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 | RCC_AHB1ENR_GPIOJEN #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 | RCC_AHB1ENR_GPIOKEN #endif ); diff --git a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c index a0f80c1a031..f2a51b9e306 100644 --- a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c @@ -134,36 +134,36 @@ static inline void rcc_enableahb1(void) /* Enable GPIOA, GPIOB, .... GPIOI */ -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 regval |= (RCC_AHB1ENR_GPIOAEN -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 | RCC_AHB1ENR_GPIOBEN #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 | RCC_AHB1ENR_GPIOCEN #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 | RCC_AHB1ENR_GPIODEN #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 | RCC_AHB1ENR_GPIOEEN #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 | RCC_AHB1ENR_GPIOFEN #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 | RCC_AHB1ENR_GPIOGEN #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 | RCC_AHB1ENR_GPIOHEN #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 | RCC_AHB1ENR_GPIOIEN #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 | RCC_AHB1ENR_GPIOJEN #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 | RCC_AHB1ENR_GPIOKEN #endif ); diff --git a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c index a497d7ccb85..d59a5729de6 100644 --- a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c @@ -142,36 +142,36 @@ static inline void rcc_enableahb1(void) /* Enable GPIOA, GPIOB, .... GPIOI */ -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 regval |= (RCC_AHB1ENR_GPIOAEN -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 | RCC_AHB1ENR_GPIOBEN #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 | RCC_AHB1ENR_GPIOCEN #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 | RCC_AHB1ENR_GPIODEN #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 | RCC_AHB1ENR_GPIOEEN #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 | RCC_AHB1ENR_GPIOFEN #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 | RCC_AHB1ENR_GPIOGEN #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 | RCC_AHB1ENR_GPIOHEN #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 | RCC_AHB1ENR_GPIOIEN #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 | RCC_AHB1ENR_GPIOJEN #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 | RCC_AHB1ENR_GPIOKEN #endif ); diff --git a/boards/arm/stm32f7/common/src/stm32_spitest.c b/boards/arm/stm32f7/common/src/stm32_spitest.c index f82b9b8fe64..51bf2d63ca6 100644 --- a/boards/arm/stm32f7/common/src/stm32_spitest.c +++ b/boards/arm/stm32f7/common/src/stm32_spitest.c @@ -127,7 +127,7 @@ int stm32_spidev_bus_test(void) return -ENODEV; } - /* Default SPI1 to STM32F7_SPI1_FREQ and mode */ + /* Default SPI1 to STM32_SPI1_FREQ and mode */ SPI_SETFREQUENCY(g_spi1, CONFIG_STM32F7_SPI1_TEST_FREQ); SPI_SETBITS(g_spi1, CONFIG_STM32F7_SPI1_TEST_BITS); @@ -145,7 +145,7 @@ int stm32_spidev_bus_test(void) return -ENODEV; } - /* Default SPI2 to STM32F7_SPI2_FREQ and mode */ + /* Default SPI2 to STM32_SPI2_FREQ and mode */ SPI_SETFREQUENCY(g_spi2, CONFIG_STM32F7_SPI2_TEST_FREQ); SPI_SETBITS(g_spi2, CONFIG_STM32F7_SPI2_TEST_BITS); @@ -163,7 +163,7 @@ int stm32_spidev_bus_test(void) return -ENODEV; } - /* Default SPI3 to STM32F7_SPI3_FREQ and mode */ + /* Default SPI3 to STM32_SPI3_FREQ and mode */ SPI_SETFREQUENCY(g_spi3, CONFIG_STM32F7_SPI3_TEST_FREQ); SPI_SETBITS(g_spi3, CONFIG_STM32F7_SPI3_TEST_BITS); diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_adc.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_adc.c index 11dab91d01c..96deea3ee98 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_adc.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_adc.c @@ -48,15 +48,15 @@ /* Up to 3 ADC interfaces are supported */ -#if STM32F7_NADC < 3 +#if STM32_NADC < 3 # undef CONFIG_STM32F7_ADC3 #endif -#if STM32F7_NADC < 2 +#if STM32_NADC < 2 # undef CONFIG_STM32F7_ADC2 #endif -#if STM32F7_NADC < 1 +#if STM32_NADC < 1 # undef CONFIG_STM32F7_ADC1 #endif diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bbsram.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bbsram.c index b9a578268f7..04b76397fdf 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bbsram.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bbsram.c @@ -76,7 +76,7 @@ #define BBSRAM_USED ((4*BBSRAM_HEADER_SIZE)+ \ (BBSRAM_SIZE_FN0+BBSRAM_SIZE_FN1+ \ BBSRAM_SIZE_FN2)) -#define BBSRAM_REAMINING (STM32F7_BBSRAM_SIZE-BBSRAM_USED) +#define BBSRAM_REAMINING (STM32_BBSRAM_SIZE-BBSRAM_USED) #if CONFIG_ARCH_INTERRUPTSTACK <= 3 # define BBSRAM_NUMBER_STACKS 1 #else @@ -265,7 +265,7 @@ typedef struct * Private Data ****************************************************************************/ -static uint8_t g_sdata[STM32F7_BBSRAM_SIZE]; +static uint8_t g_sdata[STM32_BBSRAM_SIZE]; /**************************************************************************** * Private Functions @@ -288,7 +288,7 @@ static int hardfault_get_desc(struct bbsramd_s *desc) } else { - ret = file_ioctl(&filestruct, STM32F7_BBSRAM_GETDESC_IOCTL, + ret = file_ioctl(&filestruct, STM32_BBSRAM_GETDESC_IOCTL, (unsigned long)((uintptr_t)desc)); file_close(&filestruct); diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_adc.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_adc.c index 76e270d40d3..7f79bebc84d 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_adc.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_adc.c @@ -48,15 +48,15 @@ /* Up to 3 ADC interfaces are supported */ -#if STM32F7_NADC < 3 +#if STM32_NADC < 3 # undef CONFIG_STM32F7_ADC3 #endif -#if STM32F7_NADC < 2 +#if STM32_NADC < 2 # undef CONFIG_STM32F7_ADC2 #endif -#if STM32F7_NADC < 1 +#if STM32_NADC < 1 # undef CONFIG_STM32F7_ADC1 #endif diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bbsram.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bbsram.c index e575a7f653d..7834ac832df 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bbsram.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bbsram.c @@ -76,7 +76,7 @@ #define BBSRAM_USED ((4*BBSRAM_HEADER_SIZE)+ \ (BBSRAM_SIZE_FN0+BBSRAM_SIZE_FN1+ \ BBSRAM_SIZE_FN2)) -#define BBSRAM_REAMINING (STM32F7_BBSRAM_SIZE-BBSRAM_USED) +#define BBSRAM_REAMINING (STM32_BBSRAM_SIZE-BBSRAM_USED) #if CONFIG_ARCH_INTERRUPTSTACK <= 3 # define BBSRAM_NUMBER_STACKS 1 #else @@ -265,7 +265,7 @@ typedef struct * Private Data ****************************************************************************/ -static uint8_t g_sdata[STM32F7_BBSRAM_SIZE]; +static uint8_t g_sdata[STM32_BBSRAM_SIZE]; /**************************************************************************** * Private Functions @@ -288,7 +288,7 @@ static int hardfault_get_desc(struct bbsramd_s *desc) } else { - ret = file_ioctl(&filestruct, STM32F7_BBSRAM_GETDESC_IOCTL, + ret = file_ioctl(&filestruct, STM32_BBSRAM_GETDESC_IOCTL, (unsigned long)((uintptr_t)desc)); file_close(&filestruct); diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_adc.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_adc.c index d8c2ca1239b..bf7d56c0c6b 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_adc.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_adc.c @@ -48,15 +48,15 @@ /* Up to 3 ADC interfaces are supported */ -#if STM32F7_NADC < 3 +#if STM32_NADC < 3 # undef CONFIG_STM32F7_ADC3 #endif -#if STM32F7_NADC < 2 +#if STM32_NADC < 2 # undef CONFIG_STM32F7_ADC2 #endif -#if STM32F7_NADC < 1 +#if STM32_NADC < 1 # undef CONFIG_STM32F7_ADC1 #endif diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bbsram.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bbsram.c index d1c7ab99d2d..31431f9d53d 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bbsram.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bbsram.c @@ -76,7 +76,7 @@ #define BBSRAM_USED ((4*BBSRAM_HEADER_SIZE)+ \ (BBSRAM_SIZE_FN0+BBSRAM_SIZE_FN1+ \ BBSRAM_SIZE_FN2)) -#define BBSRAM_REAMINING (STM32F7_BBSRAM_SIZE-BBSRAM_USED) +#define BBSRAM_REAMINING (STM32_BBSRAM_SIZE-BBSRAM_USED) #if CONFIG_ARCH_INTERRUPTSTACK <= 3 # define BBSRAM_NUMBER_STACKS 1 #else @@ -265,7 +265,7 @@ typedef struct * Private Data ****************************************************************************/ -static uint8_t g_sdata[STM32F7_BBSRAM_SIZE]; +static uint8_t g_sdata[STM32_BBSRAM_SIZE]; /**************************************************************************** * Private Functions @@ -288,7 +288,7 @@ static int hardfault_get_desc(struct bbsramd_s *desc) } else { - ret = file_ioctl(&filestruct, STM32F7_BBSRAM_GETDESC_IOCTL, + ret = file_ioctl(&filestruct, STM32_BBSRAM_GETDESC_IOCTL, (unsigned long)((uintptr_t)desc)); file_close(&filestruct); diff --git a/boards/arm/stm32f7/stm32f746g-disco/include/board.h b/boards/arm/stm32f7/stm32f746g-disco/include/board.h index b3904989749..0cd3f2c5624 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/include/board.h +++ b/boards/arm/stm32f7/stm32f746g-disco/include/board.h @@ -152,8 +152,8 @@ /* SAIx input frequency = 25 / M * N / Q / P * 25000000 / 25 * 192 / 2 / 1 */ -#define STM32F7_SAI1_FREQUENCY (49142857) -#define STM32F7_SAI2_FREQUENCY (49142857) +#define STM32_SAI1_FREQUENCY (49142857) +#define STM32_SAI2_FREQUENCY (49142857) /* Configure Dedicated Clock Configuration Register */ diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_extmem.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_extmem.c index 774f9204fb6..666181b3eb8 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_extmem.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_extmem.c @@ -61,7 +61,7 @@ # warning "FMC is not enabled" #endif -#if STM32F7_NGPIO < 7 +#if STM32_NGPIO < 7 # error "Required GPIO ports not enabled" #endif diff --git a/boards/arm/stm32f7/stm32f769i-disco/src/stm32_extmem.c b/boards/arm/stm32f7/stm32f769i-disco/src/stm32_extmem.c index 26ee7b72fd3..f0c45df93e3 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/src/stm32_extmem.c +++ b/boards/arm/stm32f7/stm32f769i-disco/src/stm32_extmem.c @@ -47,7 +47,7 @@ # warning "FMC is not enabled" #endif -#if STM32F7_NGPIO < 8 +#if STM32_NGPIO < 8 # error "Required GPIO ports not enabled" #endif diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h b/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h index 9f5fb71fe13..2b1cfc1a9f9 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h @@ -158,8 +158,8 @@ * 25000000 / 25 * 384 / 2 / 8 */ -#define STM32F7_SAI1_FREQUENCY (49142857) -#define STM32F7_SAI2_FREQUENCY (49142857) +#define STM32_SAI1_FREQUENCY (49142857) +#define STM32_SAI2_FREQUENCY (49142857) /* Configure Dedicated Clock Configuration Register */ diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_extmem.c b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_extmem.c index a73495f2e0c..25d4604116b 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_extmem.c +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_extmem.c @@ -47,7 +47,7 @@ # warning "FMC is not enabled" #endif -#if STM32F7_NGPIO < 6 +#if STM32_NGPIO < 6 # error "Required GPIO ports not enabled" #endif
